1 /*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file Netc_Eth_Ip_Irq.c
9 * @internal
10 *
11 * @addtogroup NETC_ETH_DRIVER NETC_ETH Driver
12 * @{
13 */
14
15 #ifdef __cplusplus
16 extern "C"{
17 #endif
18
19 /*==================================================================================================
20 * INCLUDE FILES
21 * 1) system and project includes
22 * 2) needed interfaces from external units
23 * 3) internal and external interfaces from this unit
24 ==================================================================================================*/
25 #include "Netc_Eth_Ip.h"
26 #include "Netc_Eth_Ip_Irq.h"
27 #if(NETC_ETH_IP_DEV_ERROR_DETECT == STD_ON)
28 #include "Devassert.h"
29 #endif
30
31 /*==================================================================================================
32 * SOURCE FILE VERSION INFORMATION
33 ==================================================================================================*/
34 #define NETC_ETH_IP_IRQ_VENDOR_ID_C 43
35 #define NETC_ETH_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C 4
36 #define NETC_ETH_IP_IRQ_AR_RELEASE_MINOR_VERSION_C 7
37 #define NETC_ETH_IP_IRQ_AR_RELEASE_REVISION_VERSION_C 0
38 #define NETC_ETH_IP_IRQ_SW_MAJOR_VERSION_C 2
39 #define NETC_ETH_IP_IRQ_SW_MINOR_VERSION_C 0
40 #define NETC_ETH_IP_IRQ_SW_PATCH_VERSION_C 0
41
42 /*==================================================================================================
43 * FILE VERSION CHECKS
44 ==================================================================================================*/
45 /* Checks against NETC_ETH_IP_IRQ.h */
46 #if (NETC_ETH_IP_IRQ_VENDOR_ID_C != NETC_ETH_IP_VENDOR_ID)
47 #error "Netc_Eth_Ip.c and Netc_Eth_Ip.h have different vendor ids"
48 #endif
49 #if ((NETC_ETH_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != NETC_ETH_IP_AR_RELEASE_MAJOR_VERSION) || \
50 (NETC_ETH_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != NETC_ETH_IP_AR_RELEASE_MINOR_VERSION) || \
51 (NETC_ETH_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != NETC_ETH_IP_AR_RELEASE_REVISION_VERSION))
52 #error "AUTOSAR Version Numbers of Netc_Eth_Ip.c and Netc_Eth_Ip.h are different"
53 #endif
54 #if ((NETC_ETH_IP_IRQ_SW_MAJOR_VERSION_C != NETC_ETH_IP_SW_MAJOR_VERSION) || \
55 (NETC_ETH_IP_IRQ_SW_MINOR_VERSION_C != NETC_ETH_IP_SW_MINOR_VERSION) || \
56 (NETC_ETH_IP_IRQ_SW_PATCH_VERSION_C != NETC_ETH_IP_SW_PATCH_VERSION) \
57 )
58 #error "Software Version Numbers of Netc_Eth_Ip.c and Netc_Eth_Ip.h are different"
59 #endif
60
61 /* Checks against NETC_ETH_IP_IRQ.h */
62 #if (NETC_ETH_IP_IRQ_VENDOR_ID_C != NETC_ETH_IP_IRQ_VENDOR_ID)
63 #error "Netc_Eth_Ip.c and Netc_Eth_Ip.h have different vendor ids"
64 #endif
65 #if ((NETC_ETH_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != NETC_ETH_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \
66 (NETC_ETH_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != NETC_ETH_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \
67 (NETC_ETH_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != NETC_ETH_IP_IRQ_AR_RELEASE_REVISION_VERSION))
68 #error "AUTOSAR Version Numbers of Netc_Eth_Ip.c and Netc_Eth_Ip.h are different"
69 #endif
70 #if ((NETC_ETH_IP_IRQ_SW_MAJOR_VERSION_C != NETC_ETH_IP_IRQ_SW_MAJOR_VERSION) || \
71 (NETC_ETH_IP_IRQ_SW_MINOR_VERSION_C != NETC_ETH_IP_IRQ_SW_MINOR_VERSION) || \
72 (NETC_ETH_IP_IRQ_SW_PATCH_VERSION_C != NETC_ETH_IP_IRQ_SW_PATCH_VERSION) \
73 )
74 #error "Software Version Numbers of Netc_Eth_Ip.c and Netc_Eth_Ip.h are different"
75 #endif
76 /*==================================================================================================
77 * GLOBAL CONSTANTS
78 ==================================================================================================*/
79 #define ETH_43_NETC_START_SEC_VAR_INIT_UNSPECIFIED
80 #include "Eth_43_NETC_MemMap.h"
81
82 extern Netc_Eth_Ip_VfBaseType *netcVFBase[FEATURE_NETC_ETH_NUMBER_OF_CTRLS];
83
84 #define ETH_43_NETC_STOP_SEC_VAR_INIT_UNSPECIFIED
85 #include "Eth_43_NETC_MemMap.h"
86
87 /*==================================================================================================
88 * GLOBAL VARIABLES
89 ==================================================================================================*/
90
91 /* Pointer to each SI base. */
92 extern Netc_Eth_Ip_SiBaseType *netcSIsBase[8U];
93
94 /*==================================================================================================
95 * LOCAL FUNCTION PROTOTYPES
96 ==================================================================================================*/
97 /**
98 * @brief
99 *
100 * @param CtrlIndex
101 */
102 static inline void Netc_Eth_Ip_MSIX_Tx(uint8 CtrlIndex);
103
104 /**
105 * @brief
106 *
107 * @param TxRingIntStatus
108 * @param CtrlIndex
109 */
110 static inline void Netc_Eth_Ip_MSIX_Tx_CheckAllRings(const uint32 TxRingIntStatus, const uint8 CtrlIndex);
111
112 /**
113 * @brief
114 *
115 * @param CtrlIndex
116 */
117 void Netc_Eth_Ip_MSIX_Rx(uint8 CtrlIndex);
118
119 /**
120 * @brief Local function used to process PSI Message Receive event
121 *
122 * @param CmdMacReceivedAddr
123 * @param VSIIndex
124 */
125 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsi_Mac_Addr_Set(const Netc_Eth_Ip_VsiToPsiMsgType* const CmdMacReceivedAddr, uint8 VSIIndex);
126
127 /**
128 * @brief Local function used to process PSI Message Receive event
129 *
130 * @param CmdMacReceivedAddr
131 * @param VSIIndex
132 */
133 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsi_Add_Rx_Mac_Addr_Filter(const Netc_Eth_Ip_VsiToPsiMsgType* const CmdMacReceivedAddr, uint8 VSIIndex);
134
135 /**
136 * @brief Local function used to process PSI Message Receive event
137 *
138 * @param CmdMacReceivedAddr
139 * @param VSIIndex
140 */
141 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsi_Delete_Rx_Mac_Addr_Filter(const Netc_Eth_Ip_VsiToPsiMsgType* const CmdMacReceivedAddr, uint8 VSIIndex);
142
143
144 /**
145 * @brief Local function used to process PSI Message Receive event
146 *
147 * @param VSIIndex
148 */
149 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsi_Enable_Multicast(uint8 VSIIndex);
150
151 /**
152 * @brief Local function used to process PSI Message Receive event
153 *
154 * @param VSIIndex
155 */
156 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsi_Disable_Multicast(uint8 VSIIndex);
157
158 /**
159 * @brief Local function used to process PSI Message Receive event
160 *
161 * @param VSIIndex
162 */
163 static inline void Netc_Eth_Ip_VsiToPsi_Close_Filter(uint8 VSIIndex);
164
165 /**
166 * @brief Local function used to process PSI Message Receive event
167 *
168 * @param
169 */
170 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_Get_Sync_State(void);
171
172
173 /**
174 * @brief Local function used to process PSI Message Receive event
175 *
176 * @param VSIIndex
177 */
178 static inline void Netc_Eth_Ip_ProcessMsgRcv(uint8 VSIIndex);
179
180 /**
181 * @brief Local function used to re-initialize the VSI after a Function Level Reset event
182 *
183 * @param VSIIndex
184 */
185 static inline void Netc_Eth_Ip_InitVSIAfterFlr(uint8 VSIIndex);
186
187 /*==================================================================================================
188 * LOCAL FUNCTIONS
189 ==================================================================================================*/
190 /***************************************************************************
191 * implements Netc_Eth_Ip_MSIX_Tx_Activity
192 ***************************************************************************/
Netc_Eth_Ip_MSIX_Tx(uint8 CtrlIndex)193 static inline void Netc_Eth_Ip_MSIX_Tx(uint8 CtrlIndex)
194 {
195 uint32 TxRingIntStatus = netcSIsBase[CtrlIndex]->SITXIDR0;
196 /*
197 * Checking the first queue Interrupt Enable flag
198 * In order to fulfill requirement CPR_RTD_00664, the interrupt enable flag for the first queue is checked for the following reasons:
199 * 1. The interrupts are enabled at controller level, therefore if one queue has the interrupt enabled, then all of the queues will have it.
200 * 2. In ETH driver case, the queues are mandatory configured in order, so that the first queue enables the interrupt, then all of the queues will have the interrupt enable flag set
201 * 3. Performance reason: one check vs no.of queues checks
202 */
203 if(NETC_ETH_IP_TBIER_TXFIE_MASK == (netcSIsBase[CtrlIndex]->BDR_NUM[0U].TBIER & NETC_ETH_IP_TBIER_TXFIE_MASK))
204 {
205 /* Clear TX interrupt flag for all SIs. */
206 netcSIsBase[CtrlIndex]->SITXIDR0 = TxRingIntStatus;
207 /* The flags for frame interrupt are allocated in the upper 16 bits of the register,
208 shift them in the lower part. */
209 TxRingIntStatus >>= 16UL;
210 Netc_Eth_Ip_MSIX_Tx_CheckAllRings(TxRingIntStatus, CtrlIndex);
211 }
212 else if(NETC_ETH_IP_TBIER_TXTIE_MASK == (netcSIsBase[CtrlIndex]->BDR_NUM[0U].TBIER & NETC_ETH_IP_TBIER_TXTIE_MASK))
213 {
214 /* Clear TX interrupt flag for all SIs. */
215 netcSIsBase[CtrlIndex]->SITXIDR0 = TxRingIntStatus;
216 /* Keep only coalescing interrupt status. */
217 TxRingIntStatus &= 0x0000FFFFUL;
218 Netc_Eth_Ip_MSIX_Tx_CheckAllRings(TxRingIntStatus, CtrlIndex);
219 }
220 else
221 {
222 /* MISRA C-2012 Rule 15.7 */
223 }
224
225 }
226
227 /***************************************************************************
228 * implements Netc_Eth_Ip_MSIX_Rx_Activity
229 ***************************************************************************/
Netc_Eth_Ip_MSIX_Rx(uint8 CtrlIndex)230 void Netc_Eth_Ip_MSIX_Rx(uint8 CtrlIndex)
231 {
232 uint8 RingIndex;
233 uint32 interruptStatus = netcSIsBase[CtrlIndex]->SIRXIDR0;
234 /*
235 * Checking the first queue Interrupt Enable flag
236 * In order to fulfill requirement CPR_RTD_00664, the interrupt enable flag for the first queue is checked for the following reasons:
237 * 1. The interrupts are enabled at controller level, therefore if one queue has the interrupt enabled, then all of the queues will have it.
238 * 2. In ETH driver case, the queues are mandatory configured in order, so that the first queue enables the interrupt, then all of the queues will have the interrupt enable flag set
239 * 3. Performance reason: one check vs no.of queues checks
240 */
241 if (NETC_ETH_IP_RBIER_RXTIE_MASK == netcSIsBase[CtrlIndex]->BDR_NUM[0u].RBIER)
242 {
243 /* Clear RX interrupt flag for all SIs.*/
244 netcSIsBase[CtrlIndex]->SIRXIDR0 = interruptStatus;
245
246 /* Check is current controller was intialized. Req CPR_RTD_00011 is fulfilled.*/
247 if (NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex])
248 {
249 /* Check all rings of the current controller. */
250 for(RingIndex = 0; RingIndex < Netc_Eth_Ip_apxState[CtrlIndex]->NumberOfRxBDR; RingIndex++)
251 {
252 if ((1U == (interruptStatus >> RingIndex)) && (NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]->RxCallback[RingIndex]))
253 {
254 Netc_Eth_Ip_apxState[CtrlIndex]->RxCallback[RingIndex](Netc_Eth_Ip_apxState[CtrlIndex]->CtrlLogicalIndex, RingIndex);
255 }
256 }
257 }
258 }
259 }
260
261
Netc_Eth_Ip_MSIX_Tx_CheckAllRings(const uint32 TxRingIntStatus,const uint8 CtrlIndex)262 static inline void Netc_Eth_Ip_MSIX_Tx_CheckAllRings(const uint32 TxRingIntStatus, const uint8 CtrlIndex)
263 {
264 uint8 RingIndex;
265 if (NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex])
266 {
267 for(RingIndex = 0U; RingIndex < Netc_Eth_Ip_apxState[CtrlIndex]->NumberOfTxBDR; RingIndex++)
268 {
269 /* In non autosar the user needs to define his own callback */
270 if ((1U == (TxRingIntStatus >> RingIndex)) && (NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]->TxCallback[RingIndex]))
271 {
272 Netc_Eth_Ip_apxState[CtrlIndex]->TxCallback[RingIndex](Netc_Eth_Ip_apxState[CtrlIndex]->CtrlLogicalIndex, RingIndex);
273 }
274 }
275 }
276 }
277
Netc_Eth_Ip_VsiToPsi_Mac_Addr_Set(const Netc_Eth_Ip_VsiToPsiMsgType * const CmdMacReceivedAddr,uint8 VSIIndex)278 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsi_Mac_Addr_Set(const Netc_Eth_Ip_VsiToPsiMsgType* const CmdMacReceivedAddr, uint8 VSIIndex)
279 {
280 const Netc_Eth_Ip_GeneralSIConfigType* SIConfig;
281 Netc_Eth_Ip_StatusType PSIResponseStatus;
282
283 /*Get the SI general configuration */
284 SIConfig = &(*Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->SIGeneralConfig)[VSIIndex];
285 if (SIConfig->changeMACAllowed == TRUE)
286 {
287 /* For the VSIs write the MAC address in the PSIaMAR0 and PSIaMAR1 registers. */
288 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIPMAR0 = (uint32)(CmdMacReceivedAddr->Data[2U]) | \
289 ((uint32)(CmdMacReceivedAddr->Data[3U]) << 8U ) | \
290 ((uint32)(CmdMacReceivedAddr->Data[4U]) << 16U) | \
291 ((uint32)(CmdMacReceivedAddr->Data[5U]) << 24U);
292 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIPMAR1 = (uint32)(CmdMacReceivedAddr->Data[6U]) | \
293 ((uint32)(CmdMacReceivedAddr->Data[7U]) << 8U);
294 PSIResponseStatus = NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL;
295 }
296 else
297 {
298 PSIResponseStatus = NETC_ETH_IP_PSITOVSI_PERMISSION_DENIED;
299 }
300 return PSIResponseStatus;
301 }
302
303
Netc_Eth_Ip_VsiToPsi_Add_Rx_Mac_Addr_Filter(const Netc_Eth_Ip_VsiToPsiMsgType * const CmdMacReceivedAddr,uint8 VSIIndex)304 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsi_Add_Rx_Mac_Addr_Filter(const Netc_Eth_Ip_VsiToPsiMsgType* const CmdMacReceivedAddr, uint8 VSIIndex)
305 {
306 const Netc_Eth_Ip_GeneralSIConfigType* SIConfig;
307 Netc_Eth_Ip_StatusType PSIResponseStatus;
308 uint8 HashValue;
309
310 /*Get the SI general configuration */
311 SIConfig = &(*Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->SIGeneralConfig)[VSIIndex];
312 if (SIConfig->hashFilterUpdateAllowed == TRUE)
313 {
314 HashValue = CmdMacReceivedAddr->Data[0U];
315 if ((HashValue & NETC_ETH_IP_SELECT_HASH_REGISTER) != (uint8)0U)
316 {
317 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIMMHFR1 |= (uint32)((uint32)1U << (HashValue & NETC_ETH_IP_HASH_VALUE));
318 }
319 else
320 {
321 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIMMHFR0 |= (uint32)((uint32)1U << (HashValue & NETC_ETH_IP_HASH_VALUE));
322 }
323
324 PSIResponseStatus = NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL;
325 }
326 else
327 {
328 PSIResponseStatus = NETC_ETH_IP_PSITOVSI_PERMISSION_DENIED;
329 }
330 return PSIResponseStatus;
331 }
332
Netc_Eth_Ip_VsiToPsi_Delete_Rx_Mac_Addr_Filter(const Netc_Eth_Ip_VsiToPsiMsgType * const CmdMacReceivedAddr,uint8 VSIIndex)333 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsi_Delete_Rx_Mac_Addr_Filter(const Netc_Eth_Ip_VsiToPsiMsgType* const CmdMacReceivedAddr, uint8 VSIIndex)
334 {
335 const Netc_Eth_Ip_GeneralSIConfigType* SIConfig;
336 Netc_Eth_Ip_StatusType PSIResponseStatus;
337 uint8 HashValue;
338
339 /*Get the SI general configuration */
340 SIConfig = &(*Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->SIGeneralConfig)[VSIIndex];
341 if (SIConfig->hashFilterUpdateAllowed == TRUE)
342 {
343 HashValue = CmdMacReceivedAddr->Data[0U];
344 if ((HashValue & NETC_ETH_IP_SELECT_HASH_REGISTER) != (uint8)0U)
345 {
346 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIMMHFR1 &= ~(uint32)((uint32)1U << (HashValue & NETC_ETH_IP_HASH_VALUE));
347 }
348 else
349 {
350 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIMMHFR0 &= ~(uint32)((uint32)1U << (HashValue & NETC_ETH_IP_HASH_VALUE));
351 }
352
353 PSIResponseStatus = NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL;
354 }
355 else
356 {
357 PSIResponseStatus = NETC_ETH_IP_PSITOVSI_PERMISSION_DENIED;
358 }
359 return PSIResponseStatus;
360 }
361
Netc_Eth_Ip_VsiToPsi_Enable_Multicast(uint8 VSIIndex)362 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsi_Enable_Multicast(uint8 VSIIndex)
363 {
364 const Netc_Eth_Ip_GeneralSIConfigType* SIConfig;
365 Netc_Eth_Ip_StatusType PSIResponseStatus;
366
367 /*Get the SI general configuration */
368 SIConfig = &(*Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->SIGeneralConfig)[VSIIndex];
369 if (SIConfig->multicastPromiscuousChangeAllowed == TRUE)
370 {
371 /* Enable MAC multicast promiscuous mode. */
372 IP_NETC__ENETC0_BASE->PSIPMMR |= ((uint32)((uint32)1U << ((uint8)VSIIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT)));
373
374 PSIResponseStatus = NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL;
375 }
376 else
377 {
378 PSIResponseStatus = NETC_ETH_IP_PSITOVSI_PERMISSION_DENIED;
379 }
380 return PSIResponseStatus;
381 }
382
383
Netc_Eth_Ip_VsiToPsi_Disable_Multicast(uint8 VSIIndex)384 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_VsiToPsi_Disable_Multicast(uint8 VSIIndex)
385 {
386 const Netc_Eth_Ip_GeneralSIConfigType* SIConfig;
387 Netc_Eth_Ip_StatusType PSIResponseStatus;
388
389 /*Get the SI general configuration */
390 SIConfig = &(*Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->SIGeneralConfig)[VSIIndex];
391 if (SIConfig->multicastPromiscuousChangeAllowed == TRUE)
392 {
393 /* Disable MAC multicast promiscuous mode. */
394 IP_NETC__ENETC0_BASE->PSIPMMR &= ~((uint32) ((uint32)1U << ((uint8)VSIIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT)));
395
396 PSIResponseStatus = NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL;
397 }
398 else
399 {
400 PSIResponseStatus = NETC_ETH_IP_PSITOVSI_PERMISSION_DENIED;
401 }
402 return PSIResponseStatus;
403 }
404
Netc_Eth_Ip_VsiToPsi_Close_Filter(uint8 VSIIndex)405 static inline void Netc_Eth_Ip_VsiToPsi_Close_Filter(uint8 VSIIndex)
406 {
407 const Netc_Eth_Ip_GeneralSIConfigType* SIConfig;
408 /*Get the SI general configuration */
409 SIConfig = &(*Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->SIGeneralConfig)[VSIIndex];
410 if (SIConfig->multicastPromiscuousChangeAllowed == TRUE)
411 {
412 /* Disable MAC multicast promiscuous mode. */
413 IP_NETC__ENETC0_BASE->PSIPMMR &= ~((uint32)((uint32)1U << ((uint8)VSIIndex + NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT)));
414 }
415
416 if (SIConfig->hashFilterUpdateAllowed == TRUE)
417 {
418 /* Clear all entries in filter. */
419 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIMMHFR1 = (uint32)0x0U;
420 IP_NETC__ENETC0_BASE->NUM_SI[VSIIndex].PSIMMHFR0 = (uint32)0x0U;
421 }
422 }
423
Netc_Eth_Ip_Get_Sync_State(void)424 static inline Netc_Eth_Ip_StatusType Netc_Eth_Ip_Get_Sync_State(void)
425 {
426 Netc_Eth_Ip_StatusType PSIResponseStatus;
427
428 if ((IP_NETC__ENETC0_SI0->SITSR & NETC_F3_SI0_SITSR_SYNC_MASK) != 0U)
429 {
430 PSIResponseStatus = NETC_ETH_IP_PSITOVSI_SYNC_STATUS_TRUE;
431 }
432 else
433 {
434 PSIResponseStatus = NETC_ETH_IP_PSITOVSI_SYNC_STATUS_FALSE;
435 }
436 return PSIResponseStatus;
437 }
438
Netc_Eth_Ip_ProcessMsgRcv(uint8 VSIIndex)439 static inline void Netc_Eth_Ip_ProcessMsgRcv(uint8 VSIIndex)
440 {
441 const Netc_Eth_Ip_VsiToPsiMsgType *CmdMacReceivedAddr;
442 Netc_Eth_Ip_VsiToPsiMsgActionType CommandType;
443 Netc_Eth_Ip_StatusType PSIResponse = NETC_ETH_IP_STATUS_NOT_REAL_ERROR;
444
445 CmdMacReceivedAddr =(const Netc_Eth_Ip_VsiToPsiMsgType *)(netcSIsBase[NETC_ETH_IP_PSI_INDEX]->MSGSR.PSI_A.VSI_NUM[VSIIndex].PSIVMSGRCVAR0 & \
446 NETC_F3_SI0_PSIVMSGRCVAR0_ADDRL_MASK);
447
448 #if defined(ERR_IPV_NETC_051247)
449 #if (STD_ON == ERR_IPV_NETC_051247)
450 /* Verify data integrity for the received msg. Number of VSI written bytes is unknown here, the CRC must be calculated on the whole msg buffer, minus the transmitted CRC byte*/
451 if(Netc_Eth_Ip_VsiMsgCalculateCRC8( CmdMacReceivedAddr, (((uint8)sizeof(Netc_Eth_Ip_VsiToPsiMsgType) * (uint8)NETC_ETH_IP_VSITOPSI_MSG_SIZE) - (uint8)1U)) ==
452 CmdMacReceivedAddr->Data[NETC_ETH_IP_VSI_MSG_CRC_POS] )
453 {
454 #endif
455 #endif
456 CommandType = (Netc_Eth_Ip_VsiToPsiMsgActionType)((uint16)((uint32)CmdMacReceivedAddr->Class << 8U) + ((uint32)CmdMacReceivedAddr->Command));
457
458 /* Check if the driver was intialized. Req CPR_RTD_00011 is fulfilled.*/
459 if (NULL_PTR != Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX])
460 {
461 /*Get the SI general configuration */
462
463 switch(CommandType)
464 {
465 case NETC_ETH_IP_VSITOPSI_MAC_ADDR_SET:
466 {
467 PSIResponse = Netc_Eth_Ip_VsiToPsi_Mac_Addr_Set(CmdMacReceivedAddr, (VSIIndex + 1U));
468 break;
469 }
470 case NETC_ETH_IP_VSITOPSI_ADD_RX_MAC_ADDR_FILTER:
471 {
472 PSIResponse = Netc_Eth_Ip_VsiToPsi_Add_Rx_Mac_Addr_Filter(CmdMacReceivedAddr, (VSIIndex + 1U));
473 break;
474 }
475 case NETC_ETH_IP_VSITOPSI_DELETE_RX_MAC_ADDR_FILTER:
476 {
477 PSIResponse = Netc_Eth_Ip_VsiToPsi_Delete_Rx_Mac_Addr_Filter(CmdMacReceivedAddr, (VSIIndex + 1U));
478 break;
479 }
480 case NETC_ETH_IP_VSITOPSI_ENABLE_MULTICAST:
481 {
482 PSIResponse = Netc_Eth_Ip_VsiToPsi_Enable_Multicast(VSIIndex + 1U);
483 break;
484 }
485 case NETC_ETH_IP_VSITOPSI_DISABLE_MULTICAST:
486 {
487 PSIResponse = Netc_Eth_Ip_VsiToPsi_Disable_Multicast(VSIIndex + 1U);
488 break;
489 }
490 case NETC_ETH_IP_VSITOPSI_CLOSE_FILTER:
491 {
492 Netc_Eth_Ip_VsiToPsi_Close_Filter(VSIIndex + 1U);
493 /* A positive response is expected by current IPW implementation*/
494 PSIResponse = NETC_ETH_IP_PSITOVSI_CMD_SUCCESFUL;
495 break;
496 }
497 case NETC_ETH_IP_VSITOPSI_GET_SYNC_STATE:
498 {
499 PSIResponse = Netc_Eth_Ip_Get_Sync_State();
500 break;
501 }
502 default:
503 {
504 /* Do nothing. */
505 break;
506 }
507 }
508 } /* end of driver intialization check */
509
510 #if defined(ERR_IPV_NETC_051247)
511 #if (STD_ON == ERR_IPV_NETC_051247)
512 } /* data integrity check passed */
513 else
514 {
515 PSIResponse = NETC_ETH_IP_PSITOVSI_MSG_INTEGRITY_ERROR;
516 }/* data integrity check failed */
517 #endif
518 #endif
519
520 /* Write the PSI response to MC (Message Code) field and Set the MSn (Message Sent) bit to the corresponding VSI */
521 IP_NETC__ENETC0_SI0->MSGSR.PSI_A.PSIMSGSR = ((uint32)PSIResponse << NETC_ETH_IP_PSI_MSG_POS) | (NETC_ETH_IP_VSI_ENABLE << (VSIIndex + 1U));
522
523 /* Mark the processing as complete by clearing the MR bit from PSIMSGRR. */
524 IP_NETC__ENETC0_SI0->MSGSR.PSI_A.PSIMSGRR = (uint32)((uint32)NETC_ETH_IP_MSG_RCV_COMPLETE << (VSIIndex + 1U));
525 }
526
527
Netc_Eth_Ip_InitVSIAfterFlr(uint8 VSIIndex)528 static inline void Netc_Eth_Ip_InitVSIAfterFlr(uint8 VSIIndex)
529 {
530 const Netc_Eth_Ip_GeneralSIConfigType * SIConfig;
531 uint8 siHwId;
532
533 /* Check if the driver was intialized. Req CPR_RTD_00011 is fulfilled.*/
534 if (NULL_PTR != Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX])
535 {
536 /*Get the SI general configuration */
537 SIConfig = &(*Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->SIGeneralConfig)[VSIIndex];
538
539 /* Identify the VSI in the list of SIs to configure */
540 siHwId = SIConfig->siId;
541
542 /* Enable/disable MAC multicast/unicast promiscuous mode. */
543 IP_NETC__ENETC0_BASE->PSIPMMR = ((uint32)(Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->generalConfig->maskMACPromiscuousMulticastEnable) << NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT) | \
544 (uint32)(Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->generalConfig->maskMACPromiscuousUnicastEnable);
545
546 if (TRUE == SIConfig->enableSi)
547 {
548 /** Assure that SI is not enabled. */
549 netcSIsBase[siHwId]->SIMR &= ~(NETC_F3_SI0_SIMR_EN_MASK);
550
551 /* Master enable for a station interface.*/
552 IP_NETC__ENETC0_BASE->PMR = IP_NETC__ENETC0_BASE->PMR | (NETC_F3_PMR_SI0EN_MASK << siHwId);
553
554 /* For the VSIs write the MAC address in the PSIaMAR0 and PSIaMAR1 registers */
555 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIPMAR0 = ((uint32)SIConfig->primaryMACAddress[0U]) | \
556 (((uint32)SIConfig->primaryMACAddress[1U]) << 8U) | \
557 (((uint32)SIConfig->primaryMACAddress[2U]) << 16U) | \
558 (((uint32)SIConfig->primaryMACAddress[3U]) << 24U);
559
560 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIPMAR1 = ((uint32)SIConfig->primaryMACAddress[4U]) | \
561 (((uint32)SIConfig->primaryMACAddress[5U]) << 8U);
562
563 /* Configure where the PSI receives the message for enabled VSIs. */
564 /* if(NULL_PTR != config->generalConfig->RxVsiMsgCmdToPsi[siHwId - 1U])
565 {
566 IP_NETC__ENETC0_SI0->MSGSR.PSI_A.VSI_NUM[siHwId - 1U].PSIVMSGRCVAR0 = (uint32)config->generalConfig->RxVsiMsgCmdToPsi[siHwId - 1U] | \
567 NETC_ETH_IP_VSITOPSI_MSG_SIZE;
568 }
569 */
570
571 /* Number of entries in a MSI table for the current SI. */
572 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR2 = NETC_ETH_IP_NUM_OF_ENTRIES_MSITABLE;
573
574 /* Configure the number or TX and RX BD Rings for each SI */
575 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 &= ~(NETC_F3_PSICFGR0_NUM_TX_BDR_MASK | NETC_F3_PSICFGR0_NUM_RX_BDR_MASK);
576
577 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_NUM_TX_BDR(SIConfig->NumberOfTxBDR) | \
578 NETC_F3_PSICFGR0_NUM_RX_BDR(SIConfig->NumberOfRxBDR);
579
580 /* Configure the bandwidth weight for the current SI */
581 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_SIBW(SIConfig->SIBandwidthWeight);
582
583 #if (STD_ON == NETC_ETH_IP_VLAN_SUPPORT)
584 if (TRUE == SIConfig->EnableSIVlan)
585 {
586 /* Enable VLAN and select tag protocol, priority code point, drop eligible indicator and VLAN identifier */
587 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIVLANR = NETC_F3_PSIVLANR_TPID(SIConfig->SiVLANConfig.ProtocolIdentifier) |
588 NETC_F3_PSIVLANR_PCP(SIConfig->SiVLANConfig.PriorityCodePoint) |
589 NETC_F3_PSIVLANR_VID(SIConfig->SiVLANConfig.VlanIdentifier) |
590 NETC_F3_PSIVLANR_E(1U) | NETC_F3_PSIVLANR_DEI((uint8)SIConfig->SiVLANConfig.DropIndicator);
591 }
592 else
593 {
594 /* Disable VLAN and select tag protocol */
595 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSIVLANR &= ~NETC_F3_PSIVLANR_E(1U);
596 }
597 IP_NETC__ENETC0_BASE->PSIPVMR =(uint32)(Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->generalConfig->maskMACVLANPromiscuousEnable)|
598 (Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX]->generalConfig->maskVLANAllowUntaggedEnable) ;
599
600 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 &= ~(NETC_F3_PSICFGR0_SIVC_MASK | NETC_F3_PSICFGR0_SIVIE_MASK | NETC_F3_PSICFGR0_VTE_MASK);
601 /* Insert VLAN Ethertype and enable insertion of the SI-based VLAN into frames sent by this SI. This config apply for generic */
602 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_SIVC(SIConfig->SIVlanControl) |
603 NETC_F3_PSICFGR0_SIVIE((uint8)SIConfig->EnableSoftwareVlanInsert) |
604 NETC_F3_PSICFGR0_VTE((SIConfig->EnableVLANTagExtract) ? 1U : 0U); ;
605 #endif
606
607 IP_NETC__ENETC0_BASE->NUM_SI[siHwId].PSICFGR0 |= NETC_F3_PSICFGR0_ASE((SIConfig->enableAntiSpoofing) ? 1U : 0U);
608
609 /* Enable bus for virtual function. */
610 netcVFBase[VSIIndex]->PCI_CFH_CMD |= NETC_VF1_PCI_HDR_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN(1U);
611
612 }
613 }
614
615 }
616
617
618 /*==================================================================================================
619 * GLOBAL FUNCTIONS
620 ==================================================================================================*/
621 /***************************************************************************
622 * implements Netc_Eth_Ip_MSIX_SIMsgEvent_Activity
623 ***************************************************************************/
Netc_Eth_Ip_MSIX_SIMsgEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)624 void Netc_Eth_Ip_MSIX_SIMsgEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
625 {
626 uint8 CounterRxMsgFromVsi;
627 uint8 RxMsgFromVsiMask;
628 uint32 FlrMask;
629
630 /*Check if the Interrupt for PSI is enabled*/
631 if ((netcSIsBase[NETC_ETH_IP_PSI_INDEX]->INTERRUPT.PSI.PSIIER & NETC_ETH_IP_PSIIER_MASK) != (uint32)0U)
632 {
633 /* Status of received messages. */
634 RxMsgFromVsiMask = (uint8)(netcSIsBase[NETC_ETH_IP_PSI_INDEX]->INTERRUPT.PSI.PSIIDR & NETC_ETH_IP_PSI_MR_EV_MASK);
635
636 /* Function Level Reset Mask. */
637 FlrMask = (uint32)(netcSIsBase[NETC_ETH_IP_PSI_INDEX]->INTERRUPT.PSI.PSIIDR & NETC_ETH_IP_FLR_EV_MASK);
638
639 /* Clear status for messages that will be addressed and for the SI that will be reset at function level. */
640 netcSIsBase[NETC_ETH_IP_PSI_INDEX]->INTERRUPT.PSI.PSIIDR = (uint32)RxMsgFromVsiMask | (uint32)FlrMask;
641 /*Check if driver is initialized on the current controller */
642 if (NULL_PTR != Netc_Eth_Ip_apxState[NETC_ETH_IP_PSI_INDEX])
643 {
644 for(CounterRxMsgFromVsi = 0U; CounterRxMsgFromVsi < FEATURE_NETC_ETH_NUM_OF_VIRTUAL_CTRLS; CounterRxMsgFromVsi++)
645 {
646 if((((uint32)1U << (CounterRxMsgFromVsi + 1U)) & (uint32)RxMsgFromVsiMask) != (uint32)0U)
647 {
648 Netc_Eth_Ip_ProcessMsgRcv(CounterRxMsgFromVsi);
649 }
650
651 if((((uint32)1U << NETC_ETH_IP_PSI_IDR_FLR(CounterRxMsgFromVsi + 1U)) & (uint32)FlrMask) != (uint32)0U)
652 {
653 Netc_Eth_Ip_InitVSIAfterFlr(CounterRxMsgFromVsi + 1U);
654 }
655 }
656 }
657 }
658
659 (void)RxChannelId;
660 (void)RxBuffer;
661 (void)BufferSize;
662 }
663
Netc_Eth_Ip_0_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)664 void Netc_Eth_Ip_0_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
665 {
666 Netc_Eth_Ip_MSIX_Tx(0U);
667 (void)RxChannelId;
668 (void)RxBuffer;
669 (void)BufferSize;
670 }
671
Netc_Eth_Ip_1_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)672 void Netc_Eth_Ip_1_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
673 {
674 Netc_Eth_Ip_MSIX_Tx(1U);
675 (void)RxChannelId;
676 (void)RxBuffer;
677 (void)BufferSize;
678 }
679
Netc_Eth_Ip_2_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)680 void Netc_Eth_Ip_2_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
681 {
682 Netc_Eth_Ip_MSIX_Tx(2U);
683 (void)RxChannelId;
684 (void)RxBuffer;
685 (void)BufferSize;
686 }
687
Netc_Eth_Ip_3_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)688 void Netc_Eth_Ip_3_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
689 {
690 Netc_Eth_Ip_MSIX_Tx(3U);
691 (void)RxChannelId;
692 (void)RxBuffer;
693 (void)BufferSize;
694 }
695
Netc_Eth_Ip_4_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)696 void Netc_Eth_Ip_4_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
697 {
698 Netc_Eth_Ip_MSIX_Tx(4U);
699 (void)RxChannelId;
700 (void)RxBuffer;
701 (void)BufferSize;
702 }
703
Netc_Eth_Ip_5_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)704 void Netc_Eth_Ip_5_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
705 {
706 Netc_Eth_Ip_MSIX_Tx(5U);
707 (void)RxChannelId;
708 (void)RxBuffer;
709 (void)BufferSize;
710 }
711
Netc_Eth_Ip_6_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)712 void Netc_Eth_Ip_6_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
713 {
714 Netc_Eth_Ip_MSIX_Tx(6U);
715 (void)RxChannelId;
716 (void)RxBuffer;
717 (void)BufferSize;
718 }
719
Netc_Eth_Ip_7_MSIX_TxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)720 void Netc_Eth_Ip_7_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
721 {
722 Netc_Eth_Ip_MSIX_Tx(7U);
723 (void)RxChannelId;
724 (void)RxBuffer;
725 (void)BufferSize;
726 }
727
728
Netc_Eth_Ip_0_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)729 void Netc_Eth_Ip_0_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
730 {
731 Netc_Eth_Ip_MSIX_Rx(0U);
732 (void)RxChannelId;
733 (void)RxBuffer;
734 (void)BufferSize;
735 }
736
Netc_Eth_Ip_1_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)737 void Netc_Eth_Ip_1_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
738 {
739 Netc_Eth_Ip_MSIX_Rx(1U);
740 (void)RxChannelId;
741 (void)RxBuffer;
742 (void)BufferSize;
743 }
744
Netc_Eth_Ip_2_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)745 void Netc_Eth_Ip_2_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
746 {
747 Netc_Eth_Ip_MSIX_Rx(2U);
748 (void)RxChannelId;
749 (void)RxBuffer;
750 (void)BufferSize;
751 }
752
Netc_Eth_Ip_3_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)753 void Netc_Eth_Ip_3_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
754 {
755 Netc_Eth_Ip_MSIX_Rx(3U);
756 (void)RxChannelId;
757 (void)RxBuffer;
758 (void)BufferSize;
759 }
760
Netc_Eth_Ip_4_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)761 void Netc_Eth_Ip_4_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
762 {
763 Netc_Eth_Ip_MSIX_Rx(4U);
764 (void)RxChannelId;
765 (void)RxBuffer;
766 (void)BufferSize;
767 }
768
Netc_Eth_Ip_5_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)769 void Netc_Eth_Ip_5_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
770 {
771 Netc_Eth_Ip_MSIX_Rx(5U);
772 (void)RxChannelId;
773 (void)RxBuffer;
774 (void)BufferSize;
775 }
776
Netc_Eth_Ip_6_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)777 void Netc_Eth_Ip_6_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
778 {
779 Netc_Eth_Ip_MSIX_Rx(6U);
780 (void)RxChannelId;
781 (void)RxBuffer;
782 (void)BufferSize;
783 }
784
Netc_Eth_Ip_7_MSIX_RxEvent(uint8 RxChannelId,const uint32 * RxBuffer,uint8 BufferSize)785 void Netc_Eth_Ip_7_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize)
786 {
787 Netc_Eth_Ip_MSIX_Rx(7U);
788 (void)RxChannelId;
789 (void)RxBuffer;
790 (void)BufferSize;
791 }
792
ISR(Netc_Eth_Ip_ErrorReporting)793 ISR(Netc_Eth_Ip_ErrorReporting)
794 {
795 Netc_Eth_Ip_PCIe_AER_Handler(0u);
796 }
797
798 #ifdef __cplusplus
799 }
800 #endif
801
802 /** @} */
803
