1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32U5xx_HAL_CORTEX_H 22 #define __STM32U5xx_HAL_CORTEX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32u5xx_hal_def.h" 30 31 /** @addtogroup STM32U5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @defgroup CORTEX CORTEX 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 41 * @{ 42 */ 43 44 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 45 * @{ 46 */ 47 typedef struct 48 { 49 uint8_t Enable; /*!< Specifies the status of the region. 50 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 51 uint8_t Number; /*!< Specifies the index of the region to protect. 52 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 53 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 54 uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ 55 uint8_t AttributesIndex; /*!< Specifies the memory attributes index. 56 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 57 uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter 58 can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 59 uint8_t DisableExec; /*!< Specifies the instruction access status. 60 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 61 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 62 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 63 } MPU_Region_InitTypeDef; 64 /** 65 * @} 66 */ 67 68 /** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes 69 * Initialization Structure Definition 70 * @{ 71 */ 72 typedef struct 73 { 74 uint8_t Number; /*!< Specifies the number of the memory attributes to configure. 75 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 76 77 uint8_t Attributes; /*!< Specifies the memory attributes value. Attributes This parameter 78 can be a combination of @ref CORTEX_MPU_Attributes */ 79 80 } MPU_Attributes_InitTypeDef; 81 /** 82 * @} 83 */ 84 85 86 /** 87 * @} 88 */ 89 90 /* Exported constants --------------------------------------------------------*/ 91 92 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 93 * @{ 94 */ 95 96 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 97 * @{ 98 */ 99 #define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority, 100 4 bits for subpriority */ 101 #define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority, 102 3 bits for subpriority */ 103 #define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority, 104 2 bits for subpriority */ 105 #define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority, 106 1 bit for subpriority */ 107 #define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority, 108 0 bit for subpriority */ 109 /** 110 * @} 111 */ 112 113 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 114 * @{ 115 */ 116 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x0U /*!< AHB clock divided by 8 selected as SysTick clock source */ 117 #define SYSTICK_CLKSOURCE_LSI 0x1U /*!< LSI clock selected as SysTick clock source */ 118 #define SYSTICK_CLKSOURCE_LSE 0x2U /*!< LSE clock selected as SysTick clock source */ 119 #define SYSTICK_CLKSOURCE_HCLK 0x4U /*!< AHB clock selected as SysTick clock source */ 120 /** 121 * @} 122 */ 123 124 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 125 * @{ 126 */ 127 #define MPU_HFNMI_PRIVDEF_NONE 0U 128 #define MPU_HARDFAULT_NMI 2U 129 #define MPU_PRIVILEGED_DEFAULT 4U 130 #define MPU_HFNMI_PRIVDEF 6U 131 /** 132 * @} 133 */ 134 135 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 136 * @{ 137 */ 138 #define MPU_REGION_ENABLE 1U 139 #define MPU_REGION_DISABLE 0U 140 /** 141 * @} 142 */ 143 144 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 145 * @{ 146 */ 147 #define MPU_INSTRUCTION_ACCESS_ENABLE 0U 148 #define MPU_INSTRUCTION_ACCESS_DISABLE 1U 149 /** 150 * @} 151 */ 152 153 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 154 * @{ 155 */ 156 #define MPU_ACCESS_NOT_SHAREABLE 0U 157 #define MPU_ACCESS_OUTER_SHAREABLE 1U 158 #define MPU_ACCESS_INNER_SHAREABLE 3U 159 /** 160 * @} 161 */ 162 163 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 164 * @{ 165 */ 166 #define MPU_REGION_PRIV_RW 0U 167 #define MPU_REGION_ALL_RW 1U 168 #define MPU_REGION_PRIV_RO 2U 169 #define MPU_REGION_ALL_RO 3U 170 /** 171 * @} 172 */ 173 174 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 175 * @{ 176 */ 177 #define MPU_REGION_NUMBER0 0U 178 #define MPU_REGION_NUMBER1 1U 179 #define MPU_REGION_NUMBER2 2U 180 #define MPU_REGION_NUMBER3 3U 181 #define MPU_REGION_NUMBER4 4U 182 #define MPU_REGION_NUMBER5 5U 183 #define MPU_REGION_NUMBER6 6U 184 #define MPU_REGION_NUMBER7 7U 185 /** 186 * @} 187 */ 188 189 /** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number 190 * @{ 191 */ 192 #define MPU_ATTRIBUTES_NUMBER0 0U 193 #define MPU_ATTRIBUTES_NUMBER1 1U 194 #define MPU_ATTRIBUTES_NUMBER2 2U 195 #define MPU_ATTRIBUTES_NUMBER3 3U 196 #define MPU_ATTRIBUTES_NUMBER4 4U 197 #define MPU_ATTRIBUTES_NUMBER5 5U 198 #define MPU_ATTRIBUTES_NUMBER6 6U 199 #define MPU_ATTRIBUTES_NUMBER7 7U 200 /** 201 * @} 202 */ 203 204 /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes 205 * @{ 206 */ 207 #define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ 208 #define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ 209 #define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ 210 #define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ 211 212 #define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ 213 #define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ 214 #define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ 215 216 #define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ 217 #define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ 218 219 #define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ 220 #define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ 221 #define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ 222 #define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ 223 224 /** 225 * @} 226 */ 227 228 /** 229 * @} 230 */ 231 232 /* Exported macros -----------------------------------------------------------*/ 233 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 234 * @{ 235 */ 236 #define OUTER(__ATTR__) ((__ATTR__) << 4U) 237 #define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) 238 239 /** 240 * @} 241 */ 242 243 /* Exported functions --------------------------------------------------------*/ 244 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 245 * @{ 246 */ 247 248 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 249 * @brief Initialization and Configuration functions 250 * @{ 251 */ 252 /* Initialization and Configuration functions *****************************/ 253 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 254 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 255 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 256 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 257 void HAL_NVIC_SystemReset(void); 258 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 259 /** 260 * @} 261 */ 262 263 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 264 * @brief Cortex control functions 265 * @{ 266 */ 267 /* Peripheral Control functions ***********************************************/ 268 uint32_t HAL_NVIC_GetPriorityGrouping(void); 269 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 270 uint32_t *const pSubPriority); 271 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 272 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 273 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 274 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 275 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 276 void HAL_SYSTICK_IRQHandler(void); 277 void HAL_SYSTICK_Callback(void); 278 279 void HAL_MPU_Enable(uint32_t MPU_Control); 280 void HAL_MPU_Disable(void); 281 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit); 282 void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); 283 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 284 /* MPU_NS Control functions ***********************************************/ 285 void HAL_MPU_Enable_NS(uint32_t MPU_Control); 286 void HAL_MPU_Disable_NS(void); 287 void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit); 288 void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); 289 #endif /* __ARM_FEATURE_CMSE */ 290 /** 291 * @} 292 */ 293 294 /** 295 * @} 296 */ 297 298 /* Private types -------------------------------------------------------------*/ 299 /* Private variables ---------------------------------------------------------*/ 300 /* Private constants ---------------------------------------------------------*/ 301 /* Private macros ------------------------------------------------------------*/ 302 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 303 * @{ 304 */ 305 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 306 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 307 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 308 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 309 ((GROUP) == NVIC_PRIORITYGROUP_4)) 310 311 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 312 313 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 314 315 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 316 317 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ 318 ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ 319 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ 320 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 321 322 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 323 #define IS_MPU_INSTANCE(INSTANCE) (((INSTANCE) == MPU) || ((INSTANCE) == MPU_NS)) 324 #endif /* __ARM_FEATURE_CMSE */ 325 326 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 327 ((STATE) == MPU_REGION_DISABLE)) 328 329 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 330 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 331 332 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ 333 ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ 334 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 335 336 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ 337 ((TYPE) == MPU_REGION_ALL_RW) || \ 338 ((TYPE) == MPU_REGION_PRIV_RO) || \ 339 ((TYPE) == MPU_REGION_ALL_RO)) 340 341 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 342 ((NUMBER) == MPU_REGION_NUMBER1) || \ 343 ((NUMBER) == MPU_REGION_NUMBER2) || \ 344 ((NUMBER) == MPU_REGION_NUMBER3) || \ 345 ((NUMBER) == MPU_REGION_NUMBER4) || \ 346 ((NUMBER) == MPU_REGION_NUMBER5) || \ 347 ((NUMBER) == MPU_REGION_NUMBER6) || \ 348 ((NUMBER) == MPU_REGION_NUMBER7)) 349 350 #define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ 351 ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ 352 ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ 353 ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ 354 ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ 355 ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ 356 ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ 357 ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) 358 359 /** 360 * @} 361 */ 362 363 /* Private functions ---------------------------------------------------------*/ 364 365 /** 366 * @} 367 */ 368 369 /** 370 * @} 371 */ 372 373 #ifdef __cplusplus 374 } 375 #endif 376 377 #endif /* __STM32U5xx_HAL_CORTEX_H */ 378 379 380
