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32 #ifndef __INTERRUPT_H__
33 #define __INTERRUPT_H__
34 
35 //*****************************************************************************
36 //
37 //! \addtogroup interrupt_api
38 //! @{
39 //
40 //*****************************************************************************
41 
42 
43 //*****************************************************************************
44 //
45 // If building with a C++ compiler, make all of the definitions in this header
46 // have a C binding.
47 //
48 //*****************************************************************************
49 #ifdef __cplusplus
50 extern "C"
51 {
52 #endif
53 
54 #include <stdint.h>
55 #include <stdbool.h>
56 #include <ti/devices/msp432p4xx/inc/msp.h>
57 
58 /******************************************************************************
59 * NVIC interrupts                                                             *
60 ******************************************************************************/
61 /* System exceptions */
62 #define FAULT_NMI                                       ( 2) /* NMI fault */
63 #define FAULT_HARD                                      ( 3) /* Hard fault */
64 #define FAULT_MPU                                       ( 4) /* MPU fault */
65 #define FAULT_BUS                                       ( 5) /* Bus fault */
66 #define FAULT_USAGE                                     ( 6) /* Usage fault */
67 #define FAULT_SVCALL                                    (11) /* SVCall */
68 #define FAULT_DEBUG                                     (12) /* Debug monitor */
69 #define FAULT_PENDSV                                    (14) /* PendSV */
70 #define FAULT_SYSTICK                                   (15) /* System Tick */
71 
72 /* External interrupts */
73 #define INT_PSS                                         (16) /* PSS IRQ */
74 #define INT_CS                                          (17) /* CS IRQ */
75 #define INT_PCM                                         (18) /* PCM IRQ */
76 #define INT_WDT_A                                       (19) /* WDT_A IRQ */
77 #define INT_FPU                                         (20) /* FPU IRQ */
78 #define INT_FLCTL                                       (21) /* FLCTL IRQ */
79 #define INT_COMP_E0                                     (22) /* COMP_E0 IRQ */
80 #define INT_COMP_E1                                     (23) /* COMP_E1 IRQ */
81 #define INT_TA0_0                                       (24) /* TA0_0 IRQ */
82 #define INT_TA0_N                                       (25) /* TA0_N IRQ */
83 #define INT_TA1_0                                       (26) /* TA1_0 IRQ */
84 #define INT_TA1_N                                       (27) /* TA1_N IRQ */
85 #define INT_TA2_0                                       (28) /* TA2_0 IRQ */
86 #define INT_TA2_N                                       (29) /* TA2_N IRQ */
87 #define INT_TA3_0                                       (30) /* TA3_0 IRQ */
88 #define INT_TA3_N                                       (31) /* TA3_N IRQ */
89 #define INT_EUSCIA0                                     (32) /* EUSCIA0 IRQ */
90 #define INT_EUSCIA1                                     (33) /* EUSCIA1 IRQ */
91 #define INT_EUSCIA2                                     (34) /* EUSCIA2 IRQ */
92 #define INT_EUSCIA3                                     (35) /* EUSCIA3 IRQ */
93 #define INT_EUSCIB0                                     (36) /* EUSCIB0 IRQ */
94 #define INT_EUSCIB1                                     (37) /* EUSCIB1 IRQ */
95 #define INT_EUSCIB2                                     (38) /* EUSCIB2 IRQ */
96 #define INT_EUSCIB3                                     (39) /* EUSCIB3 IRQ */
97 #define INT_ADC14                                       (40) /* ADC14 IRQ */
98 #define INT_T32_INT1                                    (41) /* T32_INT1 IRQ */
99 #define INT_T32_INT2                                    (42) /* T32_INT2 IRQ */
100 #define INT_T32_INTC                                    (43) /* T32_INTC IRQ */
101 #define INT_AES256                                      (44) /* AES256 IRQ */
102 #define INT_RTC_C                                       (45) /* RTC_C IRQ */
103 #define INT_DMA_ERR                                     (46) /* DMA_ERR IRQ */
104 #define INT_DMA_INT3                                    (47) /* DMA_INT3 IRQ */
105 #define INT_DMA_INT2                                    (48) /* DMA_INT2 IRQ */
106 #define INT_DMA_INT1                                    (49) /* DMA_INT1 IRQ */
107 #define INT_DMA_INT0                                    (50) /* DMA_INT0 IRQ */
108 #define INT_PORT1                                       (51) /* PORT1 IRQ */
109 #define INT_PORT2                                       (52) /* PORT2 IRQ */
110 #define INT_PORT3                                       (53) /* PORT3 IRQ */
111 #define INT_PORT4                                       (54) /* PORT4 IRQ */
112 #define INT_PORT5                                       (55) /* PORT5 IRQ */
113 #define INT_PORT6                                       (56) /* PORT6 IRQ */
114 #define INT_LCD_F                                       (57) /* PORT6 IRQ */
115 
116 #define NUM_INTERRUPTS                                  (57)
117 //*****************************************************************************
118 //
119 // Macro to generate an interrupt priority mask based on the number of bits
120 // of priority supported by the hardware.
121 //
122 //*****************************************************************************
123 #define INT_PRIORITY_MASK       ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
124 #define NUM_PRIORITY            8
125 
126 #define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
127 #define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
128 #define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
129 #define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
130 #define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
131 #define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
132 #define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
133 #define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
134 #define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
135 #define NVIC_SYS_PRI1_R         0xE000ED18  // System Handler Priority 1
136 #define NVIC_SYS_PRI2_R         0xE000ED1C  // System Handler Priority 2
137 #define NVIC_SYS_PRI3_R         0xE000ED20  // System Handler Priority 3
138 #define NVIC_PRI0_R             0xE000E400  // Interrupt 0-3 Priority
139 #define NVIC_PRI1_R             0xE000E404  // Interrupt 4-7 Priority
140 #define NVIC_PRI2_R             0xE000E408  // Interrupt 8-11 Priority
141 #define NVIC_PRI3_R             0xE000E40C  // Interrupt 12-15 Priority
142 #define NVIC_PRI4_R             0xE000E410  // Interrupt 16-19 Priority
143 #define NVIC_PRI5_R             0xE000E414  // Interrupt 20-23 Priority
144 #define NVIC_PRI6_R             0xE000E418  // Interrupt 24-27 Priority
145 #define NVIC_PRI7_R             0xE000E41C  // Interrupt 28-31 Priority
146 #define NVIC_PRI8_R             0xE000E420  // Interrupt 32-35 Priority
147 #define NVIC_PRI9_R             0xE000E424  // Interrupt 36-39 Priority
148 #define NVIC_PRI10_R            0xE000E428  // Interrupt 40-43 Priority
149 #define NVIC_PRI11_R            0xE000E42C  // Interrupt 44-47 Priority
150 #define NVIC_PRI12_R            0xE000E430  // Interrupt 48-51 Priority
151 #define NVIC_PRI13_R            0xE000E434  // Interrupt 52-55 Priority
152 #define NVIC_PRI14_R            0xE000E438  // Interrupt 56-59 Priority
153 #define NVIC_PRI15_R            0xE000E43C  // Interrupt 60-63 Priority
154 #define NVIC_EN0_R              0xE000E100  // Interrupt 0-31 Set Enable
155 #define NVIC_EN1_R              0xE000E104  // Interrupt 32-54 Set Enable
156 #define NVIC_DIS0_R             0xE000E180  // Interrupt 0-31 Clear Enable
157 #define NVIC_DIS1_R             0xE000E184  // Interrupt 32-54 Clear Enable
158 #define NVIC_PEND0_R            0xE000E200  // Interrupt 0-31 Set Pending
159 #define NVIC_PEND1_R            0xE000E204  // Interrupt 32-54 Set Pending
160 #define NVIC_UNPEND0_R          0xE000E280  // Interrupt 0-31 Clear Pending
161 #define NVIC_UNPEND1_R          0xE000E284  // Interrupt 32-54 Clear Pending
162 //*****************************************************************************
163 //
164 // Prototypes for the APIs.
165 //
166 //*****************************************************************************
167 
168 //*****************************************************************************
169 //
170 //! Enables the processor interrupt.
171 //!
172 //! This function allows the processor to respond to interrupts.  This function
173 //! does not affect the set of interrupts enabled in the interrupt controller;
174 //! it just gates the single interrupt from the controller to the processor.
175 //!
176 //! \return Returns \b true if interrupts were disabled when the function was
177 //! called or \b false if they were initially enabled.
178 //
179 //*****************************************************************************
180 extern bool Interrupt_enableMaster(void);
181 
182 //*****************************************************************************
183 //
184 //! Disables the processor interrupt.
185 //!
186 //! This function prevents the processor from receiving interrupts.  This
187 //! function does not affect the set of interrupts enabled in the interrupt
188 //! controller; it just gates the single interrupt from the controller to the
189 //! processor.
190 //!
191 //! \return Returns \b true if interrupts were already disabled when the
192 //! function was called or \b false if they were initially enabled.
193 //
194 //*****************************************************************************
195 extern bool Interrupt_disableMaster(void);
196 
197 //*****************************************************************************
198 //
199 //! Registers a function to be called when an interrupt occurs.
200 //!
201 //! \param interruptNumber specifies the interrupt in question.
202 //! \param intHandler is a pointer to the function to be called.
203 //!
204 //! \note The use of this function (directly or indirectly via a peripheral
205 //! driver interrupt register function) moves the interrupt vector table from
206 //! flash to SRAM.  Therefore, care must be taken when linking the application
207 //! to ensure that the SRAM vector table is located at the beginning of SRAM;
208 //! otherwise the NVIC does not look in the correct portion of memory for the
209 //! vector table (it requires the vector table be on a 1 kB memory alignment).
210 //! Normally, the SRAM vector table is so placed via the use of linker scripts.
211 //! See the discussion of compile-time versus run-time interrupt handler
212 //! registration in the introduction to this chapter.
213 //!
214 //! \note This function is only used if the customer wants to specify the
215 //!  interrupt handler at run time. In most cases, this is done through means
216 //!  of the user setting the ISR function pointer in the startup file. Refer
217 //!  Refer to the Module Operation section for more details.
218 //!
219 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
220 //! parameter
221 //!
222 //! \return None.
223 //
224 //*****************************************************************************
225 extern void Interrupt_registerInterrupt(uint32_t interruptNumber,
226         void (*intHandler)(void));
227 
228 //*****************************************************************************
229 //
230 //! Unregisters the function to be called when an interrupt occurs.
231 //!
232 //! \param interruptNumber specifies the interrupt in question.
233 //!
234 //! This function is used to indicate that no handler should be called when the
235 //! given interrupt is asserted to the processor.  The interrupt source is
236 //! automatically disabled (via Interrupt_disableInterrupt()) if necessary.
237 //!
238 //! \sa Interrupt_registerInterrupt() for important information about
239 //! registering interrupt handlers.
240 //!
241 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
242 //! parameter
243 //!
244 //! \return None.
245 //
246 //*****************************************************************************
247 extern void Interrupt_unregisterInterrupt(uint32_t interruptNumber);
248 
249 //*****************************************************************************
250 //
251 //! Sets the priority grouping of the interrupt controller.
252 //!
253 //! \param bits specifies the number of bits of preemptable priority.
254 //!
255 //! This function specifies the split between preemptable priority levels and
256 //! sub-priority levels in the interrupt priority specification.  The range of
257 //! the grouping values are dependent upon the hardware implementation; on
258 //! the MSP432 family, three bits are available for hardware interrupt
259 //! prioritization and therefore priority grouping values of three through
260 //! seven have the same effect.
261 //!
262 //! \return None.
263 //
264 //*****************************************************************************
265 extern void Interrupt_setPriorityGrouping(uint32_t bits);
266 
267 //*****************************************************************************
268 //
269 //! Gets the priority grouping of the interrupt controller.
270 //!
271 //! This function returns the split between preemptable priority levels and
272 //! sub-priority levels in the interrupt priority specification.
273 //!
274 //! \return The number of bits of preemptable priority.
275 //
276 //*****************************************************************************
277 extern uint32_t Interrupt_getPriorityGrouping(void);
278 
279 //*****************************************************************************
280 //
281 //! Sets the priority of an interrupt.
282 //!
283 //! \param interruptNumber specifies the interrupt in question.
284 //! \param priority specifies the priority of the interrupt.
285 //!
286 //! This function is used to set the priority of an interrupt.  When multiple
287 //! interrupts are asserted simultaneously, the ones with the highest priority
288 //! are processed before the lower priority interrupts.  Smaller numbers
289 //! correspond to higher interrupt priorities; priority 0 is the highest
290 //! interrupt priority.
291 //!
292 //! The hardware priority mechanism only looks at the upper N bits of the
293 //! priority level (where N is 3 for the MSP432 family), so any
294 //! prioritization must be performed in those bits.  The remaining bits can be
295 //! used to sub-prioritize the interrupt sources, and may be used by the
296 //! hardware priority mechanism on a future part.  This arrangement allows
297 //! priorities to migrate to different NVIC implementations without changing
298 //! the gross prioritization of the interrupts.
299 //!
300 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
301 //! parameter
302 //!
303 //! \return None.
304 //
305 //*****************************************************************************
306 extern void Interrupt_setPriority(uint32_t interruptNumber, uint8_t priority);
307 
308 //*****************************************************************************
309 //
310 //! Gets the priority of an interrupt.
311 //!
312 //! \param interruptNumber specifies the interrupt in question.
313 //!
314 //! This function gets the priority of an interrupt.  See
315 //! Interrupt_setPriority() for a definition of the priority value.
316 //!
317 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
318 //! parameter
319 //!
320 //! \return Returns the interrupt priority, or -1 if an invalid interrupt was
321 //! specified.
322 //
323 //*****************************************************************************
324 extern uint8_t Interrupt_getPriority(uint32_t interruptNumber);
325 
326 //*****************************************************************************
327 //
328 //! Enables an interrupt.
329 //!
330 //! \param interruptNumber specifies the interrupt to be enabled.
331 //!
332 //! The specified interrupt is enabled in the interrupt controller.  Other
333 //! enables for the interrupt (such as at the peripheral level) are unaffected
334 //! by this function.
335 //!
336 //! Valid values will vary from part to part, so it is important to check the
337 //! device specific datasheet, however for MSP432 101 the following values can
338 //! be provided:
339 //!     - \b FAULT_NMI
340 //!     - \b FAULT_HARD
341 //!     - \b FAULT_MPU
342 //!     - \b FAULT_BUS
343 //!     - \b FAULT_USAGE
344 //!     - \b FAULT_SVCALL
345 //!     - \b FAULT_DEBUG
346 //!     - \b FAULT_PENDSV
347 //!     - \b FAULT_SYSTICK
348 //!     - \b INT_PSS
349 //!     - \b INT_CS
350 //!     - \b INT_PCM
351 //!     - \b INT_WDT_A
352 //!     - \b INT_FPU
353 //!     - \b INT_FLCTL
354 //!     - \b INT_COMP0
355 //!     - \b INT_COMP1
356 //!     - \b INT_TA0_0
357 //!     - \b INT_TA0_N
358 //!     - \b INT_TA1_0
359 //!     - \b INT_TA1_N
360 //!     - \b INT_TA2_0
361 //!     - \b INT_TA2_N
362 //!     - \b INT_TA3_0
363 //!     - \b INT_TA3_N
364 //!     - \b INT_EUSCIA0
365 //!     - \b INT_EUSCIA1
366 //!     - \b INT_EUSCIA2
367 //!     - \b INT_EUSCIA3
368 //!     - \b INT_EUSCIB0
369 //!     - \b INT_EUSCIB1
370 //!     - \b INT_EUSCIB2
371 //!     - \b INT_EUSCIB3
372 //!     - \b INT_ADC14
373 //!     - \b INT_T32_INT1
374 //!     - \b INT_T32_INT2
375 //!     - \b INT_T32_INTC
376 //!     - \b INT_AES
377 //!     - \b INT_RTCC
378 //!     - \b INT_DMA_ERR
379 //!     - \b INT_DMA_INT3
380 //!     - \b INT_DMA_INT2
381 //!     - \b INT_DMA_INT1
382 //!     - \b INT_DMA_INT0
383 //!     - \b INT_PORT1
384 //!     - \b INT_PORT2
385 //!     - \b INT_PORT3
386 //!     - \b INT_PORT4
387 //!     - \b INT_PORT5
388 //!     - \b INT_PORT6
389 //!
390 //! \return None.
391 //
392 //*****************************************************************************
393 extern void Interrupt_enableInterrupt(uint32_t interruptNumber);
394 
395 //*****************************************************************************
396 //
397 //! Disables an interrupt.
398 //!
399 //! \param interruptNumber specifies the interrupt to be disabled.
400 //!
401 //! The specified interrupt is disabled in the interrupt controller.  Other
402 //! enables for the interrupt (such as at the peripheral level) are unaffected
403 //! by this function.
404 //!
405 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
406 //! parameter
407 //!
408 //! \return None.
409 //
410 //*****************************************************************************
411 extern void Interrupt_disableInterrupt(uint32_t interruptNumber);
412 
413 //*****************************************************************************
414 //
415 //! Returns if a peripheral interrupt is enabled.
416 //!
417 //! \param interruptNumber specifies the interrupt to check.
418 //!
419 //! This function checks if the specified interrupt is enabled in the interrupt
420 //! controller.
421 //!
422 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
423 //! parameter
424 //!
425 //! \return A non-zero value if the interrupt is enabled.
426 //
427 //*****************************************************************************
428 extern bool Interrupt_isEnabled(uint32_t interruptNumber);
429 
430 //*****************************************************************************
431 //
432 //! Pends an interrupt.
433 //!
434 //! \param interruptNumber specifies the interrupt to be pended.
435 //!
436 //! The specified interrupt is pended in the interrupt controller.  Pending an
437 //! interrupt causes the interrupt controller to execute the corresponding
438 //! interrupt handler at the next available time, based on the current
439 //! interrupt state priorities. For example, if called by a higher priority
440 //! interrupt handler, the specified interrupt handler is not called until
441 //! after the current interrupt handler has completed execution.  The interrupt
442 //! must have been enabled for it to be called.
443 //!
444 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
445 //! parameter
446 //!
447 //! \return None.
448 //
449 //*****************************************************************************
450 extern void Interrupt_pendInterrupt(uint32_t interruptNumber);
451 
452 //*****************************************************************************
453 //
454 //! Un-pends an interrupt.
455 //!
456 //! \param interruptNumber specifies the interrupt to be un-pended.
457 //!
458 //! The specified interrupt is un-pended in the interrupt controller.  This
459 //! will cause any previously generated interrupts that have not been handled
460 //! yet (due to higher priority interrupts or the interrupt no having been
461 //! enabled yet) to be discarded.
462 //!
463 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
464 //! parameter
465 //!
466 //! \return None.
467 //
468 //*****************************************************************************
469 extern void Interrupt_unpendInterrupt(uint32_t interruptNumber);
470 
471 //*****************************************************************************
472 //
473 //! Sets the priority masking level
474 //!
475 //! \param priorityMask is the priority level that is masked.
476 //!
477 //! This function sets the interrupt priority masking level so that all
478 //! interrupts at the specified or lesser priority level are masked.  Masking
479 //! interrupts can be used to globally disable a set of interrupts with
480 //! priority below a predetermined threshold.  A value of 0 disables priority
481 //! masking.
482 //!
483 //! Smaller numbers correspond to higher interrupt priorities.  So for example
484 //! a priority level mask of 4 allows interrupts of priority level 0-3,
485 //! and interrupts with a numerical priority of 4 and greater are blocked.
486 //!
487 //! The hardware priority mechanism only looks at the upper N bits of the
488 //! priority level (where N is 3 for the MSP432 family), so any
489 //! prioritization must be performed in those bits.
490 //!
491 //! \return None.
492 //
493 //*****************************************************************************
494 extern void Interrupt_setPriorityMask(uint8_t priorityMask);
495 
496 //*****************************************************************************
497 //
498 //! Gets the priority masking level
499 //!
500 //! This function gets the current setting of the interrupt priority masking
501 //! level.  The value returned is the priority level such that all interrupts
502 //! of that and lesser priority are masked.  A value of 0 means that priority
503 //! masking is disabled.
504 //!
505 //! Smaller numbers correspond to higher interrupt priorities.  So for example
506 //! a priority level mask of 4 allows interrupts of priority level 0-3,
507 //! and interrupts with a numerical priority of 4 and greater are blocked.
508 //!
509 //! The hardware priority mechanism only looks at the upper N bits of the
510 //! priority level (where N is 3 for the MSP432 family), so any
511 //! prioritization must be performed in those bits.
512 //!
513 //! \return Returns the value of the interrupt priority level mask.
514 //
515 //*****************************************************************************
516 extern uint8_t Interrupt_getPriorityMask(void);
517 
518 //*****************************************************************************
519 //
520 //! Sets the address of the vector table. This function is for advanced users
521 //! who might want to switch between multiple instances of vector tables
522 //! (perhaps between flash/ram).
523 //!
524 //! \param addr is the new address of the vector table.
525 //!
526 //! \return None.
527 //
528 //*****************************************************************************
529 extern void Interrupt_setVectorTableAddress(uint32_t addr);
530 
531 //*****************************************************************************
532 //
533 //! Returns the address of the interrupt vector table.
534 //!
535 //! \return Address of the vector table.
536 //
537 //*****************************************************************************
538 extern uint32_t Interrupt_getVectorTableAddress(void);
539 
540 //*****************************************************************************
541 //
542 //! Enables the processor to sleep when exiting an ISR. For low power operation,
543 //! this is ideal as power cycles are not wasted with the processing required
544 //! for waking up from an ISR and going back to sleep.
545 //!
546 //! \return None
547 //
548 //*****************************************************************************
549 extern void Interrupt_enableSleepOnIsrExit(void);
550 
551 //*****************************************************************************
552 //
553 //! Disables the processor to sleep when exiting an ISR.
554 //!
555 //! \return None
556 //
557 //*****************************************************************************
558 extern void Interrupt_disableSleepOnIsrExit(void);
559 
560 //*****************************************************************************
561 //
562 // Mark the end of the C bindings section for C++ compilers.
563 //
564 //*****************************************************************************
565 #ifdef __cplusplus
566 }
567 #endif
568 
569 //*****************************************************************************
570 //
571 // Close the Doxygen group.
572 //! @}
573 //
574 //*****************************************************************************
575 
576 #endif // __INTERRUPT_H__
577