1 /*
2  * Copyright (c) 2017 Oticon A/S
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _NRF_HW_MODEL_PPI_H
7 #define _NRF_HW_MODEL_PPI_H
8 
9 #include "nrfx.h"
10 
11 #ifdef __cplusplus
12 extern "C"{
13 #endif
14 
15 //Signals/Events types HW models may send to the PPI
16 typedef enum { //Note that, for performance, it is better to leave commented the unused ones
17   //0 0x40000000 CLOCK
18   //0 0x40000000 POWER
19   //CLOCK:
20   CLOCK_EVENTS_HFCLKSTARTED ,
21   CLOCK_EVENTS_LFCLKSTARTED ,
22 //  CLOCK_EVENTS_DONE         ,
23 //  CLOCK_EVENTS_CTTO         ,
24   //POWER:
25 //  POWER_EVENTS_POFWARN     ,
26 //  POWER_EVENTS_SLEEPENTER  ,
27 //  POWER_EVENTS_SLEEPEXIT   ,
28 //  POWER_EVENTS_USBDETECTED ,
29 //  POWER_EVENTS_USBREMOVED  ,
30 //  POWER_EVENTS_USBPWRRDY   ,
31 
32   //1 0x40001000 RADIO
33   //RADIO:
34   RADIO_EVENTS_READY      ,
35   RADIO_EVENTS_ADDRESS    ,
36   RADIO_EVENTS_PAYLOAD    ,
37   RADIO_EVENTS_END        ,
38   RADIO_EVENTS_DISABLED   ,
39   RADIO_EVENTS_DEVMATCH   ,
40   RADIO_EVENTS_DEVMISS    ,
41   RADIO_EVENTS_RSSIEND    ,
42   RADIO_EVENTS_BCMATCH    ,
43   RADIO_EVENTS_CRCOK      ,
44   RADIO_EVENTS_CRCERROR   ,
45   RADIO_EVENTS_FRAMESTART ,
46   RADIO_EVENTS_EDEND      ,
47   RADIO_EVENTS_EDSTOPPED  ,
48   RADIO_EVENTS_CCAIDLE    ,
49   RADIO_EVENTS_CCABUSY    ,
50   RADIO_EVENTS_CCASTOPPED ,
51   RADIO_EVENTS_RATEBOOST  ,
52   RADIO_EVENTS_TXREADY    ,
53   RADIO_EVENTS_RXREADY    ,
54   RADIO_EVENTS_MHRMATCH   ,
55   RADIO_EVENTS_SYNC       ,
56   RADIO_EVENTS_PHYEND     ,
57   RADIO_EVENTS_CTEPRESENT ,
58 
59 //  2 0x40002000 UARTE
60 //  2 0x40002000 UART
61 //  3 0x40003000 TWIM
62 //  3 0x40003000 SPIS
63 //  3 0x40003000 SPIM
64 //  3 0x40003000 SPI
65 //  3 0x40003000 TWIS
66 //  3 0x40003000 TWI
67 //  4 0x40004000 TWIS
68 //  4 0x40004000 SPIS
69 //  4 0x40004000 SPIM
70 //  4 0x40004000 TWI
71 //  4 0x40004000 TWIM
72 //  4 0x40004000 SPI
73 //  5 0x40005000 NFCT
74 //  6 0x40006000 GPIOTE
75 //  7 0x40007000 SAADC
76 
77   //8 0x40008000 TIMER0
78   //TIMER
79   TIMER0_EVENTS_COMPARE_0 ,
80   TIMER0_EVENTS_COMPARE_1 ,
81   TIMER0_EVENTS_COMPARE_2 ,
82   TIMER0_EVENTS_COMPARE_3 ,
83 //  TIMER0_EVENTS_COMPARE_4 ,
84 //  TIMER0_EVENTS_COMPARE_5 ,
85 
86 //9 0x40009000 Timer 1
87   TIMER1_EVENTS_COMPARE_0 ,
88   TIMER1_EVENTS_COMPARE_1 ,
89   TIMER1_EVENTS_COMPARE_2 ,
90   TIMER1_EVENTS_COMPARE_3 ,
91 //  TIMER1_EVENTS_COMPARE_4 ,
92 //  TIMER1_EVENTS_COMPARE_5 ,
93 
94 //10 0x4000A000 Timer 2
95   TIMER2_EVENTS_COMPARE_0 ,
96   TIMER2_EVENTS_COMPARE_1 ,
97   TIMER2_EVENTS_COMPARE_2 ,
98   TIMER2_EVENTS_COMPARE_3 ,
99 //  TIMER2_EVENTS_COMPARE_4 ,
100 //  TIMER2_EVENTS_COMPARE_5 ,
101 
102 
103   //11 0x4000B000 RTC0
104   //RTC
105   RTC0_EVENTS_TICK      ,
106   RTC0_EVENTS_OVRFLW    ,
107   RTC0_EVENTS_COMPARE_0 ,
108   RTC0_EVENTS_COMPARE_1 ,
109   RTC0_EVENTS_COMPARE_2 ,
110   RTC0_EVENTS_COMPARE_3 ,
111 
112   //12 0x4000C000 Temperature sensor
113   TEMP_EVENTS_DATARDY,
114 
115   //13 0x4000D000 Random number generator
116   //RNG
117   RNG_EVENTS_VALRDY     ,
118 
119   //14 0x4000E000 ECB AES
120   ECB_EVENTS_ENDECB,
121   ECB_EVENTS_ERRORECB,
122 
123   //15 0x4000F000 AAR
124   AAR_EVENTS_END,
125   AAR_EVENTS_RESOLVED,
126   AAR_EVENTS_NOTRESOLVED,
127 
128   //15 0x4000F000 CCM AES
129   CCM_EVENTS_ENDKSGEN,
130   CCM_EVENTS_ENDCRYPT,
131   CCM_EVENTS_ERROR,
132 
133   //16 0x40010000 WDT
134 
135   //17 0x40011000 RTC1
136   RTC1_EVENTS_TICK      ,
137   RTC1_EVENTS_OVRFLW    ,
138   RTC1_EVENTS_COMPARE_0 ,
139   RTC1_EVENTS_COMPARE_1 ,
140   RTC1_EVENTS_COMPARE_2 ,
141   RTC1_EVENTS_COMPARE_3 ,
142 
143 //  18 0x40012000 QDEC
144 //  19 0x40013000 LPCOMP
145 //  19 0x40013000 COMP
146 //  20 0x40014000 EGU
147   EGU0_EVENTS_TRIGGERED_0, //Careful!: These EGU events (inside each instance) are assumed consecutive in the EGU model
148   EGU0_EVENTS_TRIGGERED_1,
149   EGU0_EVENTS_TRIGGERED_2,
150   EGU0_EVENTS_TRIGGERED_3,
151   EGU0_EVENTS_TRIGGERED_4,
152   EGU0_EVENTS_TRIGGERED_5,
153   EGU0_EVENTS_TRIGGERED_6,
154   EGU0_EVENTS_TRIGGERED_7,
155   EGU0_EVENTS_TRIGGERED_8,
156   EGU0_EVENTS_TRIGGERED_9,
157   EGU0_EVENTS_TRIGGERED_10,
158   EGU0_EVENTS_TRIGGERED_11,
159   EGU0_EVENTS_TRIGGERED_12,
160   EGU0_EVENTS_TRIGGERED_13,
161   EGU0_EVENTS_TRIGGERED_14,
162   EGU0_EVENTS_TRIGGERED_15,
163 //  20 0x40014000 SWI
164 //  21 0x40015000 EGU
165   EGU1_EVENTS_TRIGGERED_0,
166   EGU1_EVENTS_TRIGGERED_1,
167   EGU1_EVENTS_TRIGGERED_2,
168   EGU1_EVENTS_TRIGGERED_3,
169   EGU1_EVENTS_TRIGGERED_4,
170   EGU1_EVENTS_TRIGGERED_5,
171   EGU1_EVENTS_TRIGGERED_6,
172   EGU1_EVENTS_TRIGGERED_7,
173   EGU1_EVENTS_TRIGGERED_8,
174   EGU1_EVENTS_TRIGGERED_9,
175   EGU1_EVENTS_TRIGGERED_10,
176   EGU1_EVENTS_TRIGGERED_11,
177   EGU1_EVENTS_TRIGGERED_12,
178   EGU1_EVENTS_TRIGGERED_13,
179   EGU1_EVENTS_TRIGGERED_14,
180   EGU1_EVENTS_TRIGGERED_15,
181 //  21 0x40015000 SWI
182 //  22 0x40016000 EGU
183   EGU2_EVENTS_TRIGGERED_0,
184   EGU2_EVENTS_TRIGGERED_1,
185   EGU2_EVENTS_TRIGGERED_2,
186   EGU2_EVENTS_TRIGGERED_3,
187   EGU2_EVENTS_TRIGGERED_4,
188   EGU2_EVENTS_TRIGGERED_5,
189   EGU2_EVENTS_TRIGGERED_6,
190   EGU2_EVENTS_TRIGGERED_7,
191   EGU2_EVENTS_TRIGGERED_8,
192   EGU2_EVENTS_TRIGGERED_9,
193   EGU2_EVENTS_TRIGGERED_10,
194   EGU2_EVENTS_TRIGGERED_11,
195   EGU2_EVENTS_TRIGGERED_12,
196   EGU2_EVENTS_TRIGGERED_13,
197   EGU2_EVENTS_TRIGGERED_14,
198   EGU2_EVENTS_TRIGGERED_15,
199 //  22 0x40016000 SWI
200 //  23 0x40017000 EGU
201   EGU3_EVENTS_TRIGGERED_0,
202   EGU3_EVENTS_TRIGGERED_1,
203   EGU3_EVENTS_TRIGGERED_2,
204   EGU3_EVENTS_TRIGGERED_3,
205   EGU3_EVENTS_TRIGGERED_4,
206   EGU3_EVENTS_TRIGGERED_5,
207   EGU3_EVENTS_TRIGGERED_6,
208   EGU3_EVENTS_TRIGGERED_7,
209   EGU3_EVENTS_TRIGGERED_8,
210   EGU3_EVENTS_TRIGGERED_9,
211   EGU3_EVENTS_TRIGGERED_10,
212   EGU3_EVENTS_TRIGGERED_11,
213   EGU3_EVENTS_TRIGGERED_12,
214   EGU3_EVENTS_TRIGGERED_13,
215   EGU3_EVENTS_TRIGGERED_14,
216   EGU3_EVENTS_TRIGGERED_15,
217 //  23 0x40017000 SWI
218 //  24 0x40018000 SWI
219 //  24 0x40018000 EGU
220   EGU4_EVENTS_TRIGGERED_0,
221   EGU4_EVENTS_TRIGGERED_1,
222   EGU4_EVENTS_TRIGGERED_2,
223   EGU4_EVENTS_TRIGGERED_3,
224   EGU4_EVENTS_TRIGGERED_4,
225   EGU4_EVENTS_TRIGGERED_5,
226   EGU4_EVENTS_TRIGGERED_6,
227   EGU4_EVENTS_TRIGGERED_7,
228   EGU4_EVENTS_TRIGGERED_8,
229   EGU4_EVENTS_TRIGGERED_9,
230   EGU4_EVENTS_TRIGGERED_10,
231   EGU4_EVENTS_TRIGGERED_11,
232   EGU4_EVENTS_TRIGGERED_12,
233   EGU4_EVENTS_TRIGGERED_13,
234   EGU4_EVENTS_TRIGGERED_14,
235   EGU4_EVENTS_TRIGGERED_15,
236 //  25 0x40019000 SWI
237 //  25 0x40019000 EGU
238   EGU5_EVENTS_TRIGGERED_0,
239   EGU5_EVENTS_TRIGGERED_1,
240   EGU5_EVENTS_TRIGGERED_2,
241   EGU5_EVENTS_TRIGGERED_3,
242   EGU5_EVENTS_TRIGGERED_4,
243   EGU5_EVENTS_TRIGGERED_5,
244   EGU5_EVENTS_TRIGGERED_6,
245   EGU5_EVENTS_TRIGGERED_7,
246   EGU5_EVENTS_TRIGGERED_8,
247   EGU5_EVENTS_TRIGGERED_9,
248   EGU5_EVENTS_TRIGGERED_10,
249   EGU5_EVENTS_TRIGGERED_11,
250   EGU5_EVENTS_TRIGGERED_12,
251   EGU5_EVENTS_TRIGGERED_13,
252   EGU5_EVENTS_TRIGGERED_14,
253   EGU5_EVENTS_TRIGGERED_15,
254 
255 //  26 0x4001A000 TIMER3
256     TIMER3_EVENTS_COMPARE_0 ,
257     TIMER3_EVENTS_COMPARE_1 ,
258     TIMER3_EVENTS_COMPARE_2 ,
259     TIMER3_EVENTS_COMPARE_3 ,
260     TIMER3_EVENTS_COMPARE_4 ,
261     TIMER3_EVENTS_COMPARE_5 ,
262 
263 //  27 0x4001B000 TIMER4
264     TIMER4_EVENTS_COMPARE_0 ,
265     TIMER4_EVENTS_COMPARE_1 ,
266     TIMER4_EVENTS_COMPARE_2 ,
267     TIMER4_EVENTS_COMPARE_3 ,
268     TIMER4_EVENTS_COMPARE_4 ,
269     TIMER4_EVENTS_COMPARE_5 ,
270 
271 //  28 0x4001C000 PWM
272 //  29 0x4001D000 PDM
273 //  30 0x4001E000 ACL
274 //  30 0x4001E000 NVMC
275 
276 //31 0x4001F000 PPI
277 //PPI
278 //No events
279 
280 //  32 0x40020000 MWU
281 //  33 0x40021000 PWM
282 //  34 0x40022000 PWM
283 //  35 0x40023000 SPIM
284 //  35 0x40023000 SPIS
285 //  35 0x40023000 SPI
286 //  36 0x40024000 RTC
287   RTC2_EVENTS_TICK      ,
288   RTC2_EVENTS_OVRFLW    ,
289   RTC2_EVENTS_COMPARE_0 ,
290   RTC2_EVENTS_COMPARE_1 ,
291   RTC2_EVENTS_COMPARE_2 ,
292   RTC2_EVENTS_COMPARE_3 ,
293 
294 //  37 0x40025000 I2S
295 //  38 0x40026000 FPU
296 //  39 0x40027000 USBD
297 //  40 0x40028000 UARTE
298 //  41 0x40029000 QSPI
299 //  45 0x4002D000 PWM
300 //  47 0x4002F000 SPIM
301 //  0 0x50000000 GPIO
302 //  0 0x50000000 GPIO
303 //  0 0x50000300 GPIO
304 //  42 0x5002A000 CRYPTOCELL
305 //  N/A 0x10000000 FICR
306 //  N/A 0x10001000 UICR
307 
308   NUMBER_PPI_EVENTS
309 } ppi_event_types_t;
310 
311 #define NUMBER_PPI_CHANNELS 32
312 
313 void nrf_ppi_init();
314 void nrf_ppi_clean_up();
315 void nrf_ppi_event(ppi_event_types_t event);
316 void nrf_ppi_regw_sideeffects();
317 void nrf_ppi_regw_sideeffects_TEP(int ch_nbr);
318 void nrf_ppi_regw_sideeffects_EEP(int ch_nbr);
319 void nrf_ppi_regw_sideeffects_FORK_TEP(int ch_nbr);
320 void nrf_ppi_regw_sideeffects_TASKS_CHG_DIS(int i);
321 void nrf_ppi_regw_sideeffects_CHENSET();
322 void nrf_ppi_regw_sideeffects_CHENCLR();
323 
324 #ifdef __cplusplus
325 }
326 #endif
327 
328 #endif
329