1 /* 2 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 3 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, this 10 list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its 17 contributors may be used to endorse or promote products derived from this 18 software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 * 32 * @file nrf5340_network.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 07. January 2025 36 * @note Generated by SVDConv V3.3.35 on Tuesday, 07.01.2025 15:34:28 37 * from File 'nrf5340_network.svd', 38 * last modified on Friday, 13.12.2024 08:41:10 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf5340_network 49 * @{ 50 */ 51 52 53 #ifndef NRF5340_NETWORK_H 54 #define NRF5340_NETWORK_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 82 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 83 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 84 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 85 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 86 /* ====================================== nrf5340_network Specific Interrupt Numbers ======================================= */ 87 CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ 88 RADIO_IRQn = 8, /*!< 8 RADIO */ 89 RNG_IRQn = 9, /*!< 9 RNG */ 90 GPIOTE_IRQn = 10, /*!< 10 GPIOTE */ 91 WDT_IRQn = 11, /*!< 11 WDT */ 92 TIMER0_IRQn = 12, /*!< 12 TIMER0 */ 93 ECB_IRQn = 13, /*!< 13 ECB */ 94 AAR_CCM_IRQn = 14, /*!< 14 AAR_CCM */ 95 TEMP_IRQn = 16, /*!< 16 TEMP */ 96 RTC0_IRQn = 17, /*!< 17 RTC0 */ 97 IPC_IRQn = 18, /*!< 18 IPC */ 98 SERIAL0_IRQn = 19, /*!< 19 SERIAL0 */ 99 EGU0_IRQn = 20, /*!< 20 EGU0 */ 100 RTC1_IRQn = 22, /*!< 22 RTC1 */ 101 TIMER1_IRQn = 24, /*!< 24 TIMER1 */ 102 TIMER2_IRQn = 25, /*!< 25 TIMER2 */ 103 SWI0_IRQn = 26, /*!< 26 SWI0 */ 104 SWI1_IRQn = 27, /*!< 27 SWI1 */ 105 SWI2_IRQn = 28, /*!< 28 SWI2 */ 106 SWI3_IRQn = 29 /*!< 29 SWI3 */ 107 } IRQn_Type; 108 109 110 111 /* =========================================================================================================================== */ 112 /* ================ Processor and Core Peripheral Section ================ */ 113 /* =========================================================================================================================== */ 114 115 /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ 116 #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ 117 #define __INTERRUPTS_MAX 129 /*!< Top interrupt number */ 118 #define __DSP_PRESENT 0 /*!< DSP present or not */ 119 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 120 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 121 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 122 #define __MPU_PRESENT 1 /*!< MPU present */ 123 #define __FPU_PRESENT 0 /*!< FPU present */ 124 #define __FPU_DP 0 /*!< unused, Device has no FPU */ 125 #define __SAUREGION_PRESENT 0 /*!< SAU region present */ 126 127 128 /** @} */ /* End of group Configuration_of_CMSIS */ 129 130 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 131 #include "system_nrf5340_network.h" /*!< nrf5340_network System */ 132 133 #ifndef __IM /*!< Fallback for older CMSIS versions */ 134 #define __IM __I 135 #endif 136 #ifndef __OM /*!< Fallback for older CMSIS versions */ 137 #define __OM __O 138 #endif 139 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 140 #define __IOM __IO 141 #endif 142 143 144 /* =========================================================================================================================== */ 145 /* ================ Device Specific Cluster Section ================ */ 146 /* =========================================================================================================================== */ 147 148 149 /** @addtogroup Device_Peripheral_clusters 150 * @{ 151 */ 152 153 154 /** 155 * @brief FICR_INFO [INFO] (Device info) 156 */ 157 typedef struct { 158 __IM uint32_t CONFIGID; /*!< (@ 0x00000000) Configuration identifier */ 159 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 160 __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ 161 __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production 162 configuration */ 163 __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ 164 __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 165 __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 166 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size in bytes */ 167 __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 168 __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 169 } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 170 171 172 /** 173 * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 174 */ 175 typedef struct { 176 __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */ 177 __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 178 } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 179 180 181 /** 182 * @brief VREQCTRL_VREGRADIO [VREGRADIO] (Unspecified) 183 */ 184 typedef struct { 185 __IOM uint32_t VREQH; /*!< (@ 0x00000000) Request high voltage on RADIO After requesting 186 high voltage, the user must wait until VREQHREADY 187 is set to Ready */ 188 __IM uint32_t RESERVED; 189 __IM uint32_t VREQHREADY; /*!< (@ 0x00000008) High voltage on RADIO is ready */ 190 } VREQCTRL_VREGRADIO_Type; /*!< Size = 12 (0xc) */ 191 192 193 /** 194 * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) 195 */ 196 typedef struct { 197 __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ 198 __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if 199 data sent from the debugger to the CPU has 200 been read. */ 201 __IM uint32_t RESERVED[30]; 202 __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ 203 __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if 204 the data sent from the CPU to the debugger 205 has been read. */ 206 } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ 207 208 209 /** 210 * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) 211 */ 212 typedef struct { 213 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE 214 register from being written until next reset. */ 215 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register 216 and performs an ERASEALL operation. */ 217 } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ 218 219 220 /** 221 * @brief CTRLAPPERI_APPROTECT [APPROTECT] (Unspecified) 222 */ 223 typedef struct { 224 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the APPROTECT.DISABLE register 225 from being written to until next reset. */ 226 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the APPROTECT register 227 and enables debug access to non-secure mode. */ 228 } CTRLAPPERI_APPROTECT_Type; /*!< Size = 8 (0x8) */ 229 230 231 /** 232 * @brief RADIO_PSEL [PSEL] (Unspecified) 233 */ 234 typedef struct { 235 __IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin select for DFE pin 236 n */ 237 } RADIO_PSEL_Type; /*!< Size = 32 (0x20) */ 238 239 240 /** 241 * @brief RADIO_DFEPACKET [DFEPACKET] (DFE packet EasyDMA channel) 242 */ 243 typedef struct { 244 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 245 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 246 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of samples transferred in the last transaction */ 247 } RADIO_DFEPACKET_Type; /*!< Size = 12 (0xc) */ 248 249 250 /** 251 * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 252 */ 253 typedef struct { 254 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 255 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 256 } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 257 258 259 /** 260 * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 261 */ 262 typedef struct { 263 __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 264 for task CHG[n].EN */ 265 __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 266 for task CHG[n].DIS */ 267 } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 268 269 270 /** 271 * @brief SPIM_PSEL [PSEL] (Unspecified) 272 */ 273 typedef struct { 274 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 275 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 276 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 277 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ 278 } SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ 279 280 281 /** 282 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 283 */ 284 typedef struct { 285 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 286 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 287 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 288 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 289 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 290 291 292 /** 293 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 294 */ 295 typedef struct { 296 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 297 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ 298 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 299 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 300 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 301 302 303 /** 304 * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) 305 */ 306 typedef struct { 307 __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ 308 __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge 309 of SCK. When SHORTS.END_START is used, this 310 is also the minimum duration CSN must stay 311 high between transactions. */ 312 } SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ 313 314 315 /** 316 * @brief SPIS_PSEL [PSEL] (Unspecified) 317 */ 318 typedef struct { 319 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 320 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 321 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 322 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 323 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 324 325 326 /** 327 * @brief SPIS_RXD [RXD] (Unspecified) 328 */ 329 typedef struct { 330 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 331 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 332 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 333 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 334 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 335 336 337 /** 338 * @brief SPIS_TXD [TXD] (Unspecified) 339 */ 340 typedef struct { 341 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 342 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 343 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 344 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 345 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 346 347 348 /** 349 * @brief TWIM_PSEL [PSEL] (Unspecified) 350 */ 351 typedef struct { 352 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 353 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 354 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 355 356 357 /** 358 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 359 */ 360 typedef struct { 361 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 362 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 363 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 364 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 365 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 366 367 368 /** 369 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 370 */ 371 typedef struct { 372 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 373 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 374 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 375 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 376 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 377 378 379 /** 380 * @brief TWIS_PSEL [PSEL] (Unspecified) 381 */ 382 typedef struct { 383 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 384 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 385 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 386 387 388 /** 389 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 390 */ 391 typedef struct { 392 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 393 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 394 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 395 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 396 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 397 398 399 /** 400 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 401 */ 402 typedef struct { 403 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 404 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 405 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 406 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 407 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 408 409 410 /** 411 * @brief UARTE_PSEL [PSEL] (Unspecified) 412 */ 413 typedef struct { 414 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 415 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 416 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 417 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 418 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 419 420 421 /** 422 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 423 */ 424 typedef struct { 425 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 426 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 427 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 428 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 429 430 431 /** 432 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 433 */ 434 typedef struct { 435 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 436 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 437 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 438 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 439 440 441 /** 442 * @brief ACL_ACL [ACL] (Unspecified) 443 */ 444 typedef struct { 445 __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region 446 to protect. The start address must be word-aligned. */ 447 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect 448 counting from address ACL[n].ADDR. Writing 449 a '0' has no effect. */ 450 __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region 451 n as defined by start address ACL[n].ADDR 452 and size ACL[n].SIZE */ 453 __IM uint32_t RESERVED; 454 } ACL_ACL_Type; /*!< Size = 16 (0x10) */ 455 456 457 /** 458 * @brief VMC_RAM [RAM] (Unspecified) 459 */ 460 typedef struct { 461 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAM[n] power control register */ 462 __IOM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAM[n] power control set 463 register */ 464 __IOM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAM[n] power control clear 465 register */ 466 __IM uint32_t RESERVED; 467 } VMC_RAM_Type; /*!< Size = 16 (0x10) */ 468 469 470 /** @} */ /* End of group Device_Peripheral_clusters */ 471 472 473 /* =========================================================================================================================== */ 474 /* ================ Device Specific Peripheral Section ================ */ 475 /* =========================================================================================================================== */ 476 477 478 /** @addtogroup Device_Peripheral_peripherals 479 * @{ 480 */ 481 482 483 484 /* =========================================================================================================================== */ 485 /* ================ FICR_NS ================ */ 486 /* =========================================================================================================================== */ 487 488 489 /** 490 * @brief Factory Information Configuration Registers (FICR_NS) 491 */ 492 493 typedef struct { /*!< (@ 0x01FF0000) FICR_NS Structure */ 494 __IM uint32_t RESERVED[128]; 495 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 496 __IM uint32_t RESERVED1[21]; 497 __IM uint32_t ER[4]; /*!< (@ 0x00000280) Description collection: Encryption Root, word 498 n */ 499 __IM uint32_t IR[4]; /*!< (@ 0x00000290) Description collection: Identity Root, word n */ 500 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000002A0) Device address type */ 501 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000002A4) Description collection: Device address n */ 502 __IM uint32_t RESERVED2[21]; 503 __IOM FICR_TRIMCNF_Type TRIMCNF[32]; /*!< (@ 0x00000300) Unspecified */ 504 } NRF_FICR_Type; /*!< Size = 1024 (0x400) */ 505 506 507 508 /* =========================================================================================================================== */ 509 /* ================ UICR_NS ================ */ 510 /* =========================================================================================================================== */ 511 512 513 /** 514 * @brief User Information Configuration Registers (UICR_NS) 515 */ 516 517 typedef struct { /*!< (@ 0x01FF8000) UICR_NS Structure */ 518 __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ 519 __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000004) Erase protection */ 520 __IM uint32_t RESERVED[126]; 521 __IOM uint32_t NRFFW[32]; /*!< (@ 0x00000200) Description collection: Reserved for Nordic firmware 522 design */ 523 __IM uint32_t RESERVED1[32]; 524 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000300) Description collection: Reserved for customer */ 525 } NRF_UICR_Type; /*!< Size = 896 (0x380) */ 526 527 528 529 /* =========================================================================================================================== */ 530 /* ================ CTI_NS ================ */ 531 /* =========================================================================================================================== */ 532 533 534 /** 535 * @brief Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. (CTI_NS) 536 */ 537 538 typedef struct { /*!< (@ 0xE0042000) CTI_NS Structure */ 539 __IOM uint32_t CTICONTROL; /*!< (@ 0x00000000) CTI Control register */ 540 __IM uint32_t RESERVED[3]; 541 __OM uint32_t CTIINTACK; /*!< (@ 0x00000010) CTI Interrupt Acknowledge register */ 542 __IOM uint32_t CTIAPPSET; /*!< (@ 0x00000014) CTI Application Trigger Set register */ 543 __OM uint32_t CTIAPPCLEAR; /*!< (@ 0x00000018) CTI Application Trigger Clear register */ 544 __OM uint32_t CTIAPPPULSE; /*!< (@ 0x0000001C) CTI Application Pulse register */ 545 __IOM uint32_t CTIINEN[8]; /*!< (@ 0x00000020) Description collection: CTI Trigger to Channel 546 Enable register */ 547 __IM uint32_t RESERVED1[24]; 548 __IOM uint32_t CTIOUTEN[8]; /*!< (@ 0x000000A0) Description collection: CTI Channel to Trigger 549 Enable register */ 550 __IM uint32_t RESERVED2[28]; 551 __IM uint32_t CTITRIGINSTATUS; /*!< (@ 0x00000130) CTI Trigger In Status register */ 552 __IM uint32_t CTITRIGOUTSTATUS; /*!< (@ 0x00000134) CTI Trigger Out Status register */ 553 __IM uint32_t CTICHINSTATUS; /*!< (@ 0x00000138) CTI Channel In Status register */ 554 __IM uint32_t RESERVED3; 555 __IOM uint32_t CTIGATE; /*!< (@ 0x00000140) Enable CTI Channel Gate register */ 556 __IM uint32_t RESERVED4[926]; 557 __IM uint32_t DEVARCH; /*!< (@ 0x00000FBC) Device Architecture register */ 558 __IM uint32_t RESERVED5[2]; 559 __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Device Configuration register */ 560 __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) Device Type Identifier register */ 561 __IM uint32_t PIDR4; /*!< (@ 0x00000FD0) Peripheral ID4 Register */ 562 __IM uint32_t PIDR5; /*!< (@ 0x00000FD4) Peripheral ID5 register */ 563 __IM uint32_t PIDR6; /*!< (@ 0x00000FD8) Peripheral ID6 register */ 564 __IM uint32_t PIDR7; /*!< (@ 0x00000FDC) Peripheral ID7 register */ 565 __IM uint32_t PIDR0; /*!< (@ 0x00000FE0) Peripheral ID0 Register */ 566 __IM uint32_t PIDR1; /*!< (@ 0x00000FE4) Peripheral ID1 Register */ 567 __IM uint32_t PIDR2; /*!< (@ 0x00000FE8) Peripheral ID2 Register */ 568 __IM uint32_t PIDR3; /*!< (@ 0x00000FEC) Peripheral ID3 Register */ 569 __IM uint32_t CIDR0; /*!< (@ 0x00000FF0) Component ID0 Register */ 570 __IM uint32_t CIDR1; /*!< (@ 0x00000FF4) Component ID1 Register */ 571 __IM uint32_t CIDR2; /*!< (@ 0x00000FF8) Component ID2 Register */ 572 __IM uint32_t CIDR3; /*!< (@ 0x00000FFC) Component ID3 Register */ 573 } NRF_CTI_Type; /*!< Size = 4096 (0x1000) */ 574 575 576 577 /* =========================================================================================================================== */ 578 /* ================ DCNF_NS ================ */ 579 /* =========================================================================================================================== */ 580 581 582 /** 583 * @brief Domain configuration management (DCNF_NS) 584 */ 585 586 typedef struct { /*!< (@ 0x41000000) DCNF_NS Structure */ 587 __IM uint32_t RESERVED[264]; 588 __IM uint32_t CPUID; /*!< (@ 0x00000420) CPU ID of this subsystem */ 589 } NRF_DCNF_Type; /*!< Size = 1060 (0x424) */ 590 591 592 593 /* =========================================================================================================================== */ 594 /* ================ VREQCTRL_NS ================ */ 595 /* =========================================================================================================================== */ 596 597 598 /** 599 * @brief Voltage request control (VREQCTRL_NS) 600 */ 601 602 typedef struct { /*!< (@ 0x41004000) VREQCTRL_NS Structure */ 603 __IM uint32_t RESERVED[320]; 604 __IOM VREQCTRL_VREGRADIO_Type VREGRADIO; /*!< (@ 0x00000500) Unspecified */ 605 } NRF_VREQCTRL_Type; /*!< Size = 1292 (0x50c) */ 606 607 608 609 /* =========================================================================================================================== */ 610 /* ================ CLOCK_NS ================ */ 611 /* =========================================================================================================================== */ 612 613 614 /** 615 * @brief Clock management (CLOCK_NS) 616 */ 617 618 typedef struct { /*!< (@ 0x41005000) CLOCK_NS Structure */ 619 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK128M/HFCLK64M source as selected in 620 HFCLKSRC */ 621 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK128M/HFCLK64M source */ 622 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source as selected in LFCLKSRC */ 623 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 624 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 625 __IM uint32_t RESERVED[27]; 626 __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 627 __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 628 __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 629 __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 630 __IOM uint32_t SUBSCRIBE_CAL; /*!< (@ 0x00000090) Subscribe configuration for task CAL */ 631 __IM uint32_t RESERVED1[27]; 632 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK128M/HFCLK64M source started */ 633 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK source started */ 634 __IM uint32_t RESERVED2[5]; 635 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000011C) Calibration of LFRC oscillator complete event */ 636 __IM uint32_t RESERVED3[24]; 637 __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 638 __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 639 __IM uint32_t RESERVED4[5]; 640 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x0000019C) Publish configuration for event DONE */ 641 __IM uint32_t RESERVED5[88]; 642 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 643 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 644 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 645 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 646 __IM uint32_t RESERVED6[62]; 647 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 648 triggered */ 649 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) Status indicating which HFCLK128M/HFCLK64M source 650 is running This register value in any CLOCK 651 instance reflects status only due to configurations/action 652 in that CLOCK instance. */ 653 __IM uint32_t RESERVED7; 654 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 655 triggered */ 656 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Status indicating which LFCLK source is running 657 This register value in any CLOCK instance 658 reflects status only due to configurations/actions 659 in that CLOCK instance. */ 660 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 661 task was triggered */ 662 __IM uint32_t RESERVED8[61]; 663 __IOM uint32_t HFCLKSRC; /*!< (@ 0x00000514) Clock source for HFCLK128M/HFCLK64M */ 664 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for LFCLK */ 665 __IM uint32_t RESERVED9[15]; 666 __IOM uint32_t HFCLKCTRL; /*!< (@ 0x00000558) HFCLK128M frequency configuration */ 667 __IM uint32_t RESERVED10[5]; 668 __IOM uint32_t HFCLKALWAYSRUN; /*!< (@ 0x00000570) Automatic or manual control of HFCLK128M/HFCLK64M */ 669 __IOM uint32_t LFCLKALWAYSRUN; /*!< (@ 0x00000574) Automatic or manual control of LFCLK */ 670 } NRF_CLOCK_Type; /*!< Size = 1400 (0x578) */ 671 672 673 674 /* =========================================================================================================================== */ 675 /* ================ POWER_NS ================ */ 676 /* =========================================================================================================================== */ 677 678 679 /** 680 * @brief Power control (POWER_NS) 681 */ 682 683 typedef struct { /*!< (@ 0x41005000) POWER_NS Structure */ 684 __IM uint32_t RESERVED[30]; 685 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 686 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-Power mode (variable latency) */ 687 __IM uint32_t RESERVED1[30]; 688 __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 689 __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 690 __IM uint32_t RESERVED2[2]; 691 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 692 __IM uint32_t RESERVED3[2]; 693 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 694 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 695 __IM uint32_t RESERVED4[27]; 696 __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 697 __IM uint32_t RESERVED5[2]; 698 __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 699 __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 700 __IM uint32_t RESERVED6[89]; 701 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 702 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 703 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 704 __IM uint32_t RESERVED7[132]; 705 __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 706 register */ 707 } NRF_POWER_Type; /*!< Size = 1316 (0x524) */ 708 709 710 711 /* =========================================================================================================================== */ 712 /* ================ RESET_NS ================ */ 713 /* =========================================================================================================================== */ 714 715 716 /** 717 * @brief Reset control (RESET_NS) 718 */ 719 720 typedef struct { /*!< (@ 0x41005000) RESET_NS Structure */ 721 __IM uint32_t RESERVED[256]; 722 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 723 } NRF_RESET_Type; /*!< Size = 1028 (0x404) */ 724 725 726 727 /* =========================================================================================================================== */ 728 /* ================ CTRLAP_NS ================ */ 729 /* =========================================================================================================================== */ 730 731 732 /** 733 * @brief Control access port (CTRLAP_NS) 734 */ 735 736 typedef struct { /*!< (@ 0x41006000) CTRLAP_NS Structure */ 737 __IM uint32_t RESERVED[256]; 738 __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */ 739 __IM uint32_t RESERVED1[30]; 740 __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ 741 __IM uint32_t RESERVED2[14]; 742 __IOM CTRLAPPERI_APPROTECT_Type APPROTECT; /*!< (@ 0x00000540) Unspecified */ 743 __IM uint32_t RESERVED3[46]; 744 __IM uint32_t STATUS; /*!< (@ 0x00000600) Status bits for CTRL-AP peripheral. */ 745 } NRF_CTRLAPPERI_Type; /*!< Size = 1540 (0x604) */ 746 747 748 749 /* =========================================================================================================================== */ 750 /* ================ RADIO_NS ================ */ 751 /* =========================================================================================================================== */ 752 753 754 /** 755 * @brief 2.4 GHz radio (RADIO_NS) 756 */ 757 758 typedef struct { /*!< (@ 0x41008000) RADIO_NS Structure */ 759 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 760 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 761 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 762 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 763 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 764 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 765 the receive signal strength */ 766 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 767 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 768 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 769 __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE 770 802.15.4 mode */ 771 __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ 772 __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE 773 802.15.4 mode */ 774 __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ 775 __IM uint32_t RESERVED[19]; 776 __IOM uint32_t SUBSCRIBE_TXEN; /*!< (@ 0x00000080) Subscribe configuration for task TXEN */ 777 __IOM uint32_t SUBSCRIBE_RXEN; /*!< (@ 0x00000084) Subscribe configuration for task RXEN */ 778 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000088) Subscribe configuration for task START */ 779 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x0000008C) Subscribe configuration for task STOP */ 780 __IOM uint32_t SUBSCRIBE_DISABLE; /*!< (@ 0x00000090) Subscribe configuration for task DISABLE */ 781 __IOM uint32_t SUBSCRIBE_RSSISTART; /*!< (@ 0x00000094) Subscribe configuration for task RSSISTART */ 782 __IOM uint32_t SUBSCRIBE_RSSISTOP; /*!< (@ 0x00000098) Subscribe configuration for task RSSISTOP */ 783 __IOM uint32_t SUBSCRIBE_BCSTART; /*!< (@ 0x0000009C) Subscribe configuration for task BCSTART */ 784 __IOM uint32_t SUBSCRIBE_BCSTOP; /*!< (@ 0x000000A0) Subscribe configuration for task BCSTOP */ 785 __IOM uint32_t SUBSCRIBE_EDSTART; /*!< (@ 0x000000A4) Subscribe configuration for task EDSTART */ 786 __IOM uint32_t SUBSCRIBE_EDSTOP; /*!< (@ 0x000000A8) Subscribe configuration for task EDSTOP */ 787 __IOM uint32_t SUBSCRIBE_CCASTART; /*!< (@ 0x000000AC) Subscribe configuration for task CCASTART */ 788 __IOM uint32_t SUBSCRIBE_CCASTOP; /*!< (@ 0x000000B0) Subscribe configuration for task CCASTOP */ 789 __IM uint32_t RESERVED1[19]; 790 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 791 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 792 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 793 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 794 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 795 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 796 packet */ 797 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 798 received packet */ 799 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 800 __IM uint32_t RESERVED2[2]; 801 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 802 __IM uint32_t RESERVED3; 803 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 804 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 805 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ 806 __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new 807 ED sample is ready for readout from the 808 RADIO.EDSAMPLE register. */ 809 __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ 810 __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ 811 __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ 812 __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ 813 __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed 814 from Ble_LR125Kbit to Ble_LR500Kbit. */ 815 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 816 TX path */ 817 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 818 RX path */ 819 __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ 820 __IM uint32_t RESERVED4[2]; 821 __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator */ 822 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received 823 from air */ 824 __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving 825 CTEInfo byte) */ 826 __IM uint32_t RESERVED5[3]; 827 __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ 828 __IOM uint32_t PUBLISH_ADDRESS; /*!< (@ 0x00000184) Publish configuration for event ADDRESS */ 829 __IOM uint32_t PUBLISH_PAYLOAD; /*!< (@ 0x00000188) Publish configuration for event PAYLOAD */ 830 __IOM uint32_t PUBLISH_END; /*!< (@ 0x0000018C) Publish configuration for event END */ 831 __IOM uint32_t PUBLISH_DISABLED; /*!< (@ 0x00000190) Publish configuration for event DISABLED */ 832 __IOM uint32_t PUBLISH_DEVMATCH; /*!< (@ 0x00000194) Publish configuration for event DEVMATCH */ 833 __IOM uint32_t PUBLISH_DEVMISS; /*!< (@ 0x00000198) Publish configuration for event DEVMISS */ 834 __IOM uint32_t PUBLISH_RSSIEND; /*!< (@ 0x0000019C) Publish configuration for event RSSIEND */ 835 __IM uint32_t RESERVED6[2]; 836 __IOM uint32_t PUBLISH_BCMATCH; /*!< (@ 0x000001A8) Publish configuration for event BCMATCH */ 837 __IM uint32_t RESERVED7; 838 __IOM uint32_t PUBLISH_CRCOK; /*!< (@ 0x000001B0) Publish configuration for event CRCOK */ 839 __IOM uint32_t PUBLISH_CRCERROR; /*!< (@ 0x000001B4) Publish configuration for event CRCERROR */ 840 __IOM uint32_t PUBLISH_FRAMESTART; /*!< (@ 0x000001B8) Publish configuration for event FRAMESTART */ 841 __IOM uint32_t PUBLISH_EDEND; /*!< (@ 0x000001BC) Publish configuration for event EDEND */ 842 __IOM uint32_t PUBLISH_EDSTOPPED; /*!< (@ 0x000001C0) Publish configuration for event EDSTOPPED */ 843 __IOM uint32_t PUBLISH_CCAIDLE; /*!< (@ 0x000001C4) Publish configuration for event CCAIDLE */ 844 __IOM uint32_t PUBLISH_CCABUSY; /*!< (@ 0x000001C8) Publish configuration for event CCABUSY */ 845 __IOM uint32_t PUBLISH_CCASTOPPED; /*!< (@ 0x000001CC) Publish configuration for event CCASTOPPED */ 846 __IOM uint32_t PUBLISH_RATEBOOST; /*!< (@ 0x000001D0) Publish configuration for event RATEBOOST */ 847 __IOM uint32_t PUBLISH_TXREADY; /*!< (@ 0x000001D4) Publish configuration for event TXREADY */ 848 __IOM uint32_t PUBLISH_RXREADY; /*!< (@ 0x000001D8) Publish configuration for event RXREADY */ 849 __IOM uint32_t PUBLISH_MHRMATCH; /*!< (@ 0x000001DC) Publish configuration for event MHRMATCH */ 850 __IM uint32_t RESERVED8[2]; 851 __IOM uint32_t PUBLISH_SYNC; /*!< (@ 0x000001E8) Publish configuration for event SYNC */ 852 __IOM uint32_t PUBLISH_PHYEND; /*!< (@ 0x000001EC) Publish configuration for event PHYEND */ 853 __IOM uint32_t PUBLISH_CTEPRESENT; /*!< (@ 0x000001F0) Publish configuration for event CTEPRESENT */ 854 __IM uint32_t RESERVED9[3]; 855 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 856 __IM uint32_t RESERVED10[64]; 857 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 858 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 859 __IM uint32_t RESERVED11[61]; 860 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 861 __IM uint32_t RESERVED12; 862 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 863 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 864 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 865 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 866 __IM uint32_t RESERVED13[13]; 867 __IM uint32_t CTESTATUS; /*!< (@ 0x0000044C) CTEInfo parsed from received packet */ 868 __IM uint32_t RESERVED14[2]; 869 __IM uint32_t DFESTATUS; /*!< (@ 0x00000458) DFE status information */ 870 __IM uint32_t RESERVED15[42]; 871 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 872 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 873 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 874 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 875 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 876 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 877 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 878 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 879 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 880 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 881 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 882 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 883 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 884 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 885 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 886 __IM uint32_t RESERVED16; 887 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 888 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 889 __IM uint32_t RESERVED17; 890 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 891 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 892 __IM uint32_t RESERVED18[2]; 893 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 894 __IM uint32_t RESERVED19[39]; 895 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 896 n */ 897 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 898 n */ 899 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 900 __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ 901 __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ 902 __IM uint32_t RESERVED20; 903 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 904 __IM uint32_t RESERVED21[3]; 905 __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ 906 __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ 907 __IM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ 908 __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ 909 __IM uint32_t RESERVED22[164]; 910 __IOM uint32_t DFEMODE; /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure 911 (AOD) */ 912 __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000904) Configuration for CTE inline mode */ 913 __IM uint32_t RESERVED23[2]; 914 __IOM uint32_t DFECTRL1; /*!< (@ 0x00000910) Various configuration for Direction finding */ 915 __IOM uint32_t DFECTRL2; /*!< (@ 0x00000914) Start offset for Direction finding */ 916 __IM uint32_t RESERVED24[4]; 917 __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000928) GPIO patterns to be used for each antenna */ 918 __IOM uint32_t CLEARPATTERN; /*!< (@ 0x0000092C) Clear the GPIO pattern array for antenna control */ 919 __IOM RADIO_PSEL_Type PSEL; /*!< (@ 0x00000930) Unspecified */ 920 __IOM RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000950) DFE packet EasyDMA channel */ 921 __IM uint32_t RESERVED25[424]; 922 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 923 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 924 925 926 927 /* =========================================================================================================================== */ 928 /* ================ RNG_NS ================ */ 929 /* =========================================================================================================================== */ 930 931 932 /** 933 * @brief Random Number Generator (RNG_NS) 934 */ 935 936 typedef struct { /*!< (@ 0x41009000) RNG_NS Structure */ 937 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 938 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 939 __IM uint32_t RESERVED[30]; 940 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 941 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 942 __IM uint32_t RESERVED1[30]; 943 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 944 written to the VALUE register */ 945 __IM uint32_t RESERVED2[31]; 946 __IOM uint32_t PUBLISH_VALRDY; /*!< (@ 0x00000180) Publish configuration for event VALRDY */ 947 __IM uint32_t RESERVED3[31]; 948 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 949 __IM uint32_t RESERVED4[64]; 950 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 951 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 952 __IM uint32_t RESERVED5[126]; 953 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 954 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 955 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 956 957 958 959 /* =========================================================================================================================== */ 960 /* ================ GPIOTE_NS ================ */ 961 /* =========================================================================================================================== */ 962 963 964 /** 965 * @brief GPIO Tasks and Events (GPIOTE_NS) 966 */ 967 968 typedef struct { /*!< (@ 0x4100A000) GPIOTE_NS Structure */ 969 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 970 specified in CONFIG[n].PSEL. Action on pin 971 is configured in CONFIG[n].POLARITY. */ 972 __IM uint32_t RESERVED[4]; 973 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 974 specified in CONFIG[n].PSEL. Action on pin 975 is to set it high. */ 976 __IM uint32_t RESERVED1[4]; 977 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 978 specified in CONFIG[n].PSEL. Action on pin 979 is to set it low. */ 980 __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 981 for task OUT[n] */ 982 __IM uint32_t RESERVED2[4]; 983 __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration 984 for task SET[n] */ 985 __IM uint32_t RESERVED3[4]; 986 __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration 987 for task CLR[n] */ 988 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 989 pin specified in CONFIG[n].PSEL */ 990 __IM uint32_t RESERVED4[23]; 991 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 992 with SENSE mechanism enabled */ 993 __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 994 for event IN[n] */ 995 __IM uint32_t RESERVED5[23]; 996 __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */ 997 __IM uint32_t RESERVED6[65]; 998 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 999 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1000 __IM uint32_t RESERVED7[126]; 1001 __IOM uint32_t LATENCY; /*!< (@ 0x00000504) Latency selection for Event mode (MODE=Event) 1002 with rising or falling edge detection on 1003 the pin. */ 1004 __IM uint32_t RESERVED8[2]; 1005 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1006 SET[n], and CLR[n] tasks and IN[n] event */ 1007 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1008 1009 1010 1011 /* =========================================================================================================================== */ 1012 /* ================ WDT_NS ================ */ 1013 /* =========================================================================================================================== */ 1014 1015 1016 /** 1017 * @brief Watchdog Timer (WDT_NS) 1018 */ 1019 1020 typedef struct { /*!< (@ 0x4100B000) WDT_NS Structure */ 1021 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start WDT */ 1022 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop WDT */ 1023 __IM uint32_t RESERVED[30]; 1024 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1025 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1026 __IM uint32_t RESERVED1[30]; 1027 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1028 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Watchdog stopped */ 1029 __IM uint32_t RESERVED2[30]; 1030 __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ 1031 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1032 __IM uint32_t RESERVED3[95]; 1033 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1034 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1035 __IM uint32_t RESERVED4[6]; 1036 __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ 1037 __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ 1038 __IM uint32_t RESERVED5[53]; 1039 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1040 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1041 __IM uint32_t RESERVED6[63]; 1042 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1043 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1044 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1045 __IM uint32_t RESERVED7[4]; 1046 __OM uint32_t TSEN; /*!< (@ 0x00000520) Task stop enable */ 1047 __IM uint32_t RESERVED8[55]; 1048 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1049 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1050 1051 1052 1053 /* =========================================================================================================================== */ 1054 /* ================ TIMER0_NS ================ */ 1055 /* =========================================================================================================================== */ 1056 1057 1058 /** 1059 * @brief Timer/Counter 0 (TIMER0_NS) 1060 */ 1061 1062 typedef struct { /*!< (@ 0x4100C000) TIMER0_NS Structure */ 1063 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1064 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1065 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1066 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1067 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1068 __IM uint32_t RESERVED[11]; 1069 __OM uint32_t TASKS_CAPTURE[8]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1070 CC[n] register */ 1071 __IM uint32_t RESERVED1[8]; 1072 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1073 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1074 __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 1075 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 1076 __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 1077 for task SHUTDOWN */ 1078 __IM uint32_t RESERVED2[11]; 1079 __IOM uint32_t SUBSCRIBE_CAPTURE[8]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 1080 for task CAPTURE[n] */ 1081 __IM uint32_t RESERVED3[24]; 1082 __IOM uint32_t EVENTS_COMPARE[8]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1083 match */ 1084 __IM uint32_t RESERVED4[24]; 1085 __IOM uint32_t PUBLISH_COMPARE[8]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1086 for event COMPARE[n] */ 1087 __IM uint32_t RESERVED5[8]; 1088 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1089 __IM uint32_t RESERVED6[63]; 1090 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1091 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1092 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1093 __IM uint32_t RESERVED7[126]; 1094 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1095 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1096 __IM uint32_t RESERVED8; 1097 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1098 __IM uint32_t RESERVED9[11]; 1099 __IOM uint32_t CC[8]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1100 n */ 1101 __IM uint32_t RESERVED10[8]; 1102 __IOM uint32_t ONESHOTEN[8]; /*!< (@ 0x00000580) Description collection: Enable one-shot operation 1103 for Capture/Compare channel n */ 1104 } NRF_TIMER_Type; /*!< Size = 1440 (0x5a0) */ 1105 1106 1107 1108 /* =========================================================================================================================== */ 1109 /* ================ ECB_NS ================ */ 1110 /* =========================================================================================================================== */ 1111 1112 1113 /** 1114 * @brief AES ECB Mode Encryption (ECB_NS) 1115 */ 1116 1117 typedef struct { /*!< (@ 0x4100D000) ECB_NS Structure */ 1118 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1119 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1120 __IM uint32_t RESERVED[30]; 1121 __IOM uint32_t SUBSCRIBE_STARTECB; /*!< (@ 0x00000080) Subscribe configuration for task STARTECB */ 1122 __IOM uint32_t SUBSCRIBE_STOPECB; /*!< (@ 0x00000084) Subscribe configuration for task STOPECB */ 1123 __IM uint32_t RESERVED1[30]; 1124 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1125 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1126 task or due to an error */ 1127 __IM uint32_t RESERVED2[30]; 1128 __IOM uint32_t PUBLISH_ENDECB; /*!< (@ 0x00000180) Publish configuration for event ENDECB */ 1129 __IOM uint32_t PUBLISH_ERRORECB; /*!< (@ 0x00000184) Publish configuration for event ERRORECB */ 1130 __IM uint32_t RESERVED3[95]; 1131 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1132 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1133 __IM uint32_t RESERVED4[126]; 1134 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1135 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1136 1137 1138 1139 /* =========================================================================================================================== */ 1140 /* ================ AAR_NS ================ */ 1141 /* =========================================================================================================================== */ 1142 1143 1144 /** 1145 * @brief Accelerated Address Resolver (AAR_NS) 1146 */ 1147 1148 typedef struct { /*!< (@ 0x4100E000) AAR_NS Structure */ 1149 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1150 in the IRK data structure */ 1151 __IM uint32_t RESERVED; 1152 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1153 __IM uint32_t RESERVED1[29]; 1154 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1155 __IM uint32_t RESERVED2; 1156 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 1157 __IM uint32_t RESERVED3[29]; 1158 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1159 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1160 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1161 __IM uint32_t RESERVED4[29]; 1162 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000180) Publish configuration for event END */ 1163 __IOM uint32_t PUBLISH_RESOLVED; /*!< (@ 0x00000184) Publish configuration for event RESOLVED */ 1164 __IOM uint32_t PUBLISH_NOTRESOLVED; /*!< (@ 0x00000188) Publish configuration for event NOTRESOLVED */ 1165 __IM uint32_t RESERVED5[94]; 1166 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1167 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1168 __IM uint32_t RESERVED6[61]; 1169 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1170 __IM uint32_t RESERVED7[63]; 1171 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1172 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1173 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1174 __IM uint32_t RESERVED8; 1175 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1176 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1177 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1178 1179 1180 1181 /* =========================================================================================================================== */ 1182 /* ================ CCM_NS ================ */ 1183 /* =========================================================================================================================== */ 1184 1185 1186 /** 1187 * @brief AES CCM mode encryption (CCM_NS) 1188 */ 1189 1190 typedef struct { /*!< (@ 0x4100E000) CCM_NS Structure */ 1191 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation 1192 will stop by itself when completed. */ 1193 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1194 stop by itself when completed. */ 1195 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1196 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 1197 the contents of the RATEOVERRIDE register 1198 for any ongoing encryption/decryption */ 1199 __IM uint32_t RESERVED[28]; 1200 __IOM uint32_t SUBSCRIBE_KSGEN; /*!< (@ 0x00000080) Subscribe configuration for task KSGEN */ 1201 __IOM uint32_t SUBSCRIBE_CRYPT; /*!< (@ 0x00000084) Subscribe configuration for task CRYPT */ 1202 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 1203 __IOM uint32_t SUBSCRIBE_RATEOVERRIDE; /*!< (@ 0x0000008C) Subscribe configuration for task RATEOVERRIDE */ 1204 __IM uint32_t RESERVED1[28]; 1205 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ 1206 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1207 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 1208 __IM uint32_t RESERVED2[29]; 1209 __IOM uint32_t PUBLISH_ENDKSGEN; /*!< (@ 0x00000180) Publish configuration for event ENDKSGEN */ 1210 __IOM uint32_t PUBLISH_ENDCRYPT; /*!< (@ 0x00000184) Publish configuration for event ENDCRYPT */ 1211 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000188) Deprecated register - Publish configuration for 1212 event ERROR */ 1213 __IM uint32_t RESERVED3[29]; 1214 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1215 __IM uint32_t RESERVED4[64]; 1216 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1217 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1218 __IM uint32_t RESERVED5[61]; 1219 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1220 __IM uint32_t RESERVED6[63]; 1221 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1222 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1223 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key 1224 and the NONCE vector */ 1225 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1226 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1227 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1228 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH 1229 = Extended */ 1230 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 1231 __IOM uint32_t HEADERMASK; /*!< (@ 0x00000520) Header (S0) mask. */ 1232 } NRF_CCM_Type; /*!< Size = 1316 (0x524) */ 1233 1234 1235 1236 /* =========================================================================================================================== */ 1237 /* ================ DPPIC_NS ================ */ 1238 /* =========================================================================================================================== */ 1239 1240 1241 /** 1242 * @brief Distributed programmable peripheral interconnect controller (DPPIC_NS) 1243 */ 1244 1245 typedef struct { /*!< (@ 0x4100F000) DPPIC_NS Structure */ 1246 __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1247 __IM uint32_t RESERVED[20]; 1248 __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 1249 __IM uint32_t RESERVED1[276]; 1250 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1251 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1252 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1253 __IM uint32_t RESERVED2[189]; 1254 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 1255 Writes to this register are ignored if either 1256 SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS 1257 is enabled */ 1258 } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 1259 1260 1261 1262 /* =========================================================================================================================== */ 1263 /* ================ TEMP_NS ================ */ 1264 /* =========================================================================================================================== */ 1265 1266 1267 /** 1268 * @brief Temperature Sensor (TEMP_NS) 1269 */ 1270 1271 typedef struct { /*!< (@ 0x41010000) TEMP_NS Structure */ 1272 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1273 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1274 __IM uint32_t RESERVED[30]; 1275 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1276 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1277 __IM uint32_t RESERVED1[30]; 1278 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1279 __IM uint32_t RESERVED2[31]; 1280 __IOM uint32_t PUBLISH_DATARDY; /*!< (@ 0x00000180) Publish configuration for event DATARDY */ 1281 __IM uint32_t RESERVED3[96]; 1282 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1283 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1284 __IM uint32_t RESERVED4[127]; 1285 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1286 __IM uint32_t RESERVED5[5]; 1287 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ 1288 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ 1289 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ 1290 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ 1291 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ 1292 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ 1293 __IM uint32_t RESERVED6[2]; 1294 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ 1295 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ 1296 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ 1297 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ 1298 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ 1299 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ 1300 __IM uint32_t RESERVED7[2]; 1301 __IOM uint32_t T0; /*!< (@ 0x00000560) Endpoint of first piecewise linear function */ 1302 __IOM uint32_t T1; /*!< (@ 0x00000564) Endpoint of second piecewise linear function */ 1303 __IOM uint32_t T2; /*!< (@ 0x00000568) Endpoint of third piecewise linear function */ 1304 __IOM uint32_t T3; /*!< (@ 0x0000056C) Endpoint of fourth piecewise linear function */ 1305 __IOM uint32_t T4; /*!< (@ 0x00000570) Endpoint of fifth piecewise linear function */ 1306 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1307 1308 1309 1310 /* =========================================================================================================================== */ 1311 /* ================ RTC0_NS ================ */ 1312 /* =========================================================================================================================== */ 1313 1314 1315 /** 1316 * @brief Real-time counter 0 (RTC0_NS) 1317 */ 1318 1319 typedef struct { /*!< (@ 0x41011000) RTC0_NS Structure */ 1320 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 1321 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 1322 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 1323 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 1324 __IM uint32_t RESERVED[12]; 1325 __OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Description collection: Capture RTC counter to 1326 CC[n] register */ 1327 __IM uint32_t RESERVED1[12]; 1328 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1329 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1330 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 1331 __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 1332 __IM uint32_t RESERVED2[12]; 1333 __IOM uint32_t SUBSCRIBE_CAPTURE[4]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 1334 for task CAPTURE[n] */ 1335 __IM uint32_t RESERVED3[12]; 1336 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 1337 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 1338 __IM uint32_t RESERVED4[14]; 1339 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1340 match */ 1341 __IM uint32_t RESERVED5[12]; 1342 __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 1343 __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 1344 __IM uint32_t RESERVED6[14]; 1345 __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1346 for event COMPARE[n] */ 1347 __IM uint32_t RESERVED7[12]; 1348 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1349 __IM uint32_t RESERVED8[64]; 1350 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1351 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1352 __IM uint32_t RESERVED9[13]; 1353 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1354 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1355 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1356 __IM uint32_t RESERVED10[110]; 1357 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 1358 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768 1359 / (PRESCALER + 1)). Must be written when 1360 RTC is stopped. */ 1361 __IM uint32_t RESERVED11[13]; 1362 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1363 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1364 1365 1366 1367 /* =========================================================================================================================== */ 1368 /* ================ IPC_NS ================ */ 1369 /* =========================================================================================================================== */ 1370 1371 1372 /** 1373 * @brief Interprocessor communication (IPC_NS) 1374 */ 1375 1376 typedef struct { /*!< (@ 0x41012000) IPC_NS Structure */ 1377 __OM uint32_t TASKS_SEND[16]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC 1378 channel enabled in SEND_CNF[n] */ 1379 __IM uint32_t RESERVED[16]; 1380 __IOM uint32_t SUBSCRIBE_SEND[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1381 for task SEND[n] */ 1382 __IM uint32_t RESERVED1[16]; 1383 __IOM uint32_t EVENTS_RECEIVE[16]; /*!< (@ 0x00000100) Description collection: Event received on one 1384 or more of the enabled IPC channels in RECEIVE_CNF[n] */ 1385 __IM uint32_t RESERVED2[16]; 1386 __IOM uint32_t PUBLISH_RECEIVE[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 1387 for event RECEIVE[n] */ 1388 __IM uint32_t RESERVED3[80]; 1389 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1390 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1391 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1392 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1393 __IM uint32_t RESERVED4[128]; 1394 __IOM uint32_t SEND_CNF[16]; /*!< (@ 0x00000510) Description collection: Send event configuration 1395 for TASKS_SEND[n] */ 1396 __IM uint32_t RESERVED5[16]; 1397 __IOM uint32_t RECEIVE_CNF[16]; /*!< (@ 0x00000590) Description collection: Receive event configuration 1398 for EVENTS_RECEIVE[n] */ 1399 __IM uint32_t RESERVED6[16]; 1400 __IOM uint32_t GPMEM[2]; /*!< (@ 0x00000610) Description collection: General purpose memory */ 1401 } NRF_IPC_Type; /*!< Size = 1560 (0x618) */ 1402 1403 1404 1405 /* =========================================================================================================================== */ 1406 /* ================ SPIM0_NS ================ */ 1407 /* =========================================================================================================================== */ 1408 1409 1410 /** 1411 * @brief Serial Peripheral Interface Master with EasyDMA (SPIM0_NS) 1412 */ 1413 1414 typedef struct { /*!< (@ 0x41013000) SPIM0_NS Structure */ 1415 __IM uint32_t RESERVED[4]; 1416 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1417 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1418 __IM uint32_t RESERVED1; 1419 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1420 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1421 __IM uint32_t RESERVED2[27]; 1422 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */ 1423 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1424 __IM uint32_t RESERVED3; 1425 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1426 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1427 __IM uint32_t RESERVED4[24]; 1428 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1429 __IM uint32_t RESERVED5[2]; 1430 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1431 __IM uint32_t RESERVED6; 1432 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1433 __IM uint32_t RESERVED7; 1434 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1435 __IM uint32_t RESERVED8[10]; 1436 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1437 __IM uint32_t RESERVED9[13]; 1438 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1439 __IM uint32_t RESERVED10[2]; 1440 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1441 __IM uint32_t RESERVED11; 1442 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */ 1443 __IM uint32_t RESERVED12; 1444 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1445 __IM uint32_t RESERVED13[10]; 1446 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */ 1447 __IM uint32_t RESERVED14[12]; 1448 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1449 __IM uint32_t RESERVED15[64]; 1450 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1451 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1452 __IM uint32_t RESERVED16[61]; 1453 __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields 1454 in this register are set to STALL by hardware 1455 whenever a stall occurres and can be cleared 1456 (set to NOSTALL) by the CPU. */ 1457 __IM uint32_t RESERVED17[63]; 1458 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1459 __IM uint32_t RESERVED18; 1460 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1461 __IM uint32_t RESERVED19[3]; 1462 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1463 source selected. */ 1464 __IM uint32_t RESERVED20[3]; 1465 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1466 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1467 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1468 __IM uint32_t RESERVED21[2]; 1469 __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ 1470 __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ 1471 __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ 1472 __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ 1473 __IM uint32_t RESERVED22[19]; 1474 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have 1475 been transmitted in the case when RXD.MAXCNT 1476 is greater than TXD.MAXCNT */ 1477 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1478 1479 1480 1481 /* =========================================================================================================================== */ 1482 /* ================ SPIS0_NS ================ */ 1483 /* =========================================================================================================================== */ 1484 1485 1486 /** 1487 * @brief SPI Slave (SPIS0_NS) 1488 */ 1489 1490 typedef struct { /*!< (@ 0x41013000) SPIS0_NS Structure */ 1491 __IM uint32_t RESERVED[9]; 1492 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1493 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1494 to acquire it */ 1495 __IM uint32_t RESERVED1[30]; 1496 __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */ 1497 __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */ 1498 __IM uint32_t RESERVED2[22]; 1499 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1500 __IM uint32_t RESERVED3[2]; 1501 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1502 __IM uint32_t RESERVED4[5]; 1503 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1504 __IM uint32_t RESERVED5[22]; 1505 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1506 __IM uint32_t RESERVED6[2]; 1507 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1508 __IM uint32_t RESERVED7[5]; 1509 __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */ 1510 __IM uint32_t RESERVED8[21]; 1511 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1512 __IM uint32_t RESERVED9[64]; 1513 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1514 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1515 __IM uint32_t RESERVED10[61]; 1516 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1517 __IM uint32_t RESERVED11[15]; 1518 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1519 __IM uint32_t RESERVED12[47]; 1520 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1521 __IM uint32_t RESERVED13; 1522 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1523 __IM uint32_t RESERVED14[7]; 1524 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1525 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1526 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1527 __IM uint32_t RESERVED15; 1528 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1529 of an ignored transaction. */ 1530 __IM uint32_t RESERVED16[24]; 1531 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1532 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1533 1534 1535 1536 /* =========================================================================================================================== */ 1537 /* ================ TWIM0_NS ================ */ 1538 /* =========================================================================================================================== */ 1539 1540 1541 /** 1542 * @brief I2C compatible Two-Wire Master Interface with EasyDMA (TWIM0_NS) 1543 */ 1544 1545 typedef struct { /*!< (@ 0x41013000) TWIM0_NS Structure */ 1546 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1547 __IM uint32_t RESERVED; 1548 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1549 __IM uint32_t RESERVED1[2]; 1550 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1551 TWI master is not suspended. */ 1552 __IM uint32_t RESERVED2; 1553 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1554 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1555 __IM uint32_t RESERVED3[23]; 1556 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1557 __IM uint32_t RESERVED4; 1558 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1559 __IM uint32_t RESERVED5[2]; 1560 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1561 __IM uint32_t RESERVED6; 1562 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1563 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1564 __IM uint32_t RESERVED7[24]; 1565 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1566 __IM uint32_t RESERVED8[7]; 1567 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1568 __IM uint32_t RESERVED9[8]; 1569 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1570 now suspended. */ 1571 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1572 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1573 __IM uint32_t RESERVED10[2]; 1574 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1575 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1576 byte */ 1577 __IM uint32_t RESERVED11[8]; 1578 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1579 __IM uint32_t RESERVED12[7]; 1580 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1581 __IM uint32_t RESERVED13[8]; 1582 __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */ 1583 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1584 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1585 __IM uint32_t RESERVED14[2]; 1586 __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */ 1587 __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */ 1588 __IM uint32_t RESERVED15[7]; 1589 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1590 __IM uint32_t RESERVED16[63]; 1591 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1592 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1593 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1594 __IM uint32_t RESERVED17[110]; 1595 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1596 __IM uint32_t RESERVED18[14]; 1597 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1598 __IM uint32_t RESERVED19; 1599 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1600 __IM uint32_t RESERVED20[5]; 1601 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1602 source selected. */ 1603 __IM uint32_t RESERVED21[3]; 1604 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1605 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1606 __IM uint32_t RESERVED22[13]; 1607 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1608 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1609 1610 1611 1612 /* =========================================================================================================================== */ 1613 /* ================ TWIS0_NS ================ */ 1614 /* =========================================================================================================================== */ 1615 1616 1617 /** 1618 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA (TWIS0_NS) 1619 */ 1620 1621 typedef struct { /*!< (@ 0x41013000) TWIS0_NS Structure */ 1622 __IM uint32_t RESERVED[5]; 1623 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1624 __IM uint32_t RESERVED1; 1625 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1626 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1627 __IM uint32_t RESERVED2[3]; 1628 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1629 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1630 __IM uint32_t RESERVED3[23]; 1631 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1632 __IM uint32_t RESERVED4; 1633 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1634 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1635 __IM uint32_t RESERVED5[3]; 1636 __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */ 1637 __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */ 1638 __IM uint32_t RESERVED6[19]; 1639 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1640 __IM uint32_t RESERVED7[7]; 1641 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1642 __IM uint32_t RESERVED8[9]; 1643 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1644 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1645 __IM uint32_t RESERVED9[4]; 1646 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1647 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1648 __IM uint32_t RESERVED10[6]; 1649 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1650 __IM uint32_t RESERVED11[7]; 1651 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1652 __IM uint32_t RESERVED12[9]; 1653 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1654 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1655 __IM uint32_t RESERVED13[4]; 1656 __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */ 1657 __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */ 1658 __IM uint32_t RESERVED14[5]; 1659 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1660 __IM uint32_t RESERVED15[63]; 1661 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1662 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1663 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1664 __IM uint32_t RESERVED16[113]; 1665 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1666 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1667 a match */ 1668 __IM uint32_t RESERVED17[10]; 1669 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1670 __IM uint32_t RESERVED18; 1671 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1672 __IM uint32_t RESERVED19[9]; 1673 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1674 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1675 __IM uint32_t RESERVED20[13]; 1676 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1677 __IM uint32_t RESERVED21; 1678 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1679 mechanism */ 1680 __IM uint32_t RESERVED22[10]; 1681 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1682 of an over-read of the transmit buffer. */ 1683 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1684 1685 1686 1687 /* =========================================================================================================================== */ 1688 /* ================ UARTE0_NS ================ */ 1689 /* =========================================================================================================================== */ 1690 1691 1692 /** 1693 * @brief UART with EasyDMA (UARTE0_NS) 1694 */ 1695 1696 typedef struct { /*!< (@ 0x41013000) UARTE0_NS Structure */ 1697 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1698 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1699 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1700 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1701 __IM uint32_t RESERVED[7]; 1702 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1703 __IM uint32_t RESERVED1[20]; 1704 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1705 __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ 1706 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1707 __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ 1708 __IM uint32_t RESERVED2[7]; 1709 __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ 1710 __IM uint32_t RESERVED3[20]; 1711 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1712 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1713 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1714 transferred to Data RAM) */ 1715 __IM uint32_t RESERVED4; 1716 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1717 __IM uint32_t RESERVED5[2]; 1718 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1719 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1720 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1721 __IM uint32_t RESERVED6[7]; 1722 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1723 __IM uint32_t RESERVED7; 1724 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1725 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1726 __IM uint32_t RESERVED8; 1727 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1728 __IM uint32_t RESERVED9[9]; 1729 __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ 1730 __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ 1731 __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ 1732 __IM uint32_t RESERVED10; 1733 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1734 __IM uint32_t RESERVED11[2]; 1735 __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ 1736 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1737 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1738 __IM uint32_t RESERVED12[7]; 1739 __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ 1740 __IM uint32_t RESERVED13; 1741 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1742 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1743 __IM uint32_t RESERVED14; 1744 __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ 1745 __IM uint32_t RESERVED15[9]; 1746 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1747 __IM uint32_t RESERVED16[63]; 1748 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1749 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1750 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1751 __IM uint32_t RESERVED17[93]; 1752 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1753 __IM uint32_t RESERVED18[31]; 1754 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1755 __IM uint32_t RESERVED19; 1756 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1757 __IM uint32_t RESERVED20[3]; 1758 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1759 selected. */ 1760 __IM uint32_t RESERVED21[3]; 1761 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1762 __IM uint32_t RESERVED22; 1763 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1764 __IM uint32_t RESERVED23[7]; 1765 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1766 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1767 1768 1769 1770 /* =========================================================================================================================== */ 1771 /* ================ EGU0_NS ================ */ 1772 /* =========================================================================================================================== */ 1773 1774 1775 /** 1776 * @brief Event generator unit (EGU0_NS) 1777 */ 1778 1779 typedef struct { /*!< (@ 0x41014000) EGU0_NS Structure */ 1780 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1781 the corresponding TRIGGERED[n] event */ 1782 __IM uint32_t RESERVED[16]; 1783 __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1784 for task TRIGGER[n] */ 1785 __IM uint32_t RESERVED1[16]; 1786 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1787 by triggering the corresponding TRIGGER[n] 1788 task */ 1789 __IM uint32_t RESERVED2[16]; 1790 __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 1791 for event TRIGGERED[n] */ 1792 __IM uint32_t RESERVED3[80]; 1793 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1794 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1795 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1796 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1797 1798 1799 1800 /* =========================================================================================================================== */ 1801 /* ================ SWI0_NS ================ */ 1802 /* =========================================================================================================================== */ 1803 1804 1805 /** 1806 * @brief Software interrupt 0 (SWI0_NS) 1807 */ 1808 1809 typedef struct { /*!< (@ 0x4101A000) SWI0_NS Structure */ 1810 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1811 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1812 1813 1814 1815 /* =========================================================================================================================== */ 1816 /* ================ APPMUTEX_NS ================ */ 1817 /* =========================================================================================================================== */ 1818 1819 1820 /** 1821 * @brief MUTEX 0 (APPMUTEX_NS) 1822 */ 1823 1824 typedef struct { /*!< (@ 0x40030000) APPMUTEX_NS Structure */ 1825 __IM uint32_t RESERVED[256]; 1826 __IOM uint32_t MUTEX[16]; /*!< (@ 0x00000400) Description collection: Mutex register */ 1827 } NRF_MUTEX_Type; /*!< Size = 1088 (0x440) */ 1828 1829 1830 1831 /* =========================================================================================================================== */ 1832 /* ================ ACL_NS ================ */ 1833 /* =========================================================================================================================== */ 1834 1835 1836 /** 1837 * @brief Access control lists (ACL_NS) 1838 */ 1839 1840 typedef struct { /*!< (@ 0x41080000) ACL_NS Structure */ 1841 __IM uint32_t RESERVED[512]; 1842 __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ 1843 } NRF_ACL_Type; /*!< Size = 2176 (0x880) */ 1844 1845 1846 1847 /* =========================================================================================================================== */ 1848 /* ================ NVMC_NS ================ */ 1849 /* =========================================================================================================================== */ 1850 1851 1852 /** 1853 * @brief Non-volatile memory controller (NVMC_NS) 1854 */ 1855 1856 typedef struct { /*!< (@ 0x41080000) NVMC_NS Structure */ 1857 __IM uint32_t RESERVED[256]; 1858 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1859 __IM uint32_t RESERVED1; 1860 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 1861 __IM uint32_t RESERVED2[62]; 1862 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1863 __IM uint32_t RESERVED3; 1864 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1865 __IM uint32_t RESERVED4[3]; 1866 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1867 __IM uint32_t RESERVED5[8]; 1868 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ 1869 __IM uint32_t RESERVED6; 1870 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ 1871 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ 1872 } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ 1873 1874 1875 1876 /* =========================================================================================================================== */ 1877 /* ================ VMC_NS ================ */ 1878 /* =========================================================================================================================== */ 1879 1880 1881 /** 1882 * @brief Volatile Memory controller (VMC_NS) 1883 */ 1884 1885 typedef struct { /*!< (@ 0x41081000) VMC_NS Structure */ 1886 __IM uint32_t RESERVED[384]; 1887 __IOM VMC_RAM_Type RAM[4]; /*!< (@ 0x00000600) Unspecified */ 1888 } NRF_VMC_Type; /*!< Size = 1600 (0x640) */ 1889 1890 1891 1892 /* =========================================================================================================================== */ 1893 /* ================ P0_NS ================ */ 1894 /* =========================================================================================================================== */ 1895 1896 1897 /** 1898 * @brief GPIO Port 0 (P0_NS) 1899 */ 1900 1901 typedef struct { /*!< (@ 0x418C0500) P0_NS Structure */ 1902 __IM uint32_t RESERVED; 1903 __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */ 1904 __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */ 1905 __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */ 1906 __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */ 1907 __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */ 1908 __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */ 1909 __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */ 1910 __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that 1911 have met the criteria set in the PIN_CNF[n].SENSE 1912 registers */ 1913 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior 1914 and LDETECT mode */ 1915 __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behavior 1916 and LDETECT mode */ 1917 __IM uint32_t RESERVED1[117]; 1918 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO 1919 pins */ 1920 } NRF_GPIO_Type; /*!< Size = 640 (0x280) */ 1921 1922 1923 /** @} */ /* End of group Device_Peripheral_peripherals */ 1924 1925 1926 /* =========================================================================================================================== */ 1927 /* ================ Device Specific Peripheral Address Map ================ */ 1928 /* =========================================================================================================================== */ 1929 1930 1931 /** @addtogroup Device_Peripheral_peripheralAddr 1932 * @{ 1933 */ 1934 1935 #define NRF_FICR_NS_BASE 0x01FF0000UL 1936 #define NRF_UICR_NS_BASE 0x01FF8000UL 1937 #define NRF_CTI_NS_BASE 0xE0042000UL 1938 #define NRF_DCNF_NS_BASE 0x41000000UL 1939 #define NRF_VREQCTRL_NS_BASE 0x41004000UL 1940 #define NRF_CLOCK_NS_BASE 0x41005000UL 1941 #define NRF_POWER_NS_BASE 0x41005000UL 1942 #define NRF_RESET_NS_BASE 0x41005000UL 1943 #define NRF_CTRLAP_NS_BASE 0x41006000UL 1944 #define NRF_RADIO_NS_BASE 0x41008000UL 1945 #define NRF_RNG_NS_BASE 0x41009000UL 1946 #define NRF_GPIOTE_NS_BASE 0x4100A000UL 1947 #define NRF_WDT_NS_BASE 0x4100B000UL 1948 #define NRF_TIMER0_NS_BASE 0x4100C000UL 1949 #define NRF_ECB_NS_BASE 0x4100D000UL 1950 #define NRF_AAR_NS_BASE 0x4100E000UL 1951 #define NRF_CCM_NS_BASE 0x4100E000UL 1952 #define NRF_DPPIC_NS_BASE 0x4100F000UL 1953 #define NRF_TEMP_NS_BASE 0x41010000UL 1954 #define NRF_RTC0_NS_BASE 0x41011000UL 1955 #define NRF_IPC_NS_BASE 0x41012000UL 1956 #define NRF_SPIM0_NS_BASE 0x41013000UL 1957 #define NRF_SPIS0_NS_BASE 0x41013000UL 1958 #define NRF_TWIM0_NS_BASE 0x41013000UL 1959 #define NRF_TWIS0_NS_BASE 0x41013000UL 1960 #define NRF_UARTE0_NS_BASE 0x41013000UL 1961 #define NRF_EGU0_NS_BASE 0x41014000UL 1962 #define NRF_RTC1_NS_BASE 0x41016000UL 1963 #define NRF_TIMER1_NS_BASE 0x41018000UL 1964 #define NRF_TIMER2_NS_BASE 0x41019000UL 1965 #define NRF_SWI0_NS_BASE 0x4101A000UL 1966 #define NRF_SWI1_NS_BASE 0x4101B000UL 1967 #define NRF_SWI2_NS_BASE 0x4101C000UL 1968 #define NRF_SWI3_NS_BASE 0x4101D000UL 1969 #define NRF_APPMUTEX_NS_BASE 0x40030000UL 1970 #define NRF_APPMUTEX_S_BASE 0x50030000UL 1971 #define NRF_ACL_NS_BASE 0x41080000UL 1972 #define NRF_NVMC_NS_BASE 0x41080000UL 1973 #define NRF_VMC_NS_BASE 0x41081000UL 1974 #define NRF_P0_NS_BASE 0x418C0500UL 1975 #define NRF_P1_NS_BASE 0x418C0800UL 1976 1977 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 1978 1979 1980 /* =========================================================================================================================== */ 1981 /* ================ Peripheral declaration ================ */ 1982 /* =========================================================================================================================== */ 1983 1984 1985 /** @addtogroup Device_Peripheral_declaration 1986 * @{ 1987 */ 1988 1989 #define NRF_FICR_NS ((NRF_FICR_Type*) NRF_FICR_NS_BASE) 1990 #define NRF_UICR_NS ((NRF_UICR_Type*) NRF_UICR_NS_BASE) 1991 #define NRF_CTI_NS ((NRF_CTI_Type*) NRF_CTI_NS_BASE) 1992 #define NRF_DCNF_NS ((NRF_DCNF_Type*) NRF_DCNF_NS_BASE) 1993 #define NRF_VREQCTRL_NS ((NRF_VREQCTRL_Type*) NRF_VREQCTRL_NS_BASE) 1994 #define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) 1995 #define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) 1996 #define NRF_RESET_NS ((NRF_RESET_Type*) NRF_RESET_NS_BASE) 1997 #define NRF_CTRLAP_NS ((NRF_CTRLAPPERI_Type*) NRF_CTRLAP_NS_BASE) 1998 #define NRF_RADIO_NS ((NRF_RADIO_Type*) NRF_RADIO_NS_BASE) 1999 #define NRF_RNG_NS ((NRF_RNG_Type*) NRF_RNG_NS_BASE) 2000 #define NRF_GPIOTE_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE_NS_BASE) 2001 #define NRF_WDT_NS ((NRF_WDT_Type*) NRF_WDT_NS_BASE) 2002 #define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE) 2003 #define NRF_ECB_NS ((NRF_ECB_Type*) NRF_ECB_NS_BASE) 2004 #define NRF_AAR_NS ((NRF_AAR_Type*) NRF_AAR_NS_BASE) 2005 #define NRF_CCM_NS ((NRF_CCM_Type*) NRF_CCM_NS_BASE) 2006 #define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE) 2007 #define NRF_TEMP_NS ((NRF_TEMP_Type*) NRF_TEMP_NS_BASE) 2008 #define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE) 2009 #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) 2010 #define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE) 2011 #define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE) 2012 #define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE) 2013 #define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE) 2014 #define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE) 2015 #define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE) 2016 #define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE) 2017 #define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE) 2018 #define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE) 2019 #define NRF_SWI0_NS ((NRF_SWI_Type*) NRF_SWI0_NS_BASE) 2020 #define NRF_SWI1_NS ((NRF_SWI_Type*) NRF_SWI1_NS_BASE) 2021 #define NRF_SWI2_NS ((NRF_SWI_Type*) NRF_SWI2_NS_BASE) 2022 #define NRF_SWI3_NS ((NRF_SWI_Type*) NRF_SWI3_NS_BASE) 2023 #define NRF_APPMUTEX_NS ((NRF_MUTEX_Type*) NRF_APPMUTEX_NS_BASE) 2024 #define NRF_APPMUTEX_S ((NRF_MUTEX_Type*) NRF_APPMUTEX_S_BASE) 2025 #define NRF_ACL_NS ((NRF_ACL_Type*) NRF_ACL_NS_BASE) 2026 #define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE) 2027 #define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE) 2028 #define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) 2029 #define NRF_P1_NS ((NRF_GPIO_Type*) NRF_P1_NS_BASE) 2030 2031 /** @} */ /* End of group Device_Peripheral_declaration */ 2032 2033 2034 #ifdef __cplusplus 2035 } 2036 #endif 2037 2038 #endif /* NRF5340_NETWORK_H */ 2039 2040 2041 /** @} */ /* End of group nrf5340_network */ 2042 2043 /** @} */ /* End of group Nordic Semiconductor */ 2044
