1 /*
2 * Copyright (c) 2015 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_TWIM_H__
35 #define NRF_TWIM_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if defined(NRF54H20_XXAA)
44 #define NRF_TWIM_CLOCKPIN_SDA_NEEDED 1
45 #endif
46
47 #if defined(HALTIUM_XXAA)
48 #define NRF_TWIM_CLOCKPIN_SCL_NEEDED 1
49 #endif
50
51 /**
52 * @defgroup nrf_twim_hal TWIM HAL
53 * @{
54 * @ingroup nrf_twim
55 * @brief Hardware access layer for managing the TWIM peripheral.
56 */
57
58 /**
59 * @brief Macro getting pointer to the structure of registers of the TWIM peripheral.
60 *
61 * @param[in] idx TWIM instance index.
62 *
63 * @return Pointer to the structure of registers of the TWIM peripheral.
64 */
65 #define NRF_TWIM_INST_GET(idx) NRFX_CONCAT(NRF_, TWIM, idx)
66
67 #if defined(TWIM_FREQUENCY_FREQUENCY_K1000) || defined(__NRFX_DOXYGEN__)
68 /** @brief Symbol indicating whether 1000 kHz clock frequency is available. */
69 #define NRF_TWIM_HAS_1000_KHZ_FREQ 1
70 #else
71 #define NRF_TWIM_HAS_1000_KHZ_FREQ 0
72 #endif
73
74 #if defined(TWIM_TXD_LIST_LIST_ArrayList) || defined(TWIM_DMA_TX_LIST_TYPE_ArrayList) || \
75 defined(__NRFX_DOXYGEN__)
76 /** @brief Symbol indicating whether EasyDMA array list feature is present. */
77 #define NRF_TWIM_HAS_ARRAY_LIST 1
78 #else
79 #define NRF_TWIM_HAS_ARRAY_LIST 0
80 #endif
81
82 #if defined(TWIM_DMA_RX_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
83 /** @brief Symbol indicating whether dedicated DMA register is present. */
84 #define NRF_TWIM_HAS_DMA_REG 1
85 #else
86 #define NRF_TWIM_HAS_DMA_REG 0
87 #endif
88
89 #if defined(TWIM_DMA_RX_CURRENTAMOUNT_AMOUNT_Msk) || defined(__NRFX_DOXYGEN__)
90 /** @brief Symbol indicating whether DMA CURRENTAMOUNT registers are present. */
91 #define NRF_TWIM_HAS_DMA_CURRENTAMOUNT_REG 1
92 #else
93 #define NRF_TWIM_HAS_DMA_CURRENTAMOUNT_REG 0
94 #endif
95
96 #if (defined(TWIM_TASKS_DMA_RX_START_START_Msk) && defined(TWIM_EVENTS_DMA_RX_END_END_Msk)) || \
97 defined(__NRFX_DOXYGEN__)
98 /** @brief Symbol indicating whether TWIM DMA tasks and events are present. */
99 #define NRF_TWIM_HAS_DMA_TASKS_EVENTS 1
100 #else
101 #define NRF_TWIM_HAS_DMA_TASKS_EVENTS 0
102 #endif
103
104 #if defined(TWIM_SHORTS_LASTTX_DMA_RX_START_Msk) || defined(__NRFX_DOXYGEN__)
105 /** @brief Symbol indicating whether TWIM DMA shortcuts are present. */
106 #define NRF_TWIM_HAS_DMA_SHORTS 1
107 #else
108 #define NRF_TWIM_HAS_DMA_SHORTS 0
109 #endif
110
111 #if (defined(TWIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Msk) || \
112 defined(TWIM_EVENTS_DMA_RX_BUSERROR_BUSERROR_Msk)) || defined(__NRFX_DOXYGEN__)
113 /** @brief Symbol indicating whether TWIM BUSERROR events are present. */
114 #define NRF_TWIM_HAS_BUS_ERROR_EVENTS 1
115 #else
116 #define NRF_TWIM_HAS_BUS_ERROR_EVENTS 0
117 #endif
118
119 #if NRF_TWIM_HAS_DMA_REG
120 /** @brief Max number of RX patterns. */
121 #define NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT TWIM_DMA_RX_MATCH_CANDIDATE_MaxCount
122 #endif
123
124 /** @brief TWIM tasks. */
125 typedef enum
126 {
127 #if NRF_TWIM_HAS_DMA_TASKS_EVENTS
128 NRF_TWIM_TASK_STARTRX = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.START), ///< Start TWI receive operation using easyDMA to load the values.
129 NRF_TWIM_TASK_STOPRX = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.STOP), ///< Stop TWI receive operation using easyDMA. This does not trigger an END event.
130 NRF_TWIM_TASK_STARTTX = offsetof(NRF_TWIM_Type, TASKS_DMA.TX.START), ///< Start TWI transmit operation using easyDMA to load the values.
131 NRF_TWIM_TASK_STOPTX = offsetof(NRF_TWIM_Type, TASKS_DMA.TX.STOP), ///< Stop TWI transmit operation using easyDMA to load the values.
132 NRF_TWIM_TASK_ENABLERXMATCH0 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.ENABLEMATCH[0]), ///< Enable TWI pattern matching functionality for pattern 0.
133 NRF_TWIM_TASK_ENABLERXMATCH1 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.ENABLEMATCH[1]), ///< Enable TWI pattern matching functionality for pattern 1.
134 NRF_TWIM_TASK_ENABLERXMATCH2 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.ENABLEMATCH[2]), ///< Enable TWI pattern matching functionality for pattern 2.
135 NRF_TWIM_TASK_ENABLERXMATCH3 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.ENABLEMATCH[3]), ///< Enable TWI pattern matching functionality for pattern 3.
136 NRF_TWIM_TASK_DISABLERXMATCH0 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.DISABLEMATCH[0]), ///< Disable TWI pattern matching functionality for pattern 0.
137 NRF_TWIM_TASK_DISABLERXMATCH1 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.DISABLEMATCH[1]), ///< Disable TWI pattern matching functionality for pattern 1.
138 NRF_TWIM_TASK_DISABLERXMATCH2 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.DISABLEMATCH[2]), ///< Disable TWI pattern matching functionality for pattern 2.
139 NRF_TWIM_TASK_DISABLERXMATCH3 = offsetof(NRF_TWIM_Type, TASKS_DMA.RX.DISABLEMATCH[3]), ///< Disable TWI pattern matching functionality for pattern 3.
140 #else
141 NRF_TWIM_TASK_STARTRX = offsetof(NRF_TWIM_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
142 NRF_TWIM_TASK_STARTTX = offsetof(NRF_TWIM_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
143 #endif
144 NRF_TWIM_TASK_STOP = offsetof(NRF_TWIM_Type, TASKS_STOP), ///< Stop TWI transaction.
145 NRF_TWIM_TASK_SUSPEND = offsetof(NRF_TWIM_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
146 NRF_TWIM_TASK_RESUME = offsetof(NRF_TWIM_Type, TASKS_RESUME) ///< Resume TWI transaction.
147 } nrf_twim_task_t;
148
149 /** @brief TWIM events. */
150 typedef enum
151 {
152 NRF_TWIM_EVENT_STOPPED = offsetof(NRF_TWIM_Type, EVENTS_STOPPED), ///< TWI stopped.
153 NRF_TWIM_EVENT_ERROR = offsetof(NRF_TWIM_Type, EVENTS_ERROR), ///< TWI error.
154 NRF_TWIM_EVENT_SUSPENDED = offsetof(NRF_TWIM_Type, EVENTS_SUSPENDED), ///< TWI suspended.
155 #if NRF_TWIM_HAS_DMA_TASKS_EVENTS
156 NRF_TWIM_EVENT_ENDRX = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.END), ///< Receive sequence finished.
157 NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.READY), ///< Receive sequence started.
158 NRF_TWIM_EVENT_RXMATCH0 = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.MATCH[0]), ///< Pattern match for pattern 0 detected.
159 NRF_TWIM_EVENT_RXMATCH1 = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.MATCH[1]), ///< Pattern match for pattern 1 detected.
160 NRF_TWIM_EVENT_RXMATCH2 = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.MATCH[2]), ///< Pattern match for pattern 2 detected.
161 NRF_TWIM_EVENT_RXMATCH3 = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.MATCH[3]), ///< Pattern match for pattern 3 detected.
162 NRF_TWIM_EVENT_ENDTX = offsetof(NRF_TWIM_Type, EVENTS_DMA.TX.END), ///< Transmit sequence finished.
163 NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_DMA.TX.READY), ///< Transmit sequence started.
164 #if NRF_TWIM_HAS_BUS_ERROR_EVENTS
165 NRF_TWIM_EVENT_RXBUSERROR = offsetof(NRF_TWIM_Type, EVENTS_DMA.RX.BUSERROR), ///< Memory bus error occurred during the RX transfer.
166 NRF_TWIM_EVENT_TXBUSERROR = offsetof(NRF_TWIM_Type, EVENTS_DMA.TX.BUSERROR), ///< Memory bus error occurred during the TX transfer.
167 #endif
168 #else
169 NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_RXSTARTED), ///< Receive sequence started.
170 NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started.
171 #if NRF_TWIM_HAS_BUS_ERROR_EVENTS
172 NRF_TWIM_EVENT_RXBUSERROR = offsetof(NRF_TWIM_Type, EVENTS_RXBUSERROR), ///< Memory bus error occurred during the RX transfer.
173 NRF_TWIM_EVENT_TXBUSERROR = offsetof(NRF_TWIM_Type, EVENTS_TXBUSERROR), ///< Memory bus error occurred during the TX transfer.
174 #endif
175 #endif // NRF_TWIM_HAS_DMA_TASKS_EVENTS
176 NRF_TWIM_EVENT_LASTRX = offsetof(NRF_TWIM_Type, EVENTS_LASTRX), ///< Byte boundary, starting to receive the last byte.
177 NRF_TWIM_EVENT_LASTTX = offsetof(NRF_TWIM_Type, EVENTS_LASTTX) ///< Byte boundary, starting to transmit the last byte.
178 } nrf_twim_event_t;
179
180 /** @brief TWIM shortcuts. */
181 typedef enum
182 {
183 NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK = TWIM_SHORTS_LASTTX_SUSPEND_Msk, ///< Shortcut between LASTTX event and SUSPEND task.
184 NRF_TWIM_SHORT_LASTTX_STOP_MASK = TWIM_SHORTS_LASTTX_STOP_Msk, ///< Shortcut between LASTTX event and STOP task.
185 NRF_TWIM_SHORT_LASTRX_STOP_MASK = TWIM_SHORTS_LASTRX_STOP_Msk, ///< Shortcut between LASTRX event and STOP task.
186 #if NRF_TWIM_HAS_DMA_SHORTS
187 NRF_TWIM_SHORT_LASTTX_STARTRX_MASK = TWIM_SHORTS_LASTTX_DMA_RX_START_Msk, ///< Shortcut between LASTTX event and STARTRX task.
188 NRF_TWIM_SHORT_LASTRX_STARTTX_MASK = TWIM_SHORTS_LASTRX_DMA_TX_START_Msk, ///< Shortcut between LASTRX event and STARTTX task.
189 #else
190 NRF_TWIM_SHORT_LASTTX_STARTRX_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk, ///< Shortcut between LASTTX event and STARTRX task.
191 NRF_TWIM_SHORT_LASTRX_STARTTX_MASK = TWIM_SHORTS_LASTRX_STARTTX_Msk, ///< Shortcut between LASTRX event and STARTTX task.
192 #endif
193 #if NRF_TWIM_HAS_DMA_TASKS_EVENTS
194 NRF_TWIM_SHORT_RXMATCH0_ENABLERXMATCH1_MASK = TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.ENABLEMATCH1 task.
195 NRF_TWIM_SHORT_RXMATCH1_ENABLERXMATCH2_MASK = TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.ENABLEMATCH2 task.
196 NRF_TWIM_SHORT_RXMATCH2_ENABLERXMATCH3_MASK = TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.ENABLEMATCH0 task.
197 NRF_TWIM_SHORT_RXMATCH3_ENABLERXMATCH0_MASK = TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.ENABLEMATCH1 task.
198 NRF_TWIM_SHORT_RXMATCH0_DISABLERXMATCH0_MASK = TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.DISABLEMATCH0 task.
199 NRF_TWIM_SHORT_RXMATCH1_DISABLERXMATCH1_MASK = TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.DISABLEMATCH1 task.
200 NRF_TWIM_SHORT_RXMATCH2_DISABLERXMATCH2_MASK = TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.DISABLEMATCH2 task.
201 NRF_TWIM_SHORT_RXMATCH3_DISABLERXMATCH3_MASK = TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.DISABLEMATCH3 task.
202 #endif
203 NRF_TWIM_ALL_SHORTS_MASK =
204 #if NRF_TWIM_HAS_DMA_SHORTS
205 TWIM_SHORTS_LASTTX_DMA_RX_START_Msk |
206 TWIM_SHORTS_LASTRX_DMA_TX_START_Msk |
207 #else
208 TWIM_SHORTS_LASTTX_STARTRX_Msk |
209 TWIM_SHORTS_LASTRX_STARTTX_Msk |
210 #endif
211 #if NRF_TWIM_HAS_DMA_TASKS_EVENTS
212 TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk |
213 TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk |
214 TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk |
215 TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk |
216 TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk |
217 TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk |
218 TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk |
219 TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk |
220 #endif
221 TWIM_SHORTS_LASTTX_SUSPEND_Msk |
222 TWIM_SHORTS_LASTTX_STOP_Msk |
223 TWIM_SHORTS_LASTRX_STOP_Msk ///< All TWIM shortcuts.
224 } nrf_twim_short_mask_t;
225
226 /** @brief TWIM interrupts. */
227 typedef enum
228 {
229 NRF_TWIM_INT_STOPPED_MASK = TWIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
230 NRF_TWIM_INT_ERROR_MASK = TWIM_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
231 NRF_TWIM_INT_SUSPENDED_MASK = TWIM_INTENSET_SUSPENDED_Msk, ///< Interrupt on SUSPENDED event.
232 #if NRF_TWIM_HAS_DMA_TASKS_EVENTS
233 NRF_TWIM_INT_RXSTARTED_MASK = TWIM_INTENSET_DMARXREADY_Msk, ///< Interrupt on RXSTARTED event.
234 NRF_TWIM_INT_TXSTARTED_MASK = TWIM_INTENSET_DMATXREADY_Msk, ///< Interrupt on TXSTARTED event.
235 NRF_TWIM_INT_ENDRX_MASK = TWIM_INTENSET_DMARXEND_Msk, ///< Interrupt on DMA.RX.END event.
236 NRF_TWIM_INT_RXREADY_MASK = TWIM_INTENSET_DMARXREADY_Msk, ///< Interrupt on DMA.RX.READY event.
237 NRF_TWIM_INT_RXBUSERROR_MASK = TWIM_INTENSET_DMARXBUSERROR_Msk, ///< Interrupt on DMA.RX.BUSERROR event.
238 NRF_TWIM_INT_RXMATCH0_MASK = TWIM_INTENSET_DMARXMATCH0_Msk, ///< Interrupt on DMA.RX.MATCH0 event.
239 NRF_TWIM_INT_RXMATCH1_MASK = TWIM_INTENSET_DMARXMATCH1_Msk, ///< Interrupt on DMA.RX.MATCH1 event.
240 NRF_TWIM_INT_RXMATCH2_MASK = TWIM_INTENSET_DMARXMATCH2_Msk, ///< Interrupt on DMA.RX.MATCH2 event.
241 NRF_TWIM_INT_RXMATCH3_MASK = TWIM_INTENSET_DMARXMATCH3_Msk, ///< Interrupt on DMA.RX.MATCH3 event.
242 NRF_TWIM_INT_ENDTX_MASK = TWIM_INTENSET_DMATXEND_Msk, ///< Interrupt on DMA.TX.END event.
243 NRF_TWIM_INT_TXREADY_MASK = TWIM_INTENSET_DMATXREADY_Msk, ///< Interrupt on DMA.TX.READY event.
244 NRF_TWIM_INT_TXBUSERROR_MASK = TWIM_INTENSET_DMATXBUSERROR_Msk, ///< Interrupt on DMA.TX.BUSERROR event.
245 #else
246 NRF_TWIM_INT_RXSTARTED_MASK = TWIM_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
247 NRF_TWIM_INT_TXSTARTED_MASK = TWIM_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
248 #endif
249 NRF_TWIM_INT_LASTRX_MASK = TWIM_INTENSET_LASTRX_Msk, ///< Interrupt on LASTRX event.
250 NRF_TWIM_INT_LASTTX_MASK = TWIM_INTENSET_LASTTX_Msk, ///< Interrupt on LASTTX event.
251 NRF_TWIM_ALL_INTS_MASK = NRF_TWIM_INT_STOPPED_MASK |
252 NRF_TWIM_INT_ERROR_MASK |
253 NRF_TWIM_INT_SUSPENDED_MASK |
254 NRF_TWIM_INT_RXSTARTED_MASK |
255 NRF_TWIM_INT_TXSTARTED_MASK |
256 #if NRF_TWIM_HAS_DMA_TASKS_EVENTS
257 NRF_TWIM_INT_ENDRX_MASK |
258 NRF_TWIM_INT_RXREADY_MASK |
259 NRF_TWIM_INT_RXBUSERROR_MASK |
260 NRF_TWIM_INT_RXMATCH0_MASK |
261 NRF_TWIM_INT_RXMATCH1_MASK |
262 NRF_TWIM_INT_RXMATCH2_MASK |
263 NRF_TWIM_INT_RXMATCH3_MASK |
264 NRF_TWIM_INT_ENDTX_MASK |
265 NRF_TWIM_INT_TXREADY_MASK |
266 NRF_TWIM_INT_TXBUSERROR_MASK |
267 #endif
268 NRF_TWIM_INT_LASTRX_MASK |
269 NRF_TWIM_INT_LASTTX_MASK ///< All TWIM interrupts.
270 } nrf_twim_int_mask_t;
271
272 /** @brief TWIM master clock frequency. */
273 typedef enum
274 {
275 NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
276 NRF_TWIM_FREQ_250K = TWIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
277 NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400, ///< 400 kbps.
278 #if NRF_TWIM_HAS_1000_KHZ_FREQ
279 NRF_TWIM_FREQ_1000K = TWIM_FREQUENCY_FREQUENCY_K1000 ///< 1000 kbps.
280 #endif
281 } nrf_twim_frequency_t;
282
283 /** @brief TWIM error source. */
284 typedef enum
285 {
286 NRF_TWIM_ERROR_ADDRESS_NACK = TWIM_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address.
287 NRF_TWIM_ERROR_DATA_NACK = TWIM_ERRORSRC_DNACK_Msk, ///< NACK received after sending a data byte.
288 NRF_TWIM_ERROR_OVERRUN = TWIM_ERRORSRC_OVERRUN_Msk ///< Overrun error.
289 /**< A new byte was received before the previous byte was
290 * handled by peripheral. (previous data is lost). */
291 } nrf_twim_error_t;
292
293
294 /**
295 * @brief Function for activating the specified TWIM task.
296 *
297 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
298 * @param[in] task Task to be activated.
299 */
300 NRF_STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,
301 nrf_twim_task_t task);
302
303 /**
304 * @brief Function for getting the address of the specified TWIM task register.
305 *
306 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
307 * @param[in] task The specified task.
308 *
309 * @return Address of the specified task register.
310 */
311 NRF_STATIC_INLINE uint32_t nrf_twim_task_address_get(NRF_TWIM_Type const * p_reg,
312 nrf_twim_task_t task);
313
314 /**
315 * @brief Function for clearing the specified TWIM event.
316 *
317 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
318 * @param[in] event Event to clear.
319 */
320 NRF_STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
321 nrf_twim_event_t event);
322
323 /**
324 * @brief Function for retrieving the state of the TWIM event.
325 *
326 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
327 * @param[in] event Event to be checked.
328 *
329 * @retval true The event has been generated.
330 * @retval false The event has not been generated.
331 */
332 NRF_STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type const * p_reg,
333 nrf_twim_event_t event);
334
335 /**
336 * @brief Function for getting the address of the specified TWIM event register.
337 *
338 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
339 * @param[in] event The specified event.
340 *
341 * @return Address of the specified event register.
342 */
343 NRF_STATIC_INLINE uint32_t nrf_twim_event_address_get(NRF_TWIM_Type const * p_reg,
344 nrf_twim_event_t event);
345
346 /**
347 * @brief Function for enabling the specified shortcuts.
348 *
349 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
350 * @param[in] mask Shortcuts to be enabled.
351 */
352 NRF_STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,
353 uint32_t mask);
354
355 /**
356 * @brief Function for disabling the specified shortcuts.
357 *
358 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
359 * @param[in] mask Shortcuts to be disabled.
360 */
361 NRF_STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,
362 uint32_t mask);
363
364 /**
365 * @brief Function for enabling the specified interrupts.
366 *
367 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
368 * @param[in] mask Mask of interrupts to be enabled.
369 * Use @ref nrf_twim_int_mask_t values for bit masking.
370 */
371 NRF_STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg,
372 uint32_t mask);
373
374 /**
375 * @brief Function for disabling the specified interrupts.
376 *
377 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
378 * @param[in] mask Mask of interrupts to be disabled.
379 * Use @ref nrf_twim_int_mask_t values for bit masking.
380 */
381 NRF_STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg,
382 uint32_t mask);
383
384 /**
385 * @brief Function for checking if the specified interrupts are enabled.
386 *
387 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
388 * @param[in] mask Mask of interrupts to be checked.
389 * Use @ref nrf_twim_int_mask_t values for bit masking.
390 *
391 * @return Mask of enabled interrupts.
392 */
393 NRF_STATIC_INLINE uint32_t nrf_twim_int_enable_check(NRF_TWIM_Type const * p_reg, uint32_t mask);
394
395 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
396 /**
397 * @brief Function for setting the subscribe configuration for a given
398 * TWIM task.
399 *
400 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
401 * @param[in] task Task for which to set the configuration.
402 * @param[in] channel Channel through which to subscribe events.
403 */
404 NRF_STATIC_INLINE void nrf_twim_subscribe_set(NRF_TWIM_Type * p_reg,
405 nrf_twim_task_t task,
406 uint8_t channel);
407
408 /**
409 * @brief Function for clearing the subscribe configuration for a given
410 * TWIM task.
411 *
412 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
413 * @param[in] task Task for which to clear the configuration.
414 */
415 NRF_STATIC_INLINE void nrf_twim_subscribe_clear(NRF_TWIM_Type * p_reg,
416 nrf_twim_task_t task);
417
418 /**
419 * @brief Function for setting the publish configuration for a given
420 * TWIM event.
421 *
422 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
423 * @param[in] event Event for which to set the configuration.
424 * @param[in] channel Channel through which to publish the event.
425 */
426 NRF_STATIC_INLINE void nrf_twim_publish_set(NRF_TWIM_Type * p_reg,
427 nrf_twim_event_t event,
428 uint8_t channel);
429
430 /**
431 * @brief Function for clearing the publish configuration for a given
432 * TWIM event.
433 *
434 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
435 * @param[in] event Event for which to clear the configuration.
436 */
437 NRF_STATIC_INLINE void nrf_twim_publish_clear(NRF_TWIM_Type * p_reg,
438 nrf_twim_event_t event);
439 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
440
441 /**
442 * @brief Function for enabling the TWIM peripheral.
443 *
444 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
445 */
446 NRF_STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg);
447
448 /**
449 * @brief Function for disabling the TWIM peripheral.
450 *
451 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
452 */
453 NRF_STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg);
454
455 /**
456 * @brief Function for configuring TWI pins.
457 *
458 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
459 * @param[in] scl_pin SCL pin number.
460 * @param[in] sda_pin SDA pin number.
461 */
462 NRF_STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
463 uint32_t scl_pin,
464 uint32_t sda_pin);
465
466 /**
467 * @brief Function for setting the SCL pin.
468 *
469 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
470 * @param[in] pin SCL pin number.
471 */
472 NRF_STATIC_INLINE void nrf_twim_scl_pin_set(NRF_TWIM_Type * p_reg, uint32_t pin);
473
474 /**
475 * @brief Function for setting the SDA pin
476 *
477 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
478 * @param[in] pin SDA pin number.
479 */
480 NRF_STATIC_INLINE void nrf_twim_sda_pin_set(NRF_TWIM_Type * p_reg, uint32_t pin);
481
482 /**
483 * @brief Function for retrieving the SCL pin selection.
484 *
485 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
486 *
487 * @return SCL pin selection.
488 */
489 NRF_STATIC_INLINE uint32_t nrf_twim_scl_pin_get(NRF_TWIM_Type const * p_reg);
490
491 /**
492 * @brief Function for retrieving the SDA pin selection.
493 *
494 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
495 *
496 * @return SDA pin selection.
497 */
498 NRF_STATIC_INLINE uint32_t nrf_twim_sda_pin_get(NRF_TWIM_Type const * p_reg);
499
500 /**
501 * @brief Function for setting the TWI master clock frequency.
502 *
503 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
504 * @param[in] frequency TWI frequency.
505 */
506 NRF_STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
507 nrf_twim_frequency_t frequency);
508
509 /**
510 * @brief Function for checking the TWI error source.
511 *
512 * The error flags are cleared after reading.
513 *
514 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
515 *
516 * @return Mask with error source flags.
517 */
518 NRF_STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg);
519
520 /**
521 * @brief Function for setting the address to be used in TWI transfers.
522 *
523 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
524 * @param[in] address Address to be used in transfers.
525 */
526 NRF_STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
527 uint8_t address);
528
529 /**
530 * @brief Function for getting the address to be used in TWI transfers.
531 *
532 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
533 *
534 * @return Address to be used in TWI transfers.
535 */
536 NRF_STATIC_INLINE uint8_t nrf_twim_address_get(NRF_TWIM_Type const * p_reg);
537
538 /**
539 * @brief Function for setting the transmit buffer.
540 *
541 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
542 * @param[in] p_buffer Pointer to the buffer with data to send.
543 * @param[in] length Maximum number of data bytes to transmit.
544 */
545 NRF_STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
546 uint8_t const * p_buffer,
547 size_t length);
548
549 /**
550 * @brief Function for setting the receive buffer.
551 *
552 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
553 * @param[in] p_buffer Pointer to the buffer for received data.
554 * @param[in] length Maximum number of data bytes to receive.
555 */
556 NRF_STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
557 uint8_t * p_buffer,
558 size_t length);
559
560 /**
561 * @brief Function for setting the specified shortcuts.
562 *
563 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
564 * @param[in] mask Shortcuts to be set.
565 */
566 NRF_STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
567 uint32_t mask);
568
569 /**
570 * @brief Function for getting the shortcut setting.
571 *
572 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
573 *
574 * @return Current shortcut configuration.
575 */
576 NRF_STATIC_INLINE uint32_t nrf_twim_shorts_get(NRF_TWIM_Type const * p_reg);
577
578 /**
579 * @brief Function for getting the amount of transmitted bytes.
580 *
581 * @note In case of NACK error, includes the NACK'ed byte.
582 * @note Number of bytes are updated after the END event and each MATCH event.
583 *
584 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
585 *
586 * @return Amount of transmitted bytes.
587 */
588 NRF_STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type const * p_reg);
589
590 /**
591 * @brief Function for getting the amount of received bytes in the last transaction.
592 *
593 * @note In case of NACK error, includes the NACK'ed byte.
594 * @note Number of bytes are updated after the END event and each MATCH event.
595 *
596 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
597 *
598 * @return Amount of received bytes.
599 */
600 NRF_STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type const * p_reg);
601
602 #if NRF_TWIM_HAS_DMA_CURRENTAMOUNT_REG
603 /**
604 * @brief Function for getting the amount of transmitted bytes in the current transaction.
605 *
606 * @note Number of bytes is continuously updated during transmission.
607 *
608 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
609 *
610 * @return Amount of transmitted bytes.
611 */
612 NRF_STATIC_INLINE size_t nrf_twim_txd_curr_amount_get(NRF_TWIM_Type const * p_reg);
613
614 /**
615 * @brief Function for getting the amount of received bytes in the current transaction.
616 *
617 * @note Number of bytes is continuously updated during reception.
618 *
619 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
620 *
621 * @return Amount of received bytes.
622 */
623 NRF_STATIC_INLINE size_t nrf_twim_rxd_curr_amount_get(NRF_TWIM_Type const * p_reg);
624 #endif
625
626 #if NRF_TWIM_HAS_ARRAY_LIST
627 /**
628 * @brief Function for enabling the TX list feature.
629 *
630 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
631 */
632 NRF_STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg);
633
634 /**
635 * @brief Function for disabling the TX list feature.
636 *
637 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
638 */
639 NRF_STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg);
640
641 /**
642 * @brief Function for enabling the RX list feature.
643 *
644 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
645 */
646 NRF_STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg);
647
648 /**
649 * @brief Function for disabling the RX list feature.
650 *
651 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
652 */
653 NRF_STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg);
654 #endif
655
656 #if NRF_TWIM_HAS_DMA_REG
657 /**
658 * @brief Function for enabling individual pattern match filters.
659 *
660 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
661 * @param[in] index Index of pattern match filter.
662 * @param[in] enable True if pattern match filter is to be enabled, false otherwise.
663 */
664 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_enable_set(NRF_TWIM_Type * p_reg,
665 uint8_t index,
666 bool enable);
667
668 /**
669 * @brief Function for checking if the specified pattern match filter is enabled.
670 *
671 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
672 * @param[in] index Index of pattern match filter.
673 *
674 * @retval true Pattern match filter is enabled.
675 * @retval false Pattern match filter is disabled.
676 */
677 NRF_STATIC_INLINE bool nrf_twim_rx_pattern_match_enable_check(NRF_TWIM_Type const * p_reg,
678 uint8_t index);
679
680 /**
681 * @brief Function for enabling one-shot operation for the specified match filter.
682 *
683 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
684 * @param[in] index Index of pattern match filter.
685 */
686 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_one_shot_enable(NRF_TWIM_Type * p_reg,
687 uint8_t index);
688
689 /**
690 * @brief Function for disabling one-shot operation for the specified match filter.
691 *
692 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
693 * @param[in] index Index of pattern match filter.
694 */
695 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_one_shot_disable(NRF_TWIM_Type * p_reg,
696 uint8_t index);
697
698 /**
699 * @brief Function for checking if specified pattern match filter is configured as one-shot.
700 *
701 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
702 * @param[in] index Index of pattern match filter.
703 *
704 * @retval true Pattern match filter is configured as one-shot.
705 * @retval false Pattern match filter is configured as continuous.
706 */
707 NRF_STATIC_INLINE bool nrf_twim_rx_pattern_match_one_shot_check(NRF_TWIM_Type const * p_reg,
708 uint8_t index);
709
710 /**
711 * @brief Function for setting the pattern to be looked for by the specified match filter.
712 *
713 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
714 * @param[in] index Index of pattern match filter.
715 * @param[in] pattern Pattern to be looked for.
716 * Match will trigger the corresponding event, if enabled.
717 */
718 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_candidate_set(NRF_TWIM_Type * p_reg,
719 uint8_t index,
720 uint32_t pattern);
721
722 /**
723 * @brief Function for getting the pattern that the specified match filter is looking for.
724 *
725 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
726 * @param[in] index Index of pattern match filter.
727 *
728 * @return Pattern that the specified match filter is looking for.
729 */
730 NRF_STATIC_INLINE uint32_t nrf_twim_rx_pattern_match_candidate_get(NRF_TWIM_Type const * p_reg,
731 uint8_t index);
732 #endif // NRF_TWIM_HAS_DMA_REG
733
734 #if NRF_TWIM_HAS_BUS_ERROR_EVENTS
735 /**
736 * @brief Function for enabling RX transaction termination on the detection of a BUSERROR event.
737 *
738 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
739 * @param[in] enable True if the RX transaction termination is to be enabled, false otherwise.
740 */
741 NRF_STATIC_INLINE void nrf_twim_rx_terminate_on_bus_error_enable_set(NRF_TWIM_Type * p_reg,
742 bool enable);
743
744 /**
745 * @brief Function for checking if the RX transaction termination on the detection
746 * of a BUSERROR event is enabled.
747 *
748 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
749 *
750 * @retval true Transaction termination on BUSERROR event is enabled.
751 * @retval false Transaction termination on BUSERROR event is disabled.
752 */
753 NRF_STATIC_INLINE bool nrf_twim_rx_terminate_on_bus_error_check(NRF_TWIM_Type const * p_reg);
754
755 /**
756 * @brief Function for enabling TX transaction termination on the detection of a BUSERROR event.
757 *
758 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
759 * @param[in] enable True if the TX transaction termination is to be enabled, false otherwise.
760 */
761 NRF_STATIC_INLINE void nrf_twim_tx_terminate_on_bus_error_enable_set(NRF_TWIM_Type * p_reg,
762 bool enable);
763
764 /**
765 * @brief Function for checking if the TX transaction termination on the detection
766 * of a BUSERROR event is enabled.
767 *
768 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
769 *
770 * @retval true Transaction termination on BUSERROR event is enabled.
771 * @retval false Transaction termination on BUSERROR event is disabled.
772 */
773 NRF_STATIC_INLINE bool nrf_twim_tx_terminate_on_bus_error_check(NRF_TWIM_Type const * p_reg);
774 #endif
775
776 #ifndef NRF_DECLARE_ONLY
777
nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,nrf_twim_task_t task)778 NRF_STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,
779 nrf_twim_task_t task)
780 {
781 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
782 }
783
nrf_twim_task_address_get(NRF_TWIM_Type const * p_reg,nrf_twim_task_t task)784 NRF_STATIC_INLINE uint32_t nrf_twim_task_address_get(NRF_TWIM_Type const * p_reg,
785 nrf_twim_task_t task)
786 {
787 return nrf_task_event_address_get(p_reg, task);
788 }
789
nrf_twim_event_clear(NRF_TWIM_Type * p_reg,nrf_twim_event_t event)790 NRF_STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
791 nrf_twim_event_t event)
792 {
793 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
794 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
795 }
796
nrf_twim_event_check(NRF_TWIM_Type const * p_reg,nrf_twim_event_t event)797 NRF_STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type const * p_reg,
798 nrf_twim_event_t event)
799 {
800 return nrf_event_check(p_reg, event);
801 }
802
nrf_twim_event_address_get(NRF_TWIM_Type const * p_reg,nrf_twim_event_t event)803 NRF_STATIC_INLINE uint32_t nrf_twim_event_address_get(NRF_TWIM_Type const * p_reg,
804 nrf_twim_event_t event)
805 {
806 return nrf_task_event_address_get(p_reg, event);
807 }
808
nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,uint32_t mask)809 NRF_STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,
810 uint32_t mask)
811 {
812 p_reg->SHORTS |= mask;
813 }
814
nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,uint32_t mask)815 NRF_STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,
816 uint32_t mask)
817 {
818 p_reg->SHORTS &= ~(mask);
819 }
820
nrf_twim_int_enable(NRF_TWIM_Type * p_reg,uint32_t mask)821 NRF_STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg,
822 uint32_t mask)
823 {
824 p_reg->INTENSET = mask;
825 }
826
nrf_twim_int_disable(NRF_TWIM_Type * p_reg,uint32_t mask)827 NRF_STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg,
828 uint32_t mask)
829 {
830 p_reg->INTENCLR = mask;
831 }
832
nrf_twim_int_enable_check(NRF_TWIM_Type const * p_reg,uint32_t mask)833 NRF_STATIC_INLINE uint32_t nrf_twim_int_enable_check(NRF_TWIM_Type const * p_reg, uint32_t mask)
834 {
835 return p_reg->INTENSET & mask;
836 }
837
838 #if defined(DPPI_PRESENT)
nrf_twim_subscribe_set(NRF_TWIM_Type * p_reg,nrf_twim_task_t task,uint8_t channel)839 NRF_STATIC_INLINE void nrf_twim_subscribe_set(NRF_TWIM_Type * p_reg,
840 nrf_twim_task_t task,
841 uint8_t channel)
842 {
843 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
844 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
845 }
846
nrf_twim_subscribe_clear(NRF_TWIM_Type * p_reg,nrf_twim_task_t task)847 NRF_STATIC_INLINE void nrf_twim_subscribe_clear(NRF_TWIM_Type * p_reg,
848 nrf_twim_task_t task)
849 {
850 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
851 }
852
nrf_twim_publish_set(NRF_TWIM_Type * p_reg,nrf_twim_event_t event,uint8_t channel)853 NRF_STATIC_INLINE void nrf_twim_publish_set(NRF_TWIM_Type * p_reg,
854 nrf_twim_event_t event,
855 uint8_t channel)
856 {
857 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
858 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
859 }
860
nrf_twim_publish_clear(NRF_TWIM_Type * p_reg,nrf_twim_event_t event)861 NRF_STATIC_INLINE void nrf_twim_publish_clear(NRF_TWIM_Type * p_reg,
862 nrf_twim_event_t event)
863 {
864 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
865 }
866 #endif // defined(DPPI_PRESENT)
867
nrf_twim_enable(NRF_TWIM_Type * p_reg)868 NRF_STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg)
869 {
870 p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos);
871 }
872
nrf_twim_disable(NRF_TWIM_Type * p_reg)873 NRF_STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg)
874 {
875 p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos);
876 }
877
nrf_twim_pins_set(NRF_TWIM_Type * p_reg,uint32_t scl_pin,uint32_t sda_pin)878 NRF_STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
879 uint32_t scl_pin,
880 uint32_t sda_pin)
881 {
882 p_reg->PSEL.SCL = scl_pin;
883 p_reg->PSEL.SDA = sda_pin;
884 }
885
nrf_twim_scl_pin_set(NRF_TWIM_Type * p_reg,uint32_t pin)886 NRF_STATIC_INLINE void nrf_twim_scl_pin_set(NRF_TWIM_Type * p_reg, uint32_t pin)
887 {
888 p_reg->PSEL.SCL = pin;
889 }
890
nrf_twim_sda_pin_set(NRF_TWIM_Type * p_reg,uint32_t pin)891 NRF_STATIC_INLINE void nrf_twim_sda_pin_set(NRF_TWIM_Type * p_reg, uint32_t pin)
892 {
893 p_reg->PSEL.SDA = pin;
894 }
895
nrf_twim_scl_pin_get(NRF_TWIM_Type const * p_reg)896 NRF_STATIC_INLINE uint32_t nrf_twim_scl_pin_get(NRF_TWIM_Type const * p_reg)
897 {
898 return p_reg->PSEL.SCL;
899 }
900
nrf_twim_sda_pin_get(NRF_TWIM_Type const * p_reg)901 NRF_STATIC_INLINE uint32_t nrf_twim_sda_pin_get(NRF_TWIM_Type const * p_reg)
902 {
903 return p_reg->PSEL.SDA;
904 }
905
nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,nrf_twim_frequency_t frequency)906 NRF_STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
907 nrf_twim_frequency_t frequency)
908 {
909 p_reg->FREQUENCY = frequency;
910 }
911
nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg)912 NRF_STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg)
913 {
914 uint32_t error_source = p_reg->ERRORSRC;
915
916 // [error flags are cleared by writing '1' on their position]
917 p_reg->ERRORSRC = error_source;
918
919 return error_source;
920 }
921
nrf_twim_address_set(NRF_TWIM_Type * p_reg,uint8_t address)922 NRF_STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
923 uint8_t address)
924 {
925 p_reg->ADDRESS = address;
926 }
927
nrf_twim_address_get(NRF_TWIM_Type const * p_reg)928 NRF_STATIC_INLINE uint8_t nrf_twim_address_get(NRF_TWIM_Type const * p_reg)
929 {
930 return (uint8_t)(p_reg->ADDRESS & TWIM_ADDRESS_ADDRESS_Msk);
931 }
932
nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,uint8_t const * p_buffer,size_t length)933 NRF_STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
934 uint8_t const * p_buffer,
935 size_t length)
936 {
937 #if NRF_TWIM_HAS_DMA_REG
938 p_reg->DMA.TX.PTR = (uint32_t)p_buffer;
939 p_reg->DMA.TX.MAXCNT = length;
940 #else
941 p_reg->TXD.PTR = (uint32_t)p_buffer;
942 p_reg->TXD.MAXCNT = length;
943 #endif
944 }
945
nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,uint8_t * p_buffer,size_t length)946 NRF_STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
947 uint8_t * p_buffer,
948 size_t length)
949 {
950 #if NRF_TWIM_HAS_DMA_REG
951 p_reg->DMA.RX.PTR = (uint32_t)p_buffer;
952 p_reg->DMA.RX.MAXCNT = length;
953 #else
954 p_reg->RXD.PTR = (uint32_t)p_buffer;
955 p_reg->RXD.MAXCNT = length;
956 #endif
957 }
958
nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,uint32_t mask)959 NRF_STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
960 uint32_t mask)
961 {
962 p_reg->SHORTS = mask;
963 }
964
nrf_twim_shorts_get(NRF_TWIM_Type const * p_reg)965 NRF_STATIC_INLINE uint32_t nrf_twim_shorts_get(NRF_TWIM_Type const * p_reg)
966 {
967 return p_reg->SHORTS;
968 }
969
nrf_twim_txd_amount_get(NRF_TWIM_Type const * p_reg)970 NRF_STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type const * p_reg)
971 {
972 #if NRF_TWIM_HAS_DMA_REG
973 return p_reg->DMA.TX.AMOUNT;
974 #else
975 return p_reg->TXD.AMOUNT;
976 #endif
977 }
978
nrf_twim_rxd_amount_get(NRF_TWIM_Type const * p_reg)979 NRF_STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type const * p_reg)
980 {
981 #if NRF_TWIM_HAS_DMA_REG
982 return p_reg->DMA.RX.AMOUNT;
983 #else
984 return p_reg->RXD.AMOUNT;
985 #endif
986 }
987
988 #if NRF_TWIM_HAS_DMA_CURRENTAMOUNT_REG
nrf_twim_txd_curr_amount_get(NRF_TWIM_Type const * p_reg)989 NRF_STATIC_INLINE size_t nrf_twim_txd_curr_amount_get(NRF_TWIM_Type const * p_reg)
990 {
991 return p_reg->DMA.TX.CURRENTAMOUNT;
992 }
993
nrf_twim_rxd_curr_amount_get(NRF_TWIM_Type const * p_reg)994 NRF_STATIC_INLINE size_t nrf_twim_rxd_curr_amount_get(NRF_TWIM_Type const * p_reg)
995 {
996 return p_reg->DMA.RX.CURRENTAMOUNT;
997 }
998 #endif
999
1000 #if NRF_TWIM_HAS_ARRAY_LIST
nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg)1001 NRF_STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg)
1002 {
1003 #if NRF_TWIM_HAS_DMA_REG
1004 p_reg->DMA.TX.LIST = TWIM_DMA_TX_LIST_TYPE_ArrayList << TWIM_DMA_TX_LIST_TYPE_Pos;
1005 #else
1006 p_reg->TXD.LIST = TWIM_TXD_LIST_LIST_ArrayList << TWIM_TXD_LIST_LIST_Pos;
1007 #endif
1008 }
1009
nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg)1010 NRF_STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg)
1011 {
1012 #if NRF_TWIM_HAS_DMA_REG
1013 p_reg->DMA.TX.LIST = TWIM_DMA_TX_LIST_TYPE_Disabled << TWIM_DMA_TX_LIST_TYPE_Pos;
1014 #else
1015 p_reg->TXD.LIST = TWIM_TXD_LIST_LIST_Disabled << TWIM_TXD_LIST_LIST_Pos;
1016 #endif
1017 }
1018
nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg)1019 NRF_STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg)
1020 {
1021 #if NRF_TWIM_HAS_DMA_REG
1022 p_reg->DMA.RX.LIST = TWIM_DMA_RX_LIST_TYPE_ArrayList << TWIM_DMA_RX_LIST_TYPE_Pos;
1023 #else
1024 p_reg->RXD.LIST = TWIM_RXD_LIST_LIST_ArrayList << TWIM_RXD_LIST_LIST_Pos;
1025 #endif
1026 }
1027
nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg)1028 NRF_STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg)
1029 {
1030 #if NRF_TWIM_HAS_DMA_REG
1031 p_reg->DMA.RX.LIST = TWIM_DMA_RX_LIST_TYPE_Disabled << TWIM_DMA_RX_LIST_TYPE_Pos;
1032 #else
1033 p_reg->RXD.LIST = TWIM_RXD_LIST_LIST_Disabled << TWIM_RXD_LIST_LIST_Pos;
1034 #endif
1035 }
1036 #endif
1037
1038 #if NRF_TWIM_HAS_DMA_REG
nrf_twim_rx_pattern_match_enable_set(NRF_TWIM_Type * p_reg,uint8_t index,bool enable)1039 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_enable_set(NRF_TWIM_Type * p_reg,
1040 uint8_t index,
1041 bool enable)
1042 {
1043 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
1044 switch (index)
1045 {
1046 case 0:
1047 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1048 ~TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk) |
1049 ((enable ?
1050 TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled :
1051 TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled)
1052 << TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos));
1053 break;
1054 case 1:
1055 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1056 ~TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk) |
1057 ((enable ?
1058 TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled :
1059 TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled)
1060 << TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos));
1061 break;
1062 case 2:
1063 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1064 ~TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk) |
1065 ((enable ?
1066 TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled :
1067 TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled)
1068 << TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos));
1069 break;
1070 case 3:
1071 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1072 ~TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk) |
1073 ((enable ?
1074 TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled :
1075 TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled)
1076 << TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos));
1077 break;
1078 default:
1079 NRFX_ASSERT(false);
1080 break;
1081 }
1082 }
1083
nrf_twim_rx_pattern_match_enable_check(NRF_TWIM_Type const * p_reg,uint8_t index)1084 NRF_STATIC_INLINE bool nrf_twim_rx_pattern_match_enable_check(NRF_TWIM_Type const * p_reg,
1085 uint8_t index)
1086 {
1087 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
1088 switch (index)
1089 {
1090 case 0:
1091 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk)
1092 >> TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) ==
1093 TWIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled;
1094 case 1:
1095 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk)
1096 >> TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) ==
1097 TWIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled;
1098 case 2:
1099 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk)
1100 >> TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) ==
1101 TWIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled;
1102 case 3:
1103 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk)
1104 >> TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) ==
1105 TWIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled;
1106 default:
1107 NRFX_ASSERT(false);
1108 return 0;
1109 }
1110 }
1111
nrf_twim_rx_pattern_match_one_shot_enable(NRF_TWIM_Type * p_reg,uint8_t index)1112 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_one_shot_enable(NRF_TWIM_Type * p_reg,
1113 uint8_t index)
1114 {
1115 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
1116 switch (index)
1117 {
1118 case 0:
1119 p_reg->DMA.RX.MATCH.CONFIG |= TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk;
1120 break;
1121 case 1:
1122 p_reg->DMA.RX.MATCH.CONFIG |= TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk;
1123 break;
1124 case 2:
1125 p_reg->DMA.RX.MATCH.CONFIG |= TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk;
1126 break;
1127 case 3:
1128 p_reg->DMA.RX.MATCH.CONFIG |= TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk;
1129 break;
1130 default:
1131 NRFX_ASSERT(false);
1132 break;
1133 }
1134 }
1135
nrf_twim_rx_pattern_match_one_shot_disable(NRF_TWIM_Type * p_reg,uint8_t index)1136 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_one_shot_disable(NRF_TWIM_Type * p_reg,
1137 uint8_t index)
1138 {
1139 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
1140 switch (index)
1141 {
1142 case 0:
1143 p_reg->DMA.RX.MATCH.CONFIG &= ~(TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk);
1144 break;
1145 case 1:
1146 p_reg->DMA.RX.MATCH.CONFIG &= ~(TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk);
1147 break;
1148 case 2:
1149 p_reg->DMA.RX.MATCH.CONFIG &= ~(TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk);
1150 break;
1151 case 3:
1152 p_reg->DMA.RX.MATCH.CONFIG &= ~(TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk);
1153 break;
1154 default:
1155 NRFX_ASSERT(false);
1156 break;
1157 }
1158 }
1159
nrf_twim_rx_pattern_match_one_shot_check(NRF_TWIM_Type const * p_reg,uint8_t index)1160 NRF_STATIC_INLINE bool nrf_twim_rx_pattern_match_one_shot_check(NRF_TWIM_Type const * p_reg,
1161 uint8_t index)
1162 {
1163 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
1164 switch (index)
1165 {
1166 case 0:
1167 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk)
1168 >> TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) ==
1169 TWIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot;
1170 case 1:
1171 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk)
1172 >> TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) ==
1173 TWIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot;
1174 case 2:
1175 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk)
1176 >> TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) ==
1177 TWIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot;
1178 case 3:
1179 return ((p_reg->DMA.RX.MATCH.CONFIG & TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk)
1180 >> TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) ==
1181 TWIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot;
1182 default:
1183 NRFX_ASSERT(false);
1184 return 0;
1185 }
1186 }
1187
nrf_twim_rx_pattern_match_candidate_set(NRF_TWIM_Type * p_reg,uint8_t index,uint32_t pattern)1188 NRF_STATIC_INLINE void nrf_twim_rx_pattern_match_candidate_set(NRF_TWIM_Type * p_reg,
1189 uint8_t index,
1190 uint32_t pattern)
1191 {
1192 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
1193 p_reg->DMA.RX.MATCH.CANDIDATE[index] = pattern;
1194 }
1195
nrf_twim_rx_pattern_match_candidate_get(NRF_TWIM_Type const * p_reg,uint8_t index)1196 NRF_STATIC_INLINE uint32_t nrf_twim_rx_pattern_match_candidate_get(NRF_TWIM_Type const * p_reg,
1197 uint8_t index)
1198 {
1199 NRFX_ASSERT(index < NRF_TWIM_DMA_RX_PATTERN_MAX_COUNT);
1200 return p_reg->DMA.RX.MATCH.CANDIDATE[index];
1201 }
1202 #endif // NRF_TWIM_HAS_DMA_REG
1203
1204 #if NRF_TWIM_HAS_BUS_ERROR_EVENTS
nrf_twim_rx_terminate_on_bus_error_enable_set(NRF_TWIM_Type * p_reg,bool enable)1205 NRF_STATIC_INLINE void nrf_twim_rx_terminate_on_bus_error_enable_set(NRF_TWIM_Type * p_reg,
1206 bool enable)
1207 {
1208 p_reg->DMA.RX.TERMINATEONBUSERROR = (enable ? TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled :
1209 TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled)
1210 << TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos;
1211 }
1212
nrf_twim_rx_terminate_on_bus_error_check(NRF_TWIM_Type const * p_reg)1213 NRF_STATIC_INLINE bool nrf_twim_rx_terminate_on_bus_error_check(NRF_TWIM_Type const * p_reg)
1214 {
1215 return ((p_reg->DMA.RX.TERMINATEONBUSERROR & TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk)
1216 >> TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) ==
1217 TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled;
1218 }
1219
nrf_twim_tx_terminate_on_bus_error_enable_set(NRF_TWIM_Type * p_reg,bool enable)1220 NRF_STATIC_INLINE void nrf_twim_tx_terminate_on_bus_error_enable_set(NRF_TWIM_Type * p_reg,
1221 bool enable)
1222 {
1223 p_reg->DMA.TX.TERMINATEONBUSERROR = (enable ? TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled :
1224 TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled)
1225 << TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos;
1226 }
1227
nrf_twim_tx_terminate_on_bus_error_check(NRF_TWIM_Type const * p_reg)1228 NRF_STATIC_INLINE bool nrf_twim_tx_terminate_on_bus_error_check(NRF_TWIM_Type const * p_reg)
1229 {
1230 return ((p_reg->DMA.TX.TERMINATEONBUSERROR & TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk)
1231 >> TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) ==
1232 TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled;
1233 }
1234 #endif // NRF_TWIM_HAS_BUS_ERROR_EVENTS
1235
1236 #endif // NRF_DECLARE_ONLY
1237
1238 /** @} */
1239
1240 #ifdef __cplusplus
1241 }
1242 #endif
1243
1244 #endif // NRF_TWIM_H__
1245
