1 /*
2 * Copyright (c) 2015 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_SPIM_H__
35 #define NRF_SPIM_H__
36
37 #include <nrfx.h>
38 #include <nrf_erratas.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 #if defined(NRF54H20_XXAA) || defined(NRF92_SERIES)
45 #define NRF_SPIM_CLOCKPIN_MOSI_NEEDED 1
46 #endif
47
48 #if defined(HALTIUM_XXAA)
49 #define NRF_SPIM_CLOCKPIN_SCK_NEEDED 1
50 #endif
51
52 /*
53 * Macro for generating code blocks that allow extracting
54 * the maximum prescaler value allowed for the specified SPIM instance.
55 */
56 #define _NRF_SPIM_PRESCALER_MAX_GET(periph_name, prefix, idx, p_reg) \
57 (p_reg == NRFX_CONCAT(NRF_, periph_name, prefix, idx)) ? \
58 (NRFX_CONCAT(periph_name, prefix, idx, _PRESCALER_DIVISOR_RANGE_MAX)) :
59
60 /*
61 * Macro for generating code blocks that allow extracting
62 * the minimum prescaler value allowed for the specified SPIM instance.
63 */
64 #define _NRF_SPIM_PRESCALER_MIN_GET(periph_name, prefix, idx, p_reg) \
65 (p_reg == NRFX_CONCAT(NRF_, periph_name, prefix, idx)) ? \
66 (NRFX_CONCAT(periph_name, prefix, idx, _PRESCALER_DIVISOR_RANGE_MIN)) :
67
68 /**
69 * @defgroup nrf_spim_hal SPIM HAL
70 * @{
71 * @ingroup nrf_spim
72 * @brief Hardware access layer for managing the SPIM peripheral.
73 */
74
75 /**
76 * @brief Macro getting pointer to the structure of registers of the SPIM peripheral.
77 *
78 * @param[in] idx SPIM instance index.
79 *
80 * @return Pointer to the structure of registers of the SPIM peripheral.
81 */
82 #define NRF_SPIM_INST_GET(idx) NRFX_CONCAT(NRF_, SPIM, idx)
83
84 #if defined(SPIM_FREQUENCY_FREQUENCY_M16) || defined(__NRFX_DOXYGEN__)
85 /** @brief Symbol indicating whether 16 MHz clock frequency is available. */
86 #define NRF_SPIM_HAS_16_MHZ_FREQ 1
87 #else
88 #define NRF_SPIM_HAS_16_MHZ_FREQ 0
89 #endif
90
91 #if defined(SPIM_FREQUENCY_FREQUENCY_M32) || defined(__NRFX_DOXYGEN__)
92 /** @brief Symbol indicating whether 32 MHz clock frequency is available. */
93 #define NRF_SPIM_HAS_32_MHZ_FREQ 1
94 #else
95 #define NRF_SPIM_HAS_32_MHZ_FREQ 0
96 #endif
97
98 #if defined(SPIM_FREQUENCY_FREQUENCY_Msk) || defined(__NRFX_DOXYGEN__)
99 /** @brief Symbol indicating whether frequency is used. */
100 #define NRF_SPIM_HAS_FREQUENCY 1
101 #else
102 #define NRF_SPIM_HAS_FREQUENCY 0
103 #endif
104
105 #if defined(SPIM_PRESCALER_DIVISOR_Msk) || defined(__NRFX_DOXYGEN__)
106 /** @brief Symbol indicating whether prescaler is used. */
107 #define NRF_SPIM_HAS_PRESCALER 1
108 #else
109 #define NRF_SPIM_HAS_PRESCALER 0
110 #endif
111
112 #if defined(SPIM_TXD_LIST_LIST_ArrayList) || defined(__NRFX_DOXYGEN__)
113 /** @brief Symbol indicating whether EasyDMA array list feature is present. */
114 #define NRF_SPIM_HAS_ARRAY_LIST 1
115 #else
116 #define NRF_SPIM_HAS_ARRAY_LIST 0
117 #endif
118
119 #if defined(SPIM_DMA_RX_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
120 /** @brief Symbol indicating whether dedicated DMA register is present. */
121 #define NRF_SPIM_HAS_DMA_REG 1
122 #else
123 #define NRF_SPIM_HAS_DMA_REG 0
124 #endif
125
126 #if (defined(SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk) && \
127 defined(SPIM_EVENTS_DMA_RX_END_END_Msk)) || \
128 defined(__NRFX_DOXYGEN__)
129 /** @brief Symbol indicating whether SPIM DMA tasks and events are present. */
130 #define NRF_SPIM_HAS_DMA_TASKS_EVENTS 1
131 #else
132 #define NRF_SPIM_HAS_DMA_TASKS_EVENTS 0
133 #endif
134
135 /** @brief Macro for checking if the hardware chip select function is available. */
136 #if NRFX_FEATURE_PRESENT(SPIM, _FEATURE_HARDWARE_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
137 #define NRF_SPIM_HAS_HW_CSN 1
138 #else
139 #define NRF_SPIM_HAS_HW_CSN 0
140 #endif
141
142 /** @brief Macro for checking if the DCX pin control is available. */
143 #if NRFX_FEATURE_PRESENT(SPIM, _FEATURE_HARDWARE_DCX_PRESENT) || \
144 NRFX_FEATURE_PRESENT(SPIM, _FEATURE_DCX_PRESENT) || \
145 defined(__NRFX_DOXYGEN__)
146 #define NRF_SPIM_HAS_DCX 1
147 #else
148 #define NRF_SPIM_HAS_DCX 0
149 #endif
150
151 /** @brief Macro for checking if the RXDELAY function is available. */
152 #if NRFX_FEATURE_PRESENT(SPIM, _FEATURE_RXDELAY_PRESENT) || defined(__NRFX_DOXYGEN__)
153 #define NRF_SPIM_HAS_RXDELAY 1
154 #else
155 #define NRF_SPIM_HAS_RXDELAY 0
156 #endif
157
158 #if defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__)
159 /** @brief Macro for checking if the STALLSTAT feature is available. */
160 #define NRF_SPIM_HAS_STALLSTAT 1
161 #else
162 #define NRF_SPIM_HAS_STALLSTAT 0
163 #endif
164
165 #if NRF_SPIM_HAS_HW_CSN || NRF_SPIM_HAS_DCX || NRF_SPIM_HAS_RXDELAY
166 /** @brief Symbol indicating whether any of the SPIM extended features is available. */
167 #define NRF_SPIM_HAS_EXTENDED 1
168 #else
169 #define NRF_SPIM_HAS_EXTENDED 0
170 #endif
171
172 #if NRF_SPIM_HAS_DCX
173 /**
174 * @brief This value specified in the DCX line configuration causes this line
175 * to be set low during whole transmission (all transmitted bytes are
176 * marked as command bytes). Any lower value causes the DCX line to be
177 * switched from low to high after this number of bytes is transmitted
178 * (all remaining bytes are marked as data bytes).
179 */
180 #define NRF_SPIM_DCX_CNT_ALL_CMD 0xF
181 #endif
182
183 /**
184 * @brief This value can be used as a parameter for the @ref nrf_spim_pins_set
185 * function to specify that a given SPI signal (SCK, MOSI, or MISO)
186 * shall not be connected to a physical pin.
187 */
188 #define NRF_SPIM_PIN_NOT_CONNECTED 0xFFFFFFFF
189
190 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
191 /** @brief Max number of RX patterns. */
192 #define NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT SPIM_DMA_RX_MATCH_CANDIDATE_MaxCount
193 #endif
194
195 #if NRF_SPIM_HAS_DCX
196 #if defined(SPIM_PSEL_DCX_ResetValue) || defined(__NRFX_DOXYGEN__)
197 /** @brief Symbol specifying default value of DCX pin setting. */
198 #define NRF_SPIM_DCX_DEFAULT SPIM_PSEL_DCX_ResetValue
199 #else
200 #define NRF_SPIM_DCX_DEFAULT 0xFFFFFFFFUL
201 #endif
202 #endif // NRF_SPIM_HAS_DCX
203
204 #if NRF_SPIM_HAS_HW_CSN
205 #if defined(SPIM_PSEL_CSN_ResetValue) || defined(__NRFX_DOXYGEN__)
206 /** @brief Symbol specifying default value of CSN pin setting. */
207 #define NRF_SPIM_CSN_DEFAULT SPIM_PSEL_CSN_ResetValue
208 #else
209 #define NRF_SPIM_CSN_DEFAULT 0xFFFFFFFFUL
210 #endif
211
212 #if defined(SPIM_CSNDUR_ResetValue) || defined(__NRFX_DOXYGEN__)
213 /** @brief Symbol specifying default value of CSN duration setting. */
214 #define NRF_SPIM_CSNDUR_DEFAULT SPIM_CSNDUR_ResetValue
215 #else
216 #define NRF_SPIM_CSNDUR_DEFAULT 0x2UL
217 #endif
218
219 #if defined(SPIM_CSNPOL_ResetValue) || defined(__NRFX_DOXYGEN__)
220 /** @brief Symbol specifying default value of CSN polarity setting. */
221 #define NRF_SPIM_CSNPOL_DEFAULT SPIM_CSNPOL_ResetValue
222 #else
223 #define NRF_SPIM_CSNPOL_DEFAULT 0x0UL
224 #endif
225 #endif // NRF_SPIM_HAS_HW_CSN
226
227 #if NRF_SPIM_HAS_RXDELAY
228 #if defined(SPIM_IFTIMING_RXDELAY_ResetValue) || defined(__NRFX_DOXYGEN__)
229 /** @brief Symbol specifying default value of RX delay setting. */
230 #define NRF_SPIM_RXDELAY_DEFAULT SPIM_IFTIMING_RXDELAY_ResetValue
231 #else
232 #define NRF_SPIM_RXDELAY_DEFAULT 0x2UL
233 #endif
234 #endif // NRF_SPIM_HAS_RXDELAY
235
236 /** @brief Minimal SPIM frequency in Hz. */
237 #define NRF_SPIM_MIN_FREQUENCY (NRFX_KHZ_TO_HZ(125UL))
238
239 /** @brief Base frequency value 320 MHz for SPIM. */
240 #define NRF_SPIM_BASE_FREQUENCY_320MHZ (NRFX_MHZ_TO_HZ(320UL))
241
242 /** @brief Base frequency value 192 MHz for SPIM. */
243 #define NRF_SPIM_BASE_FREQUENCY_192MHZ (NRFX_MHZ_TO_HZ(192UL))
244
245 /** @brief Base frequency value 128 MHz for SPIM. */
246 #define NRF_SPIM_BASE_FREQUENCY_128MHZ (NRFX_MHZ_TO_HZ(128UL))
247
248 /** @brief Base frequency value 64 MHz for SPIM. */
249 #define NRF_SPIM_BASE_FREQUENCY_64MHZ (NRFX_MHZ_TO_HZ(64UL))
250
251 /** @brief Base frequency value 32 MHz for SPIM. */
252 #define NRF_SPIM_BASE_FREQUENCY_32MHZ (NRFX_MHZ_TO_HZ(32UL))
253
254 /** @brief Base frequency value 16 MHz for SPIM. */
255 #define NRF_SPIM_BASE_FREQUENCY_16MHZ (NRFX_MHZ_TO_HZ(16UL))
256
257 #if !defined(NRF_SPIM_IS_320MHZ_SPIM)
258 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 320 MHz. */
259 #define NRF_SPIM_IS_320MHZ_SPIM(p_reg) \
260 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(SPIM120), (p_reg == NRF_SPIM120), (false)) || \
261 NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(SPIM121), (p_reg == NRF_SPIM121), (false)))
262 #endif
263
264 #if !defined(NRF_SPIM_IS_192MHZ_SPIM)
265 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 192 MHz. */
266 #define NRF_SPIM_IS_192MHZ_SPIM(p_reg) false
267 #endif
268
269 #if !defined(NRF_SPIM_IS_128MHZ_SPIM)
270 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 128 MHz. */
271 #define NRF_SPIM_IS_128MHZ_SPIM(p_reg) \
272 (NRFX_COND_CODE_1(NRFX_IS_ENABLED(NRF_CPU_FREQ_IS_128MHZ), \
273 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(SPIM00), (p_reg == NRF_SPIM00), (false))), \
274 (false)))
275 #endif
276
277 #if !defined(NRF_SPIM_IS_64MHZ_SPIM)
278 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 64 MHz. */
279 #define NRF_SPIM_IS_64MHZ_SPIM(p_reg) \
280 (NRFX_COND_CODE_1(NRFX_IS_ENABLED(NRF_CPU_FREQ_IS_64MHZ), \
281 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(SPIM00), (p_reg == NRF_SPIM00), (false))), \
282 (false)))
283 #endif
284
285 #if !defined(NRF_SPIM_IS_32MHZ_SPIM)
286 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 32 MHz. */
287 #define NRF_SPIM_IS_32MHZ_SPIM(p_reg) false
288 #endif
289
290 /** @brief Macro for getting base frequency value in Hz for the specified SPIM instance. */
291 #define NRF_SPIM_BASE_FREQUENCY_GET(p_reg) \
292 ((NRF_SPIM_IS_320MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_320MHZ) : \
293 ((NRF_SPIM_IS_192MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_192MHZ) : \
294 ((NRF_SPIM_IS_128MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_128MHZ) : \
295 ((NRF_SPIM_IS_64MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_64MHZ) : \
296 ((NRF_SPIM_IS_32MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_32MHZ) : \
297 (NRF_SPIM_BASE_FREQUENCY_16MHZ))))))
298
299 #if NRF_SPIM_HAS_PRESCALER
300 /**
301 * @brief Macro for getting the maximum value of PRESCALER register.
302 *
303 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
304 */
305 #define NRF_SPIM_PRESCALER_MAX_GET(p_reg) \
306 (NRFX_FOREACH_ENABLED(SPIM, _NRF_SPIM_PRESCALER_MAX_GET, (), (), p_reg) \
307 SPIM_PRESCALER_DIVISOR_Max)
308
309 /**
310 * @brief Macro for getting the minimum value of PRESCALER register.
311 *
312 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
313 */
314 #define NRF_SPIM_PRESCALER_MIN_GET(p_reg) \
315 (NRFX_FOREACH_ENABLED(SPIM, _NRF_SPIM_PRESCALER_MIN_GET, (), (), p_reg) \
316 SPIM_PRESCALER_DIVISOR_Min)
317
318 /**
319 * @brief Macro for computing prescaler value for a given SPIM instance and desired frequency.
320 *
321 * @warning Not every combination of base and desired frequency is supported.
322 * The @ref NRF_SPIM_FREQUENCY_STATIC_CHECK macro can be used to check if the desired frequency is supported.
323 *
324 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
325 * @param[in] frequency Desired frequency value in Hz.
326 */
327 #define NRF_SPIM_PRESCALER_CALCULATE(p_reg, frequency) \
328 ((uint32_t)(NRF_SPIM_BASE_FREQUENCY_GET(p_reg)) / (uint32_t)(frequency))
329 #endif
330
331 /**
332 * @brief Macro for checking whether specified frequency can be achieved for a given SPIM instance.
333 *
334 * @note This macro uses a compile-time assertion.
335 *
336 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
337 * @param[in] frequency Desired frequency value in Hz.
338 */
339 #define NRF_SPIM_FREQUENCY_STATIC_CHECK(p_reg, frequency) \
340 NRFX_STATIC_ASSERT( \
341 NRFX_COND_CODE_1(NRF_SPIM_HAS_PRESCALER, \
342 ((NRF_SPIM_BASE_FREQUENCY_GET(p_reg) % (uint32_t)frequency == 0) && \
343 (NRFX_IS_EVEN(NRF_SPIM_PRESCALER_CALCULATE(p_reg, (uint32_t)frequency))) && \
344 (NRF_SPIM_PRESCALER_CALCULATE(p_reg, (uint32_t)frequency) >= (NRF_SPIM_PRESCALER_MIN_GET(p_reg))) && \
345 (NRF_SPIM_PRESCALER_CALCULATE(p_reg, (uint32_t)frequency) <= (NRF_SPIM_PRESCALER_MAX_GET(p_reg)))) \
346 , \
347 (((uint32_t)frequency == (uint32_t)NRFX_KHZ_TO_HZ(125)) || \
348 ((uint32_t)frequency == (uint32_t)NRFX_KHZ_TO_HZ(250)) || \
349 ((uint32_t)frequency == (uint32_t)NRFX_KHZ_TO_HZ(500)) || \
350 ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(1)) || \
351 ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(2)) || \
352 ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(4)) || \
353 ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(8)) || \
354 (((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(16)) && (NRF_SPIM_HAS_16_MHZ_FREQ)) || \
355 (((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(32)) && (NRF_SPIM_HAS_32_MHZ_FREQ)))))
356
357 /** @brief SPIM tasks. */
358 typedef enum
359 {
360 NRF_SPIM_TASK_START = offsetof(NRF_SPIM_Type, TASKS_START), ///< Start SPI transaction.
361 NRF_SPIM_TASK_STOP = offsetof(NRF_SPIM_Type, TASKS_STOP), ///< Stop SPI transaction.
362 NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction.
363 NRF_SPIM_TASK_RESUME = offsetof(NRF_SPIM_Type, TASKS_RESUME), ///< Resume SPI transaction.
364 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
365 NRF_SPIM_TASK_ENABLERXMATCH0 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.ENABLEMATCH[0]), ///< Enable SPI pattern matching functionality for pattern 0.
366 NRF_SPIM_TASK_ENABLERXMATCH1 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.ENABLEMATCH[1]), ///< Enable SPI pattern matching functionality for pattern 1.
367 NRF_SPIM_TASK_ENABLERXMATCH2 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.ENABLEMATCH[2]), ///< Enable SPI pattern matching functionality for pattern 2.
368 NRF_SPIM_TASK_ENABLERXMATCH3 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.ENABLEMATCH[3]), ///< Enable SPI pattern matching functionality for pattern 3.
369 NRF_SPIM_TASK_DISABLERXMATCH0 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.DISABLEMATCH[0]), ///< Disable SPI pattern matching functionality for pattern 0.
370 NRF_SPIM_TASK_DISABLERXMATCH1 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.DISABLEMATCH[1]), ///< Disable SPI pattern matching functionality for pattern 1.
371 NRF_SPIM_TASK_DISABLERXMATCH2 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.DISABLEMATCH[2]), ///< Disable SPI pattern matching functionality for pattern 2.
372 NRF_SPIM_TASK_DISABLERXMATCH3 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.DISABLEMATCH[3]) ///< Disable SPI pattern matching functionality for pattern 3.
373 #endif
374 } nrf_spim_task_t;
375
376 /** @brief SPIM events. */
377 typedef enum
378 {
379 NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED), ///< SPI transaction has started.
380 NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped.
381 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
382 NRF_SPIM_EVENT_RXSTARTED = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.READY), ///< Receive sequence started.
383 NRF_SPIM_EVENT_RXBUSERROR = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.BUSERROR), ///< Memory bus error occurred during the RX transfer.
384 NRF_SPIM_EVENT_RXMATCH0 = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.MATCH[0]), ///< Pattern match for pattern 0 detected.
385 NRF_SPIM_EVENT_RXMATCH1 = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.MATCH[1]), ///< Pattern match for pattern 1 detected.
386 NRF_SPIM_EVENT_RXMATCH2 = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.MATCH[2]), ///< Pattern match for pattern 2 detected.
387 NRF_SPIM_EVENT_RXMATCH3 = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.MATCH[3]), ///< Pattern match for pattern 3 detected.
388 NRF_SPIM_EVENT_TXSTARTED = offsetof(NRF_SPIM_Type, EVENTS_DMA.TX.READY), ///< Transmit sequence started.
389 NRF_SPIM_EVENT_TXBUSERROR = offsetof(NRF_SPIM_Type, EVENTS_DMA.TX.BUSERROR), ///< Memory bus error occurred during the TX transfer.
390 NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.END), ///< End of RXD buffer reached.
391 NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_DMA.TX.END), ///< End of TXD buffer reached.
392 #else
393 NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_ENDRX), ///< End of RXD buffer reached.
394 NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_ENDTX), ///< End of TXD buffer reached.
395 #endif
396 NRF_SPIM_EVENT_END = offsetof(NRF_SPIM_Type, EVENTS_END) ///< End of RXD buffer and TXD buffer reached.
397 } nrf_spim_event_t;
398
399 /** @brief SPIM shortcuts. */
400 typedef enum
401 {
402 NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk, ///< Shortcut between END event and START task.
403 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
404 NRF_SPIM_SHORT_RXMATCH0_ENABLERXMATCH1_MASK = SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.ENABLEMATCH1 task.
405 NRF_SPIM_SHORT_RXMATCH1_ENABLERXMATCH2_MASK = SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.ENABLEMATCH2 task.
406 NRF_SPIM_SHORT_RXMATCH2_ENABLERXMATCH3_MASK = SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.ENABLEMATCH3 task.
407 NRF_SPIM_SHORT_RXMATCH3_ENABLERXMATCH0_MASK = SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.ENABLEMATCH4 task.
408 NRF_SPIM_SHORT_RXMATCH0_DISABLERXMATCH0_MASK = SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.DISABLEMATCH0 task.
409 NRF_SPIM_SHORT_RXMATCH1_DISABLERXMATCH1_MASK = SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.DISABLEMATCH1 task.
410 NRF_SPIM_SHORT_RXMATCH2_DISABLERXMATCH2_MASK = SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.DISABLEMATCH2 task.
411 NRF_SPIM_SHORT_RXMATCH3_DISABLERXMATCH3_MASK = SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.DISABLEMATCH3 task.
412 #endif
413 NRF_SPIM_ALL_SHORTS_MASK = SPIM_SHORTS_END_START_Msk
414 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
415 | SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk
416 | SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk
417 | SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk
418 | SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk
419 | SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk
420 | SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk
421 | SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk
422 | SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk ///< All SPIM shortcuts.
423 #endif
424 } nrf_spim_short_mask_t;
425
426 /** @brief SPIM interrupts. */
427 typedef enum
428 {
429 NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk, ///< Interrupt on STARTED event.
430 NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
431 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
432 NRF_SPIM_INT_RXREADY_MASK = SPIM_INTENSET_DMARXREADY_Msk, ///< Interrupt on DMA.RX.READY event.
433 NRF_SPIM_INT_RXBUSERROR_MASK = SPIM_INTENSET_DMARXBUSERROR_Msk, ///< Interrupt on DMA.RX.BUSERROR event.
434 NRF_SPIM_INT_RXMATCH0_MASK = SPIM_INTENSET_DMARXMATCH0_Msk, ///< Interrupt on DMA.RX.MATCH0 event.
435 NRF_SPIM_INT_RXMATCH1_MASK = SPIM_INTENSET_DMARXMATCH1_Msk, ///< Interrupt on DMA.RX.MATCH1 event.
436 NRF_SPIM_INT_RXMATCH2_MASK = SPIM_INTENSET_DMARXMATCH2_Msk, ///< Interrupt on DMA.RX.MATCH2 event.
437 NRF_SPIM_INT_RXMATCH3_MASK = SPIM_INTENSET_DMARXMATCH3_Msk, ///< Interrupt on DMA.RX.MATCH3 event.
438 NRF_SPIM_INT_TXREADY_MASK = SPIM_INTENSET_DMATXREADY_Msk, ///< Interrupt on DMA.TX.READY event.
439 NRF_SPIM_INT_TXBUSERROR_MASK = SPIM_INTENSET_DMATXBUSERROR_Msk, ///< Interrupt on DMA.TX.BUSERROR event.
440 NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_DMARXEND_Msk, ///< Interrupt on ENDRX event.
441 NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_DMATXEND_Msk, ///< Interrupt on ENDTX event.
442 #else
443 NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
444 NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
445 #endif
446 NRF_SPIM_INT_END_MASK = SPIM_INTENSET_END_Msk, ///< Interrupt on END event.
447 NRF_SPIM_ALL_INTS_MASK = NRF_SPIM_INT_STARTED_MASK
448 | NRF_SPIM_INT_STOPPED_MASK
449 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
450 | NRF_SPIM_INT_RXREADY_MASK
451 | NRF_SPIM_INT_RXBUSERROR_MASK
452 | NRF_SPIM_INT_RXMATCH0_MASK
453 | NRF_SPIM_INT_RXMATCH1_MASK
454 | NRF_SPIM_INT_RXMATCH2_MASK
455 | NRF_SPIM_INT_RXMATCH3_MASK
456 | NRF_SPIM_INT_TXREADY_MASK
457 | NRF_SPIM_INT_TXBUSERROR_MASK
458 #endif
459 | NRF_SPIM_INT_ENDRX_MASK
460 | NRF_SPIM_INT_ENDTX_MASK
461 | NRF_SPIM_INT_END_MASK ///< All SPIM interrupts.
462 } nrf_spim_int_mask_t;
463
464 #if NRF_SPIM_HAS_FREQUENCY
465 /** @brief SPI master data rates. */
466 typedef enum
467 {
468 NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps.
469 NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
470 NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500, ///< 500 kbps.
471 NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps.
472 NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps.
473 NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps.
474 // Conversion to int is needed to prevent compilers from getting an error message
475 // that the provided value (0x80000000UL) is out of range for int.
476 NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8, ///< 8 Mbps.
477 #if NRF_SPIM_HAS_16_MHZ_FREQ
478 NRF_SPIM_FREQ_16M = SPIM_FREQUENCY_FREQUENCY_M16, ///< 16 Mbps.
479 #endif
480 #if NRF_SPIM_HAS_32_MHZ_FREQ
481 NRF_SPIM_FREQ_32M = SPIM_FREQUENCY_FREQUENCY_M32 ///< 32 Mbps.
482 #endif
483 } nrf_spim_frequency_t;
484 #endif // NRF_SPIM_HAS_FREQUENCY
485
486 /** @brief SPI modes. */
487 typedef enum
488 {
489 NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock.
490 NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock.
491 NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock.
492 NRF_SPIM_MODE_3 ///< SCK active low, sample on trailing edge of clock.
493 } nrf_spim_mode_t;
494
495 /** @brief SPI bit orders. */
496 typedef enum
497 {
498 NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
499 NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
500 } nrf_spim_bit_order_t;
501
502 #if NRF_SPIM_HAS_HW_CSN
503 /** @brief SPI CSN pin polarity. */
504 typedef enum
505 {
506 #if defined(SPIM_CSNPOL_CSNPOL0_LOW)
507 NRF_SPIM_CSN_POL_LOW = SPIM_CSNPOL_CSNPOL0_LOW, ///< Active low (idle state high).
508 NRF_SPIM_CSN_POL_HIGH = SPIM_CSNPOL_CSNPOL0_HIGH ///< Active high (idle state low).
509 #else
510 NRF_SPIM_CSN_POL_LOW = SPIM_CSNPOL_CSNPOL_LOW, ///< Active low (idle state high).
511 NRF_SPIM_CSN_POL_HIGH = SPIM_CSNPOL_CSNPOL_HIGH ///< Active high (idle state low).
512 #endif
513 } nrf_spim_csn_pol_t;
514 #endif
515
516 /**
517 * @brief Function for activating the specified SPIM task.
518 *
519 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
520 * @param[in] task Task to be activated.
521 */
522 NRF_STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
523 nrf_spim_task_t task);
524
525 /**
526 * @brief Function for getting the address of the specified SPIM task register.
527 *
528 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
529 * @param[in] task The specified task.
530 *
531 * @return Address of the specified task register.
532 */
533 NRF_STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type const * p_reg,
534 nrf_spim_task_t task);
535
536 /**
537 * @brief Function for clearing the specified SPIM event.
538 *
539 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
540 * @param[in] event Event to be cleared.
541 */
542 NRF_STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
543 nrf_spim_event_t event);
544
545 /**
546 * @brief Function for retrieving the state of the SPIM event.
547 *
548 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
549 * @param[in] event Event to be checked.
550 *
551 * @retval true The event has been generated.
552 * @retval false The event has not been generated.
553 */
554 NRF_STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type const * p_reg,
555 nrf_spim_event_t event);
556
557 /**
558 * @brief Function for getting the address of the specified SPIM event register.
559 *
560 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
561 * @param[in] event The specified event.
562 *
563 * @return Address of the specified event register.
564 */
565 NRF_STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type const * p_reg,
566 nrf_spim_event_t event);
567
568 /**
569 * @brief Function for enabling the specified shortcuts.
570 *
571 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
572 * @param[in] mask Shortcuts to be enabled.
573 */
574 NRF_STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
575 uint32_t mask);
576
577 /**
578 * @brief Function for disabling the specified shortcuts.
579 *
580 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
581 * @param[in] mask Shortcuts to be disabled.
582 */
583 NRF_STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
584 uint32_t mask);
585
586 /**
587 * @brief Function for getting the shortcut setting.
588 *
589 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
590 *
591 * @return Current shortcut configuration.
592 */
593 NRF_STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type const * p_reg);
594
595 /**
596 * @brief Function for enabling the specified interrupts.
597 *
598 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
599 * @param[in] mask Mask of interrupts to be enabled.
600 * Use @ref nrf_spim_int_mask_t values for bit masking.
601 */
602 NRF_STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
603 uint32_t mask);
604
605 /**
606 * @brief Function for disabling the specified interrupts.
607 *
608 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
609 * @param[in] mask Mask of interrupts to be disabled.
610 * Use @ref nrf_spim_int_mask_t values for bit masking.
611 */
612 NRF_STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
613 uint32_t mask);
614
615 /**
616 * @brief Function for checking if the specified interrupts are enabled.
617 *
618 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
619 * @param[in] mask Mask of interrupts to be checked.
620 * Use @ref nrf_spim_int_mask_t values for bit masking.
621 *
622 * @return Mask of enabled interrupts.
623 */
624 NRF_STATIC_INLINE uint32_t nrf_spim_int_enable_check(NRF_SPIM_Type const * p_reg, uint32_t mask);
625
626 #if NRF_SPIM_HAS_PRESCALER
627 /**
628 * @brief Function for setting the prescaler value.
629 *
630 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
631 * @param[in] prescaler Prescaler value.
632 */
633 NRF_STATIC_INLINE void nrf_spim_prescaler_set(NRF_SPIM_Type * p_reg,
634 uint32_t prescaler);
635
636 /**
637 * @brief Function for getting the prescaler value.
638 *
639 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
640 *
641 * @return Prescaler value.
642 */
643 NRF_STATIC_INLINE uint32_t nrf_spim_prescaler_get(NRF_SPIM_Type const * p_reg);
644 #endif
645
646 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
647 /**
648 * @brief Function for setting the subscribe configuration for a given
649 * SPIM task.
650 *
651 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
652 * @param[in] task Task for which to set the configuration.
653 * @param[in] channel Channel through which to subscribe events.
654 */
655 NRF_STATIC_INLINE void nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg,
656 nrf_spim_task_t task,
657 uint8_t channel);
658
659 /**
660 * @brief Function for clearing the subscribe configuration for a given
661 * SPIM task.
662 *
663 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
664 * @param[in] task Task for which to clear the configuration.
665 */
666 NRF_STATIC_INLINE void nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg,
667 nrf_spim_task_t task);
668
669 /**
670 * @brief Function for setting the publish configuration for a given
671 * SPIM event.
672 *
673 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
674 * @param[in] event Event for which to set the configuration.
675 * @param[in] channel Channel through which to publish the event.
676 */
677 NRF_STATIC_INLINE void nrf_spim_publish_set(NRF_SPIM_Type * p_reg,
678 nrf_spim_event_t event,
679 uint8_t channel);
680
681 /**
682 * @brief Function for clearing the publish configuration for a given
683 * SPIM event.
684 *
685 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
686 * @param[in] event Event for which to clear the configuration.
687 */
688 NRF_STATIC_INLINE void nrf_spim_publish_clear(NRF_SPIM_Type * p_reg,
689 nrf_spim_event_t event);
690 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
691
692 /**
693 * @brief Function for enabling the SPIM peripheral.
694 *
695 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
696 */
697 NRF_STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg);
698
699 /**
700 * @brief Function for disabling the SPIM peripheral.
701 *
702 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
703 */
704 NRF_STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg);
705
706 /**
707 * @brief Function for checking if the SPIM peripheral is enabled.
708 *
709 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
710 *
711 * @retval true The SPIM is enabled.
712 * @retval false The SPIM is not enabled.
713 */
714 NRF_STATIC_INLINE bool nrf_spim_enable_check(NRF_SPIM_Type const * p_reg);
715
716 /**
717 * @brief Function for configuring SPIM pins.
718 *
719 * If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
720 * value instead of its pin number.
721 *
722 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
723 * @param[in] sck_pin SCK pin number.
724 * @param[in] mosi_pin MOSI pin number.
725 * @param[in] miso_pin MISO pin number.
726 */
727 NRF_STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
728 uint32_t sck_pin,
729 uint32_t mosi_pin,
730 uint32_t miso_pin);
731
732 /**
733 * @brief Function for setting the SCK pin.
734 *
735 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
736 * @param[in] pin SCK pin number.
737 */
738 NRF_STATIC_INLINE void nrf_spim_sck_pin_set(NRF_SPIM_Type * p_reg, uint32_t pin);
739
740 /**
741 * @brief Function for setting the MOSI pin
742 *
743 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
744 * @param[in] pin MOSI pin number.
745 */
746 NRF_STATIC_INLINE void nrf_spim_mosi_pin_set(NRF_SPIM_Type * p_reg, uint32_t pin);
747
748 /**
749 * @brief Function for setting the MISO pin.
750 *
751 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
752 * @param[in] pin MISO pin number.
753 */
754 NRF_STATIC_INLINE void nrf_spim_miso_pin_set(NRF_SPIM_Type * p_reg, uint32_t pin);
755
756 /**
757 * @brief Function for getting the SCK pin selection.
758 *
759 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
760 *
761 * @return SCK pin selection.
762 */
763 NRF_STATIC_INLINE uint32_t nrf_spim_sck_pin_get(NRF_SPIM_Type const * p_reg);
764
765 /**
766 * @brief Function for getting the MOSI pin selection.
767 *
768 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
769 *
770 * @return MOSI pin selection.
771 */
772 NRF_STATIC_INLINE uint32_t nrf_spim_mosi_pin_get(NRF_SPIM_Type const * p_reg);
773
774 /**
775 * @brief Function for getting the MISO pin selection.
776 *
777 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
778 *
779 * @return MISO pin selection.
780 */
781 NRF_STATIC_INLINE uint32_t nrf_spim_miso_pin_get(NRF_SPIM_Type const * p_reg);
782
783 #if NRF_SPIM_HAS_HW_CSN
784 /**
785 * @brief Function for configuring the SPIM hardware CSN pin.
786 *
787 * If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
788 * value instead of its pin number.
789 *
790 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
791 * @param[in] pin CSN pin number.
792 * @param[in] polarity CSN pin polarity.
793 * @param[in] duration Minimum duration between the edge of CSN and the edge of SCK
794 * and minimum duration of CSN must stay unselected between transactions.
795 * The value is specified in number of 64 MHz clock cycles (15.625 ns).
796 */
797 NRF_STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
798 uint32_t pin,
799 nrf_spim_csn_pol_t polarity,
800 uint32_t duration);
801
802 /**
803 * @brief Function for getting the CSN pin selection.
804 *
805 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
806 *
807 * @return CSN pin selection.
808 */
809 NRF_STATIC_INLINE uint32_t nrf_spim_csn_pin_get(NRF_SPIM_Type const * p_reg);
810 #endif
811
812 #if NRF_SPIM_HAS_DCX
813 /**
814 * @brief Function for configuring the SPIM DCX pin.
815 *
816 * If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
817 * value instead of its pin number.
818 *
819 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
820 * @param[in] dcx_pin DCX pin number.
821 */
822 NRF_STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
823 uint32_t dcx_pin);
824
825 /**
826 * @brief Function for getting the DCX pin selection.
827 *
828 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
829 *
830 * @return DCX pin selection.
831 */
832 NRF_STATIC_INLINE uint32_t nrf_spim_dcx_pin_get(NRF_SPIM_Type const * p_reg);
833
834 /**
835 * @brief Function for configuring the number of command bytes.
836 *
837 * Maximum value available for dividing the transmitted bytes into command
838 * bytes and data bytes is @ref NRF_SPIM_DCX_CNT_ALL_CMD - 1.
839 * The @ref NRF_SPIM_DCX_CNT_ALL_CMD value passed as the @c count parameter
840 * causes all transmitted bytes to be marked as command bytes.
841 *
842 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
843 * @param[in] count Number of command bytes preceding the data bytes.
844 */
845 NRF_STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,
846 uint32_t count);
847 #endif // NRF_SPIM_HAS_DCX
848
849 #if NRF_SPIM_HAS_RXDELAY
850 /**
851 * @brief Function for configuring the extended SPIM interface.
852 *
853 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
854 * @param[in] rxdelay Sample delay for input serial data on MISO,
855 * specified in 64 MHz clock cycles (15.625 ns) from the sampling edge of SCK.
856 */
857 NRF_STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
858 uint32_t rxdelay);
859 #endif
860
861 #if NRF_SPIM_HAS_STALLSTAT
862 /**
863 * @brief Function for clearing stall status for RX EasyDMA RAM accesses.
864 *
865 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
866 */
867 NRF_STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg);
868
869 /**
870 * @brief Function for getting stall status for RX EasyDMA RAM accesses.
871 *
872 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
873 *
874 * @return Stall status of RX EasyDMA RAM accesses.
875 */
876 NRF_STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type const * p_reg);
877
878 /**
879 * @brief Function for clearing stall status for TX EasyDMA RAM accesses.
880 *
881 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
882 */
883 NRF_STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg);
884
885 /**
886 * @brief Function for getting stall status for TX EasyDMA RAM accesses.
887 *
888 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
889 *
890 * @return Stall status of TX EasyDMA RAM accesses.
891 */
892 NRF_STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type const * p_reg);
893 #endif // NRF_SPIM_HAS_STALLSTAT
894
895 #if NRF_SPIM_HAS_FREQUENCY
896 /**
897 * @brief Function for setting the SPI master data rate.
898 *
899 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
900 * @param[in] frequency SPI frequency.
901 */
902 NRF_STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
903 nrf_spim_frequency_t frequency);
904
905 /**
906 * @brief Function for getting the SPI master data rate.
907 *
908 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
909 *
910 * @retval SPI master frequency.
911 */
912 NRF_STATIC_INLINE nrf_spim_frequency_t nrf_spim_frequency_get(NRF_SPIM_Type * p_reg);
913 #endif
914
915 /**
916 * @brief Function for setting the transmit buffer.
917 *
918 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
919 * @param[in] p_buffer Pointer to the buffer with data to send.
920 * @param[in] length Maximum number of data bytes to transmit.
921 */
922 NRF_STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
923 uint8_t const * p_buffer,
924 size_t length);
925
926 /**
927 * @brief Function for getting number of bytes transmitted in the last transaction.
928 *
929 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
930 *
931 * @retval Amount of bytes transmitted.
932 */
933 NRF_STATIC_INLINE uint32_t nrf_spim_tx_amount_get(NRF_SPIM_Type const * p_reg);
934
935 /**
936 * @brief Function for getting number of bytes to be transmitted in the next transaction.
937 *
938 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
939 *
940 * @retval Amount of bytes to be transmitted.
941 */
942 NRF_STATIC_INLINE uint32_t nrf_spim_tx_maxcnt_get(NRF_SPIM_Type const * p_reg);
943
944 /**
945 * @brief Function for setting the receive buffer.
946 *
947 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
948 * @param[in] p_buffer Pointer to the buffer for received data.
949 * @param[in] length Maximum number of data bytes to receive.
950 */
951 NRF_STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
952 uint8_t * p_buffer,
953 size_t length);
954
955 /**
956 * @brief Function for getting number of bytes received in the last transaction.
957 *
958 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
959 *
960 * @retval Amount of bytes received.
961 */
962 NRF_STATIC_INLINE uint32_t nrf_spim_rx_amount_get(NRF_SPIM_Type const * p_reg);
963
964 /**
965 * @brief Function for getting number of bytes to be received in the next transaction.
966 *
967 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
968 *
969 * @retval Amount of bytes to be received.
970 */
971 NRF_STATIC_INLINE uint32_t nrf_spim_rx_maxcnt_get(NRF_SPIM_Type const * p_reg);
972
973 /**
974 * @brief Function for setting the SPI configuration.
975 *
976 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
977 * @param[in] spi_mode SPI mode.
978 * @param[in] spi_bit_order SPI bit order.
979 */
980 NRF_STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
981 nrf_spim_mode_t spi_mode,
982 nrf_spim_bit_order_t spi_bit_order);
983
984 /**
985 * @brief Function for setting the over-read character.
986 *
987 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
988 * @param[in] orc Over-read character that is clocked out in case of
989 * an over-read of the TXD buffer.
990 */
991 NRF_STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
992 uint8_t orc);
993
994 #if NRF_SPIM_HAS_ARRAY_LIST
995 /**
996 * @brief Function for enabling the TX list feature.
997 *
998 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
999 */
1000 NRF_STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg);
1001
1002 /**
1003 * @brief Function for disabling the TX list feature.
1004 *
1005 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1006 */
1007 NRF_STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg);
1008
1009 /**
1010 * @brief Function for enabling the RX list feature.
1011 *
1012 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1013 */
1014 NRF_STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg);
1015
1016 /**
1017 * @brief Function for disabling the RX list feature.
1018 *
1019 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1020 */
1021 NRF_STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg);
1022 #endif
1023
1024 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
1025 /**
1026 * @brief Function for enabling individual pattern match filters.
1027 *
1028 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1029 * @param[in] index Index of pattern match filter.
1030 * @param[in] enable True if pattern match filter is to be enabled, false otherwise.
1031 */
1032 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_enable_set(NRF_SPIM_Type * p_reg,
1033 uint8_t index,
1034 bool enable);
1035
1036 /**
1037 * @brief Function for checking if the specified pattern match filter is enabled.
1038 *
1039 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1040 * @param[in] index Index of pattern match filter.
1041 *
1042 * @retval true Pattern match filter is enabled.
1043 * @retval false Pattern match filter is disabled.
1044 */
1045 NRF_STATIC_INLINE bool nrf_spim_rx_pattern_match_enable_check(NRF_SPIM_Type const * p_reg,
1046 uint8_t index);
1047
1048 /**
1049 * @brief Function for enabling one-shot operation for the specified match filter.
1050 *
1051 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1052 * @param[in] index Index of pattern match filter.
1053 */
1054 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_one_shot_enable(NRF_SPIM_Type * p_reg,
1055 uint8_t index);
1056
1057 /**
1058 * @brief Function for disabling one-shot operation for the specified match filter.
1059 *
1060 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1061 * @param[in] index Index of pattern match filter.
1062 */
1063 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_one_shot_disable(NRF_SPIM_Type * p_reg,
1064 uint8_t index);
1065
1066 /**
1067 * @brief Function for checking if specified pattern match filter is configured as one-shot.
1068 *
1069 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1070 * @param[in] index Index of pattern match filter.
1071 *
1072 * @retval true Pattern match filter is configured as one-shot.
1073 * @retval false Pattern match filter is configured as continuous.
1074 */
1075 NRF_STATIC_INLINE bool nrf_spim_rx_pattern_match_one_shot_check(NRF_SPIM_Type const * p_reg,
1076 uint8_t index);
1077
1078 /**
1079 * @brief Function for setting the pattern to be looked for by the specified match filter.
1080 *
1081 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1082 * @param[in] index Index of pattern match filter.
1083 * @param[in] pattern Pattern to be looked for.
1084 * Match will trigger the corresponding event, if enabled.
1085 */
1086 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_candidate_set(NRF_SPIM_Type * p_reg,
1087 uint8_t index,
1088 uint32_t pattern);
1089
1090 /**
1091 * @brief Function for getting the pattern that the specified match filter is looking for.
1092 *
1093 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1094 * @param[in] index Index of pattern match filter.
1095 *
1096 * @return Pattern that the specified match filter is looking for.
1097 */
1098 NRF_STATIC_INLINE uint32_t nrf_spim_rx_pattern_match_candidate_get(NRF_SPIM_Type const * p_reg,
1099 uint8_t index);
1100 #endif // NRF_SPIM_HAS_DMA_TASKS_EVENTS
1101
1102 #if NRF_SPIM_HAS_DMA_REG
1103 /**
1104 * @brief Function for enabling the termination of the RX transaction after detecting the BUSERROR event.
1105 *
1106 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1107 */
1108 NRF_STATIC_INLINE void nrf_spim_rx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg);
1109
1110 /**
1111 * @brief Function for disabling the termination of the RX transaction after detecting the BUSERROR event.
1112 *
1113 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1114 */
1115 NRF_STATIC_INLINE void nrf_spim_rx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg);
1116
1117 /**
1118 * @brief Function for checking if RX transaction termination after detecting the BUSERROR event is enabled.
1119 *
1120 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1121 *
1122 * @retval true RX transaction termination after detecting a BUSERROR event is enabled.
1123 * @retval false RX transaction termination after detecting a BUSERROR event is disabled.
1124 */
1125 NRF_STATIC_INLINE bool nrf_spim_rx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg);
1126
1127 /**
1128 * @brief Function for enabling the termination of the TX transaction after detecting the BUSERROR event.
1129 *
1130 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1131 */
1132 NRF_STATIC_INLINE void nrf_spim_tx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg);
1133
1134 /**
1135 * @brief Function for disabling the termination of the TX transaction after detecting the BUSERROR event.
1136 *
1137 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1138 */
1139 NRF_STATIC_INLINE void nrf_spim_tx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg);
1140
1141 /**
1142 * @brief Function for checking if TX transaction termination after detecting the BUSERROR event is enabled.
1143 *
1144 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1145 *
1146 * @retval true TX transaction termination after detecting a BUSERROR event is enabled.
1147 * @retval false TX transaction termination after detecting a BUSERROR event is disabled.
1148 */
1149 NRF_STATIC_INLINE bool nrf_spim_tx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg);
1150 #endif // NRF_SPIM_HAS_DMA_REG
1151
1152 #ifndef NRF_DECLARE_ONLY
1153
nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,nrf_spim_task_t task)1154 NRF_STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
1155 nrf_spim_task_t task)
1156 {
1157 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
1158 }
1159
nrf_spim_task_address_get(NRF_SPIM_Type const * p_reg,nrf_spim_task_t task)1160 NRF_STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type const * p_reg,
1161 nrf_spim_task_t task)
1162 {
1163 return nrf_task_event_address_get(p_reg, task);
1164 }
1165
nrf_spim_event_clear(NRF_SPIM_Type * p_reg,nrf_spim_event_t event)1166 NRF_STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
1167 nrf_spim_event_t event)
1168 {
1169 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
1170 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
1171 }
1172
nrf_spim_event_check(NRF_SPIM_Type const * p_reg,nrf_spim_event_t event)1173 NRF_STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type const * p_reg,
1174 nrf_spim_event_t event)
1175 {
1176 return nrf_event_check(p_reg, event);
1177 }
1178
nrf_spim_event_address_get(NRF_SPIM_Type const * p_reg,nrf_spim_event_t event)1179 NRF_STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type const * p_reg,
1180 nrf_spim_event_t event)
1181 {
1182 return nrf_task_event_address_get(p_reg, event);
1183 }
1184
nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,uint32_t mask)1185 NRF_STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
1186 uint32_t mask)
1187 {
1188 p_reg->SHORTS |= mask;
1189 }
1190
nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,uint32_t mask)1191 NRF_STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
1192 uint32_t mask)
1193 {
1194 p_reg->SHORTS &= ~(mask);
1195 }
1196
nrf_spim_shorts_get(NRF_SPIM_Type const * p_reg)1197 NRF_STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type const * p_reg)
1198 {
1199 return p_reg->SHORTS;
1200 }
1201
nrf_spim_int_enable(NRF_SPIM_Type * p_reg,uint32_t mask)1202 NRF_STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
1203 uint32_t mask)
1204 {
1205 p_reg->INTENSET = mask;
1206 }
1207
nrf_spim_int_disable(NRF_SPIM_Type * p_reg,uint32_t mask)1208 NRF_STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
1209 uint32_t mask)
1210 {
1211 p_reg->INTENCLR = mask;
1212 }
1213
nrf_spim_int_enable_check(NRF_SPIM_Type const * p_reg,uint32_t mask)1214 NRF_STATIC_INLINE uint32_t nrf_spim_int_enable_check(NRF_SPIM_Type const * p_reg, uint32_t mask)
1215 {
1216 return p_reg->INTENSET & mask;
1217 }
1218
1219 #if NRF_SPIM_HAS_PRESCALER
nrf_spim_prescaler_set(NRF_SPIM_Type * p_reg,uint32_t prescaler)1220 NRF_STATIC_INLINE void nrf_spim_prescaler_set(NRF_SPIM_Type * p_reg,
1221 uint32_t prescaler)
1222 {
1223 NRFX_ASSERT(prescaler >= NRF_SPIM_PRESCALER_MIN_GET(p_reg));
1224 NRFX_ASSERT(prescaler <= NRF_SPIM_PRESCALER_MAX_GET(p_reg));
1225 NRFX_ASSERT(NRFX_IS_EVEN(prescaler));
1226 p_reg->PRESCALER = prescaler;
1227 }
1228
nrf_spim_prescaler_get(NRF_SPIM_Type const * p_reg)1229 NRF_STATIC_INLINE uint32_t nrf_spim_prescaler_get(NRF_SPIM_Type const * p_reg)
1230 {
1231 return p_reg->PRESCALER;
1232 }
1233 #endif
1234
1235 #if defined(DPPI_PRESENT)
nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg,nrf_spim_task_t task,uint8_t channel)1236 NRF_STATIC_INLINE void nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg,
1237 nrf_spim_task_t task,
1238 uint8_t channel)
1239 {
1240 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
1241 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1242 }
1243
nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg,nrf_spim_task_t task)1244 NRF_STATIC_INLINE void nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg,
1245 nrf_spim_task_t task)
1246 {
1247 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
1248 }
1249
nrf_spim_publish_set(NRF_SPIM_Type * p_reg,nrf_spim_event_t event,uint8_t channel)1250 NRF_STATIC_INLINE void nrf_spim_publish_set(NRF_SPIM_Type * p_reg,
1251 nrf_spim_event_t event,
1252 uint8_t channel)
1253 {
1254 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
1255 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1256 }
1257
nrf_spim_publish_clear(NRF_SPIM_Type * p_reg,nrf_spim_event_t event)1258 NRF_STATIC_INLINE void nrf_spim_publish_clear(NRF_SPIM_Type * p_reg,
1259 nrf_spim_event_t event)
1260 {
1261 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
1262 }
1263 #endif
1264
nrf_spim_enable(NRF_SPIM_Type * p_reg)1265 NRF_STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg)
1266 {
1267 p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
1268 }
1269
nrf_spim_disable(NRF_SPIM_Type * p_reg)1270 NRF_STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg)
1271 {
1272 #if NRF52_ERRATA_89_ENABLE_WORKAROUND
1273 if (nrf52_errata_89())
1274 {
1275 uint32_t temp1 = *(volatile uint32_t *)((uint8_t *)p_reg + 0x508UL);
1276 uint32_t temp2 = *(volatile uint32_t *)((uint8_t *)p_reg + 0x50CUL);
1277 *(volatile uint32_t *)((uint8_t *)p_reg + 0x500) = 0;
1278 *(volatile uint32_t *)((uint8_t *)p_reg + 0x508) = 0xFFFFFFFF;
1279 *(volatile uint32_t *)((uint8_t *)p_reg + 0x50C) = 0xFFFFFFFF;
1280 *(volatile uint32_t *)((uint8_t *)p_reg + 0x500) = 9;
1281
1282 p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
1283
1284 *(volatile uint32_t *)((uint8_t *)p_reg + 0x508) = temp1;
1285 *(volatile uint32_t *)((uint8_t *)p_reg + 0x50C) = temp2;
1286 }
1287 else
1288 #endif
1289 {
1290 p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
1291 }
1292 }
1293
nrf_spim_enable_check(NRF_SPIM_Type const * p_reg)1294 NRF_STATIC_INLINE bool nrf_spim_enable_check(NRF_SPIM_Type const * p_reg)
1295 {
1296 return p_reg->ENABLE == SPIM_ENABLE_ENABLE_Enabled;
1297 }
1298
nrf_spim_pins_set(NRF_SPIM_Type * p_reg,uint32_t sck_pin,uint32_t mosi_pin,uint32_t miso_pin)1299 NRF_STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
1300 uint32_t sck_pin,
1301 uint32_t mosi_pin,
1302 uint32_t miso_pin)
1303 {
1304 p_reg->PSEL.SCK = sck_pin;
1305 p_reg->PSEL.MOSI = mosi_pin;
1306 p_reg->PSEL.MISO = miso_pin;
1307 }
1308
nrf_spim_sck_pin_set(NRF_SPIM_Type * p_reg,uint32_t pin)1309 NRF_STATIC_INLINE void nrf_spim_sck_pin_set(NRF_SPIM_Type * p_reg, uint32_t pin)
1310 {
1311 p_reg->PSEL.SCK = pin;
1312 }
1313
nrf_spim_mosi_pin_set(NRF_SPIM_Type * p_reg,uint32_t pin)1314 NRF_STATIC_INLINE void nrf_spim_mosi_pin_set(NRF_SPIM_Type * p_reg, uint32_t pin)
1315 {
1316 p_reg->PSEL.MOSI = pin;
1317 }
1318
nrf_spim_miso_pin_set(NRF_SPIM_Type * p_reg,uint32_t pin)1319 NRF_STATIC_INLINE void nrf_spim_miso_pin_set(NRF_SPIM_Type * p_reg, uint32_t pin)
1320 {
1321 p_reg->PSEL.MISO = pin;
1322 }
1323
nrf_spim_sck_pin_get(NRF_SPIM_Type const * p_reg)1324 NRF_STATIC_INLINE uint32_t nrf_spim_sck_pin_get(NRF_SPIM_Type const * p_reg)
1325 {
1326 return p_reg->PSEL.SCK;
1327 }
1328
nrf_spim_mosi_pin_get(NRF_SPIM_Type const * p_reg)1329 NRF_STATIC_INLINE uint32_t nrf_spim_mosi_pin_get(NRF_SPIM_Type const * p_reg)
1330 {
1331 return p_reg->PSEL.MOSI;
1332 }
1333
nrf_spim_miso_pin_get(NRF_SPIM_Type const * p_reg)1334 NRF_STATIC_INLINE uint32_t nrf_spim_miso_pin_get(NRF_SPIM_Type const * p_reg)
1335 {
1336 return p_reg->PSEL.MISO;
1337 }
1338
1339 #if NRF_SPIM_HAS_HW_CSN
nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,uint32_t pin,nrf_spim_csn_pol_t polarity,uint32_t duration)1340 NRF_STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
1341 uint32_t pin,
1342 nrf_spim_csn_pol_t polarity,
1343 uint32_t duration)
1344 {
1345 #if defined(SPIM_CSNPOL_CSNPOL0_LOW) && defined(SPIM_PSEL_CSN_MaxCount)
1346 p_reg->PSEL.CSN[0] = pin;
1347 #else
1348 p_reg->PSEL.CSN = pin;
1349 #endif
1350 p_reg->CSNPOL = polarity;
1351 p_reg->IFTIMING.CSNDUR = duration;
1352 }
1353
nrf_spim_csn_pin_get(NRF_SPIM_Type const * p_reg)1354 NRF_STATIC_INLINE uint32_t nrf_spim_csn_pin_get(NRF_SPIM_Type const * p_reg)
1355 {
1356 #if defined(SPIM_CSNPOL_CSNPOL0_LOW) && defined(SPIM_PSEL_CSN_MaxCount)
1357 return p_reg->PSEL.CSN[0];
1358 #else
1359 return p_reg->PSEL.CSN;
1360 #endif
1361 }
1362 #endif // NRF_SPIM_HAS_HW_CSN
1363
1364 #if NRF_SPIM_HAS_DCX
nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,uint32_t dcx_pin)1365 NRF_STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg, uint32_t dcx_pin)
1366 {
1367 #if defined(SPIM_PSEL_DCX_PIN_Msk)
1368 p_reg->PSEL.DCX = dcx_pin;
1369 #else
1370 p_reg->PSELDCX = dcx_pin;
1371 #endif
1372 }
1373
nrf_spim_dcx_pin_get(NRF_SPIM_Type const * p_reg)1374 NRF_STATIC_INLINE uint32_t nrf_spim_dcx_pin_get(NRF_SPIM_Type const * p_reg)
1375 {
1376 #if defined(SPIM_PSEL_DCX_PIN_Msk)
1377 return p_reg->PSEL.DCX;
1378 #else
1379 return p_reg->PSELDCX;
1380 #endif
1381 }
1382
nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,uint32_t dcx_cnt)1383 NRF_STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg, uint32_t dcx_cnt)
1384 {
1385 p_reg->DCXCNT = dcx_cnt;
1386 }
1387 #endif // NRF_SPIM_HAS_DCX
1388
1389 #if NRF_SPIM_HAS_RXDELAY
nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,uint32_t rxdelay)1390 NRF_STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
1391 uint32_t rxdelay)
1392 {
1393 p_reg->IFTIMING.RXDELAY = rxdelay;
1394 }
1395 #endif
1396
1397 #if NRF_SPIM_HAS_STALLSTAT
nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg)1398 NRF_STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg)
1399 {
1400 p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_RX_Msk);
1401 }
1402
nrf_spim_stallstat_rx_get(NRF_SPIM_Type const * p_reg)1403 NRF_STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type const * p_reg)
1404 {
1405 return (p_reg->STALLSTAT & SPIM_STALLSTAT_RX_Msk) != 0;
1406 }
1407
nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg)1408 NRF_STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg)
1409 {
1410 p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_TX_Msk);
1411 }
1412
nrf_spim_stallstat_tx_get(NRF_SPIM_Type const * p_reg)1413 NRF_STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type const * p_reg)
1414 {
1415 return (p_reg->STALLSTAT & SPIM_STALLSTAT_TX_Msk) != 0;
1416 }
1417 #endif
1418
1419 #if NRF_SPIM_HAS_FREQUENCY
nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,nrf_spim_frequency_t frequency)1420 NRF_STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
1421 nrf_spim_frequency_t frequency)
1422 {
1423 p_reg->FREQUENCY = (uint32_t)frequency;
1424 }
1425
nrf_spim_frequency_get(NRF_SPIM_Type * p_reg)1426 NRF_STATIC_INLINE nrf_spim_frequency_t nrf_spim_frequency_get(NRF_SPIM_Type * p_reg)
1427 {
1428 return (nrf_spim_frequency_t)(p_reg->FREQUENCY);
1429 }
1430 #endif
1431
nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,uint8_t const * p_buffer,size_t length)1432 NRF_STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
1433 uint8_t const * p_buffer,
1434 size_t length)
1435 {
1436 #if NRF_SPIM_HAS_DMA_REG
1437 p_reg->DMA.TX.PTR = (uint32_t)p_buffer;
1438 p_reg->DMA.TX.MAXCNT = length;
1439 #else
1440 p_reg->TXD.PTR = (uint32_t)p_buffer;
1441 p_reg->TXD.MAXCNT = length;
1442 #endif
1443 }
1444
nrf_spim_tx_amount_get(NRF_SPIM_Type const * p_reg)1445 NRF_STATIC_INLINE uint32_t nrf_spim_tx_amount_get(NRF_SPIM_Type const * p_reg)
1446 {
1447 #if NRF_SPIM_HAS_DMA_REG
1448 return p_reg->DMA.TX.AMOUNT;
1449 #else
1450 return p_reg->TXD.AMOUNT;
1451 #endif
1452 }
1453
nrf_spim_tx_maxcnt_get(NRF_SPIM_Type const * p_reg)1454 NRF_STATIC_INLINE uint32_t nrf_spim_tx_maxcnt_get(NRF_SPIM_Type const * p_reg)
1455 {
1456 #if NRF_SPIM_HAS_DMA_REG
1457 return p_reg->DMA.TX.MAXCNT;
1458 #else
1459 return p_reg->TXD.MAXCNT;
1460 #endif
1461 }
1462
nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,uint8_t * p_buffer,size_t length)1463 NRF_STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
1464 uint8_t * p_buffer,
1465 size_t length)
1466 {
1467 #if NRF_SPIM_HAS_DMA_REG
1468 p_reg->DMA.RX.PTR = (uint32_t)p_buffer;
1469 p_reg->DMA.RX.MAXCNT = length;
1470 #else
1471 p_reg->RXD.PTR = (uint32_t)p_buffer;
1472 p_reg->RXD.MAXCNT = length;
1473 #endif
1474 }
1475
nrf_spim_rx_amount_get(NRF_SPIM_Type const * p_reg)1476 NRF_STATIC_INLINE uint32_t nrf_spim_rx_amount_get(NRF_SPIM_Type const * p_reg)
1477 {
1478 #if NRF_SPIM_HAS_DMA_REG
1479 return p_reg->DMA.RX.AMOUNT;
1480 #else
1481 return p_reg->RXD.AMOUNT;
1482 #endif
1483 }
1484
nrf_spim_rx_maxcnt_get(NRF_SPIM_Type const * p_reg)1485 NRF_STATIC_INLINE uint32_t nrf_spim_rx_maxcnt_get(NRF_SPIM_Type const * p_reg)
1486 {
1487 #if NRF_SPIM_HAS_DMA_REG
1488 return p_reg->DMA.RX.MAXCNT;
1489 #else
1490 return p_reg->RXD.MAXCNT;
1491 #endif
1492 }
1493
nrf_spim_configure(NRF_SPIM_Type * p_reg,nrf_spim_mode_t spi_mode,nrf_spim_bit_order_t spi_bit_order)1494 NRF_STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
1495 nrf_spim_mode_t spi_mode,
1496 nrf_spim_bit_order_t spi_bit_order)
1497 {
1498 uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
1499 SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
1500 switch (spi_mode)
1501 {
1502 default:
1503 case NRF_SPIM_MODE_0:
1504 config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
1505 (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
1506 break;
1507
1508 case NRF_SPIM_MODE_1:
1509 config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
1510 (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
1511 break;
1512
1513 case NRF_SPIM_MODE_2:
1514 config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
1515 (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
1516 break;
1517
1518 case NRF_SPIM_MODE_3:
1519 config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
1520 (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
1521 break;
1522 }
1523 p_reg->CONFIG = config;
1524 }
1525
nrf_spim_orc_set(NRF_SPIM_Type * p_reg,uint8_t orc)1526 NRF_STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
1527 uint8_t orc)
1528 {
1529 p_reg->ORC = orc;
1530 }
1531
1532 #if NRF_SPIM_HAS_ARRAY_LIST
nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)1533 NRF_STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)
1534 {
1535 p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_ArrayList << SPIM_TXD_LIST_LIST_Pos;
1536 }
1537
nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)1538 NRF_STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)
1539 {
1540 p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_Disabled << SPIM_TXD_LIST_LIST_Pos;
1541 }
1542
nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)1543 NRF_STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)
1544 {
1545 p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_ArrayList << SPIM_RXD_LIST_LIST_Pos;
1546 }
1547
nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)1548 NRF_STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)
1549 {
1550 p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_Disabled << SPIM_RXD_LIST_LIST_Pos;
1551 }
1552 #endif
1553
1554 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
nrf_spim_rx_pattern_match_enable_set(NRF_SPIM_Type * p_reg,uint8_t index,bool enable)1555 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_enable_set(NRF_SPIM_Type * p_reg,
1556 uint8_t index,
1557 bool enable)
1558 {
1559 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1560 switch (index)
1561 {
1562 case 0:
1563 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1564 ~SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk) |
1565 ((enable ?
1566 SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled :
1567 SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled)
1568 << SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos));
1569 break;
1570 case 1:
1571 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1572 ~SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk) |
1573 ((enable ?
1574 SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled :
1575 SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled)
1576 << SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos));
1577 break;
1578 case 2:
1579 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1580 ~SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk) |
1581 ((enable ?
1582 SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled :
1583 SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled)
1584 << SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos));
1585 break;
1586 case 3:
1587 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1588 ~SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk) |
1589 ((enable ?
1590 SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled :
1591 SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled)
1592 << SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos));
1593 break;
1594 default:
1595 NRFX_ASSERT(false);
1596 break;
1597 }
1598 }
1599
nrf_spim_rx_pattern_match_enable_check(NRF_SPIM_Type const * p_reg,uint8_t index)1600 NRF_STATIC_INLINE bool nrf_spim_rx_pattern_match_enable_check(NRF_SPIM_Type const * p_reg,
1601 uint8_t index)
1602 {
1603 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1604 switch (index)
1605 {
1606 case 0:
1607 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk)
1608 >> SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) ==
1609 SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled;
1610 case 1:
1611 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk)
1612 >> SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) ==
1613 SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled;
1614 case 2:
1615 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk)
1616 >> SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) ==
1617 SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled;
1618 case 3:
1619 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk)
1620 >> SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) ==
1621 SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled;
1622 default:
1623 NRFX_ASSERT(false);
1624 return 0;
1625 }
1626 }
1627
nrf_spim_rx_pattern_match_one_shot_enable(NRF_SPIM_Type * p_reg,uint8_t index)1628 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_one_shot_enable(NRF_SPIM_Type * p_reg,
1629 uint8_t index)
1630 {
1631 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1632 switch (index)
1633 {
1634 case 0:
1635 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk;
1636 break;
1637 case 1:
1638 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk;
1639 break;
1640 case 2:
1641 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk;
1642 break;
1643 case 3:
1644 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk;
1645 break;
1646 default:
1647 NRFX_ASSERT(false);
1648 break;
1649 }
1650 }
1651
nrf_spim_rx_pattern_match_one_shot_disable(NRF_SPIM_Type * p_reg,uint8_t index)1652 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_one_shot_disable(NRF_SPIM_Type * p_reg,
1653 uint8_t index)
1654 {
1655 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1656 switch (index)
1657 {
1658 case 0:
1659 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk);
1660 break;
1661 case 1:
1662 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk);
1663 break;
1664 case 2:
1665 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk);
1666 break;
1667 case 3:
1668 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk);
1669 break;
1670 default:
1671 NRFX_ASSERT(false);
1672 break;
1673 }
1674 }
1675
nrf_spim_rx_pattern_match_one_shot_check(NRF_SPIM_Type const * p_reg,uint8_t index)1676 NRF_STATIC_INLINE bool nrf_spim_rx_pattern_match_one_shot_check(NRF_SPIM_Type const * p_reg,
1677 uint8_t index)
1678 {
1679 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1680 switch (index)
1681 {
1682 case 0:
1683 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk)
1684 >> SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) ==
1685 SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot;
1686 case 1:
1687 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk)
1688 >> SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) ==
1689 SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot;
1690 case 2:
1691 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk)
1692 >> SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) ==
1693 SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot;
1694 case 3:
1695 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk)
1696 >> SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) ==
1697 SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot;
1698 default:
1699 NRFX_ASSERT(false);
1700 return 0;
1701 }
1702 }
1703
nrf_spim_rx_pattern_match_candidate_set(NRF_SPIM_Type * p_reg,uint8_t index,uint32_t pattern)1704 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_candidate_set(NRF_SPIM_Type * p_reg,
1705 uint8_t index,
1706 uint32_t pattern)
1707 {
1708 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1709 p_reg->DMA.RX.MATCH.CANDIDATE[index] = pattern;
1710 }
1711
nrf_spim_rx_pattern_match_candidate_get(NRF_SPIM_Type const * p_reg,uint8_t index)1712 NRF_STATIC_INLINE uint32_t nrf_spim_rx_pattern_match_candidate_get(NRF_SPIM_Type const * p_reg,
1713 uint8_t index)
1714 {
1715 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1716 return p_reg->DMA.RX.MATCH.CANDIDATE[index];
1717 }
1718 #endif // NRF_SPIM_HAS_DMA_TASKS_EVENTS
1719
1720 #if NRF_SPIM_HAS_DMA_REG
nrf_spim_rx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg)1721 NRF_STATIC_INLINE void nrf_spim_rx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg)
1722 {
1723 p_reg->DMA.RX.TERMINATEONBUSERROR |= SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk;
1724 }
1725
nrf_spim_rx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg)1726 NRF_STATIC_INLINE void nrf_spim_rx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg)
1727 {
1728 p_reg->DMA.RX.TERMINATEONBUSERROR &= ~(SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk);
1729 }
1730
nrf_spim_rx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg)1731 NRF_STATIC_INLINE bool nrf_spim_rx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg)
1732 {
1733 return ((p_reg->DMA.RX.TERMINATEONBUSERROR & SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk)
1734 >> SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) ==
1735 SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled;
1736 }
1737
nrf_spim_tx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg)1738 NRF_STATIC_INLINE void nrf_spim_tx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg)
1739 {
1740 p_reg->DMA.TX.TERMINATEONBUSERROR |= SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk;
1741 }
1742
nrf_spim_tx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg)1743 NRF_STATIC_INLINE void nrf_spim_tx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg)
1744 {
1745 p_reg->DMA.TX.TERMINATEONBUSERROR &= ~(SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk);
1746 }
1747
nrf_spim_tx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg)1748 NRF_STATIC_INLINE bool nrf_spim_tx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg)
1749 {
1750 return ((p_reg->DMA.TX.TERMINATEONBUSERROR & SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk)
1751 >> SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) ==
1752 SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled;
1753 }
1754 #endif // NRF_SPIM_HAS_DMA_REG
1755
1756 #endif // NRF_DECLARE_ONLY
1757
1758 /** @} */
1759
1760 #ifdef __cplusplus
1761 }
1762 #endif
1763
1764 #endif // NRF_SPIM_H__
1765
