1 /*
2 * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_SAADC_H_
35 #define NRF_SAADC_H_
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_saadc_hal SAADC HAL
45 * @{
46 * @ingroup nrf_saadc
47 * @brief Hardware access layer for managing the SAADC peripheral.
48 */
49
50 /** @brief Symbol specifying the offset of interrupt bitmask for limits of all channels. */
51 #define NRF_SAADC_LIMITS_INT_OFFSET \
52 NRFX_MIN(SAADC_INTENSET_CH0LIMITH_Pos, SAADC_INTENSET_CH0LIMITL_Pos)
53
54 /** @brief Symbol specifying the interrupt bitmask for limits of all channels. */
55 #define NRF_SAADC_ALL_CHANNELS_LIMITS_INT_MASK \
56 ((uint32_t)(((1 << SAADC_CH_NUM) - 1) << NRF_SAADC_LIMITS_INT_OFFSET))
57
58 #if defined(SAADC_CH_CONFIG_TACQ_3us) || defined(__NRFX_DOXYGEN__)
59 /** @brief Symbol indicating whether the configuration of acquisition time using predefined values is present. */
60 #define NRF_SAADC_HAS_ACQTIME_ENUM 1
61 #else
62 #define NRF_SAADC_HAS_ACQTIME_ENUM 0
63 #endif
64
65 #if defined(SAADC_CH_CONFIG_TCONV_Msk) || defined(__NRFX_DOXYGEN__)
66 /** @brief Symbol indicating whether the configuration of conversion time is present. */
67 #define NRF_SAADC_HAS_CONVTIME 1
68 #else
69 #define NRF_SAADC_HAS_CONVTIME 0
70 #endif
71
72 #if defined(SAADC_TRIM_LINCALCOEFF_VAL_Msk) || defined(__NRFX_DOXYGEN__)
73 /** @brief Symbol indicating whether the configuration of linearity calibration coefficients is present. */
74 #define NRF_SAADC_HAS_LIN_CAL 1
75 #else
76 #define NRF_SAADC_HAS_LIN_CAL 0
77 #endif
78
79 #if defined(SAADC_CH_PSELP_PIN_Msk) || defined(__NRFX_DOXYGEN__)
80 /** @brief Symbol indicating whether configuration of analog input using pin number is present. */
81 #define NRF_SAADC_HAS_AIN_AS_PIN 1
82 #else
83 #define NRF_SAADC_HAS_AIN_AS_PIN 0
84 #endif
85
86 #if defined(SAADC_DMA_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
87 /** @brief Symbol indicating whether dedicated DMA register is present. */
88 #define NRF_SAADC_HAS_DMA_REG 1
89 #else
90 #define NRF_SAADC_HAS_DMA_REG 0
91 #endif
92
93 #if defined(SAADC_EVENTS_DMA_END_END_Msk) || defined(__NRFX_DOXYGEN__)
94 /** @brief Symbol indicating whether SAADC DMA events are present. */
95 #define NRF_SAADC_HAS_DMA_EVENTS 1
96 #else
97 #define NRF_SAADC_HAS_DMA_EVENTS 0
98 #endif
99
100 #if defined(SAADC_CH_CONFIG_RESP_Msk) || defined(__NRFX_DOXYGEN__)
101 /** @brief Symbol indicating whether SAADC channel resistor control is present. */
102 #define NRF_SAADC_HAS_CH_CONFIG_RES 1
103 #else
104 #define NRF_SAADC_HAS_CH_CONFIG_RES 0
105 #endif
106
107 #if !NRF_SAADC_HAS_ACQTIME_ENUM
108 /** @brief Maximum value of acquire time. */
109 #define NRF_SAADC_ACQTIME_MAX SAADC_CH_CONFIG_TACQ_Max
110 #endif
111
112 #if NRF_SAADC_HAS_CONVTIME
113 /** @brief Symbol specifying maximum value of conversion time. */
114 #define NRF_SAADC_CONVTIME_MAX SAADC_CH_CONFIG_TCONV_Max
115 #endif
116
117 #if NRF_SAADC_HAS_LIN_CAL
118 /** @brief Symbol specifying maximum count of linearity calibration coefficients. */
119 #define NRF_SAADC_LIN_CAL_MAX_COUNT SAADC_TRIM_LINCALCOEFF_MaxCount
120
121 /** @brief Symbol specifying maximum value of linearity calibration coefficient. */
122 #define NRF_SAADC_LIN_CAL_MAX SAADC_TRIM_LINCALCOEFF_VAL_Max
123 #endif
124
125 /** @brief Resolution of the analog-to-digital converter. */
126 typedef enum
127 {
128 NRF_SAADC_RESOLUTION_8BIT = SAADC_RESOLUTION_VAL_8bit, ///< 8 bit resolution.
129 NRF_SAADC_RESOLUTION_10BIT = SAADC_RESOLUTION_VAL_10bit, ///< 10 bit resolution.
130 NRF_SAADC_RESOLUTION_12BIT = SAADC_RESOLUTION_VAL_12bit, ///< 12 bit resolution.
131 NRF_SAADC_RESOLUTION_14BIT = SAADC_RESOLUTION_VAL_14bit ///< 14 bit resolution.
132 } nrf_saadc_resolution_t;
133
134 #if NRF_SAADC_HAS_AIN_AS_PIN
135 /** @brief Analog input type. */
136 typedef uint32_t nrf_saadc_input_t;
137
138 /** @brief Symbol specifying disconnected analog input. */
139 #define NRF_SAADC_INPUT_DISABLED ((nrf_saadc_input_t)0)
140 #else
141 /** @brief Input selection for the analog-to-digital converter. */
142 typedef enum
143 {
144 NRF_SAADC_INPUT_DISABLED = SAADC_CH_PSELP_PSELP_NC, ///< Not connected.
145 NRF_SAADC_INPUT_AIN0 = SAADC_CH_PSELP_PSELP_AnalogInput0, ///< Analog input 0 (AIN0).
146 NRF_SAADC_INPUT_AIN1 = SAADC_CH_PSELP_PSELP_AnalogInput1, ///< Analog input 1 (AIN1).
147 NRF_SAADC_INPUT_AIN2 = SAADC_CH_PSELP_PSELP_AnalogInput2, ///< Analog input 2 (AIN2).
148 NRF_SAADC_INPUT_AIN3 = SAADC_CH_PSELP_PSELP_AnalogInput3, ///< Analog input 3 (AIN3).
149 NRF_SAADC_INPUT_AIN4 = SAADC_CH_PSELP_PSELP_AnalogInput4, ///< Analog input 4 (AIN4).
150 NRF_SAADC_INPUT_AIN5 = SAADC_CH_PSELP_PSELP_AnalogInput5, ///< Analog input 5 (AIN5).
151 NRF_SAADC_INPUT_AIN6 = SAADC_CH_PSELP_PSELP_AnalogInput6, ///< Analog input 6 (AIN6).
152 NRF_SAADC_INPUT_AIN7 = SAADC_CH_PSELP_PSELP_AnalogInput7, ///< Analog input 7 (AIN7).
153 #if defined(SAADC_CH_PSELP_PSELP_VDD) || defined(__NRFX_DOXYGEN__)
154 NRF_SAADC_INPUT_VDD = SAADC_CH_PSELP_PSELP_VDD, ///< VDD as input.
155 #endif
156 #if defined(SAADC_CH_PSELP_PSELP_VDDHDIV5) || defined(__NRFX_DOXYGEN__)
157 NRF_SAADC_INPUT_VDDHDIV5 = SAADC_CH_PSELP_PSELP_VDDHDIV5 ///< VDDH/5 as input.
158 #endif
159 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput8) || defined(__NRFX_DOXYGEN__)
160 NRF_SAADC_INPUT_AIN8 = SAADC_CH_PSELP_PSELP_AnalogInput8, ///< Analog input 8 (AIN8).
161 #endif
162 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput9) || defined(__NRFX_DOXYGEN__)
163 NRF_SAADC_INPUT_AIN9 = SAADC_CH_PSELP_PSELP_AnalogInput9, ///< Analog input 9 (AIN9).
164 #endif
165 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput10) || defined(__NRFX_DOXYGEN__)
166 NRF_SAADC_INPUT_AIN10 = SAADC_CH_PSELP_PSELP_AnalogInput10, ///< Analog input 10 (AIN10).
167 #endif
168 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput11) || defined(__NRFX_DOXYGEN__)
169 NRF_SAADC_INPUT_AIN11 = SAADC_CH_PSELP_PSELP_AnalogInput11, ///< Analog input 11 (AIN11).
170 #endif
171 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput12) || defined(__NRFX_DOXYGEN__)
172 NRF_SAADC_INPUT_AIN12 = SAADC_CH_PSELP_PSELP_AnalogInput12, ///< Analog input 12 (AIN12).
173 #endif
174 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput13) || defined(__NRFX_DOXYGEN__)
175 NRF_SAADC_INPUT_AIN13 = SAADC_CH_PSELP_PSELP_AnalogInput13, ///< Analog input 13 (AIN13).
176 #endif
177 } nrf_saadc_input_t;
178 #endif
179
180 /** @brief Analog-to-digital converter oversampling mode. */
181 typedef enum
182 {
183 NRF_SAADC_OVERSAMPLE_DISABLED = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass, ///< No oversampling.
184 NRF_SAADC_OVERSAMPLE_2X = SAADC_OVERSAMPLE_OVERSAMPLE_Over2x, ///< Oversample 2x.
185 NRF_SAADC_OVERSAMPLE_4X = SAADC_OVERSAMPLE_OVERSAMPLE_Over4x, ///< Oversample 4x.
186 NRF_SAADC_OVERSAMPLE_8X = SAADC_OVERSAMPLE_OVERSAMPLE_Over8x, ///< Oversample 8x.
187 NRF_SAADC_OVERSAMPLE_16X = SAADC_OVERSAMPLE_OVERSAMPLE_Over16x, ///< Oversample 16x.
188 NRF_SAADC_OVERSAMPLE_32X = SAADC_OVERSAMPLE_OVERSAMPLE_Over32x, ///< Oversample 32x.
189 NRF_SAADC_OVERSAMPLE_64X = SAADC_OVERSAMPLE_OVERSAMPLE_Over64x, ///< Oversample 64x.
190 NRF_SAADC_OVERSAMPLE_128X = SAADC_OVERSAMPLE_OVERSAMPLE_Over128x, ///< Oversample 128x.
191 NRF_SAADC_OVERSAMPLE_256X = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x ///< Oversample 256x.
192 } nrf_saadc_oversample_t;
193
194 #if NRF_SAADC_HAS_CH_CONFIG_RES
195 /** @brief Analog-to-digital converter channel resistor control. */
196 typedef enum
197 {
198 NRF_SAADC_RESISTOR_DISABLED = SAADC_CH_CONFIG_RESP_Bypass, ///< Bypass resistor ladder.
199 NRF_SAADC_RESISTOR_PULLDOWN = SAADC_CH_CONFIG_RESP_Pulldown, ///< Pull-down to GND.
200 NRF_SAADC_RESISTOR_PULLUP = SAADC_CH_CONFIG_RESP_Pullup, ///< Pull-up to VDD.
201 #if defined(SAADC_CH_CONFIG_RESP_VDD1_2) || defined(__NRFX_DOXYGEN__)
202 NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDD1_2, ///< Set input at VDD/2.
203 #endif
204 #if defined(SAADC_CH_CONFIG_RESP_VDDAO1V8div2)
205 NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDDAO1V8div2, ///< Set input at VDD/2.
206 #endif
207 } nrf_saadc_resistor_t;
208 #endif
209
210 /** @brief Gain factor of the analog-to-digital converter input. */
211 typedef enum
212 {
213 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_6) || defined(__NRFX_DOXYGEN__)
214 NRF_SAADC_GAIN1_6 = SAADC_CH_CONFIG_GAIN_Gain1_6, ///< Gain factor 1/6.
215 #endif
216 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_5) || defined(__NRFX_DOXYGEN__)
217 NRF_SAADC_GAIN1_5 = SAADC_CH_CONFIG_GAIN_Gain1_5, ///< Gain factor 1/5.
218 #endif
219 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_4) || defined(__NRFX_DOXYGEN__)
220 NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain1_4, ///< Gain factor 1/4.
221 #endif
222 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_3) || defined(__NRFX_DOXYGEN__)
223 NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain1_3, ///< Gain factor 1/3.
224 #endif
225 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_2) || defined(__NRFX_DOXYGEN__)
226 NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain1_2, ///< Gain factor 1/2.
227 #endif
228 #if defined(SAADC_CH_CONFIG_GAIN_Gain2_3) || defined(__NRFX_DOXYGEN__)
229 NRF_SAADC_GAIN2_3 = SAADC_CH_CONFIG_GAIN_Gain2_3, ///< Gain factor 2/3.
230 #endif
231 NRF_SAADC_GAIN1 = SAADC_CH_CONFIG_GAIN_Gain1, ///< Gain factor 1.
232 NRF_SAADC_GAIN2 = SAADC_CH_CONFIG_GAIN_Gain2, ///< Gain factor 2.
233 NRF_SAADC_GAIN4 = SAADC_CH_CONFIG_GAIN_Gain4, ///< Gain factor 4.
234 } nrf_saadc_gain_t;
235
236 /** @brief Reference selection for the analog-to-digital converter. */
237 typedef enum
238 {
239 #if defined(SAADC_CH_CONFIG_REFSEL_Internal) || defined(__NRFX_DOXYGEN__)
240 NRF_SAADC_REFERENCE_INTERNAL = SAADC_CH_CONFIG_REFSEL_Internal, ///< Internal reference.
241 #endif
242 #if defined(SAADC_CH_CONFIG_REFSEL_VDD1_4) || defined(__NRFX_DOXYGEN__)
243 NRF_SAADC_REFERENCE_VDD4 = SAADC_CH_CONFIG_REFSEL_VDD1_4 ///< VDD/4 as reference.
244 #endif
245 #if defined(SAADC_CH_CONFIG_REFSEL_External) || defined(__NRFX_DOXYGEN__)
246 NRF_SAADC_REFERENCE_EXTERNAL = SAADC_CH_CONFIG_REFSEL_External, ///< External reference.
247 #endif
248 } nrf_saadc_reference_t;
249
250 #if NRF_SAADC_HAS_ACQTIME_ENUM
251 /** @brief Analog-to-digital converter acquisition time. */
252 typedef enum
253 {
254 NRF_SAADC_ACQTIME_3US = SAADC_CH_CONFIG_TACQ_3us, ///< 3 us.
255 NRF_SAADC_ACQTIME_5US = SAADC_CH_CONFIG_TACQ_5us, ///< 5 us.
256 NRF_SAADC_ACQTIME_10US = SAADC_CH_CONFIG_TACQ_10us, ///< 10 us.
257 NRF_SAADC_ACQTIME_15US = SAADC_CH_CONFIG_TACQ_15us, ///< 15 us.
258 NRF_SAADC_ACQTIME_20US = SAADC_CH_CONFIG_TACQ_20us, ///< 20 us.
259 NRF_SAADC_ACQTIME_40US = SAADC_CH_CONFIG_TACQ_40us ///< 40 us.
260 } nrf_saadc_acqtime_t;
261 #else
262 typedef uint16_t nrf_saadc_acqtime_t;
263 #endif
264
265 /** @brief Analog-to-digital converter channel mode. */
266 typedef enum
267 {
268 NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE, ///< Single-ended mode. PSELN will be ignored, negative input to ADC shorted to GND.
269 NRF_SAADC_MODE_DIFFERENTIAL = SAADC_CH_CONFIG_MODE_Diff ///< Differential mode.
270 } nrf_saadc_mode_t;
271
272 /** @brief Analog-to-digital converter channel burst mode. */
273 typedef enum
274 {
275 NRF_SAADC_BURST_DISABLED = SAADC_CH_CONFIG_BURST_Disabled, ///< Burst mode is disabled (normal operation).
276 NRF_SAADC_BURST_ENABLED = SAADC_CH_CONFIG_BURST_Enabled ///< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.
277 } nrf_saadc_burst_t;
278
279 /** @brief Analog-to-digital converter tasks. */
280 typedef enum
281 {
282 NRF_SAADC_TASK_START = offsetof(NRF_SAADC_Type, TASKS_START), ///< Start the ADC and prepare the result buffer in RAM.
283 NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_STOP), ///< Stop the ADC and terminate any ongoing conversion.
284 NRF_SAADC_TASK_SAMPLE = offsetof(NRF_SAADC_Type, TASKS_SAMPLE), ///< Take one ADC sample. If scan is enabled, all channels are sampled.
285 NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration.
286 } nrf_saadc_task_t;
287
288 /** @brief Analog-to-digital converter events. */
289 typedef enum
290 {
291 NRF_SAADC_EVENT_STARTED = offsetof(NRF_SAADC_Type, EVENTS_STARTED), ///< The ADC has started.
292 #if NRF_SAADC_HAS_DMA_EVENTS
293 NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_DMA.END), ///< The ADC has filled up the result buffer.
294 #else
295 NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_END), ///< The ADC has filled up the result buffer.
296 #endif
297 NRF_SAADC_EVENT_DONE = offsetof(NRF_SAADC_Type, EVENTS_DONE), ///< A conversion task has been completed.
298 NRF_SAADC_EVENT_RESULTDONE = offsetof(NRF_SAADC_Type, EVENTS_RESULTDONE), ///< A result is ready to get transferred to RAM.
299 NRF_SAADC_EVENT_CALIBRATEDONE = offsetof(NRF_SAADC_Type, EVENTS_CALIBRATEDONE), ///< Calibration is complete.
300 NRF_SAADC_EVENT_STOPPED = offsetof(NRF_SAADC_Type, EVENTS_STOPPED), ///< The ADC has stopped.
301 NRF_SAADC_EVENT_CH0_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITH), ///< Last result is equal or above CH[0].LIMIT.HIGH.
302 NRF_SAADC_EVENT_CH0_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITL), ///< Last result is equal or below CH[0].LIMIT.LOW.
303 NRF_SAADC_EVENT_CH1_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITH), ///< Last result is equal or above CH[1].LIMIT.HIGH.
304 NRF_SAADC_EVENT_CH1_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITL), ///< Last result is equal or below CH[1].LIMIT.LOW.
305 NRF_SAADC_EVENT_CH2_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITH), ///< Last result is equal or above CH[2].LIMIT.HIGH.
306 NRF_SAADC_EVENT_CH2_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITL), ///< Last result is equal or below CH[2].LIMIT.LOW.
307 NRF_SAADC_EVENT_CH3_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITH), ///< Last result is equal or above CH[3].LIMIT.HIGH.
308 NRF_SAADC_EVENT_CH3_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITL), ///< Last result is equal or below CH[3].LIMIT.LOW.
309 NRF_SAADC_EVENT_CH4_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITH), ///< Last result is equal or above CH[4].LIMIT.HIGH.
310 NRF_SAADC_EVENT_CH4_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITL), ///< Last result is equal or below CH[4].LIMIT.LOW.
311 NRF_SAADC_EVENT_CH5_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITH), ///< Last result is equal or above CH[5].LIMIT.HIGH.
312 NRF_SAADC_EVENT_CH5_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITL), ///< Last result is equal or below CH[5].LIMIT.LOW.
313 NRF_SAADC_EVENT_CH6_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITH), ///< Last result is equal or above CH[6].LIMIT.HIGH.
314 NRF_SAADC_EVENT_CH6_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITL), ///< Last result is equal or below CH[6].LIMIT.LOW.
315 NRF_SAADC_EVENT_CH7_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITH), ///< Last result is equal or above CH[7].LIMIT.HIGH.
316 NRF_SAADC_EVENT_CH7_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL) ///< Last result is equal or below CH[7].LIMIT.LOW.
317 } nrf_saadc_event_t;
318
319 /** @brief Analog-to-digital converter interrupt masks. */
320 typedef enum
321 {
322 NRF_SAADC_INT_STARTED = SAADC_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event.
323 #if NRF_SAADC_HAS_DMA_EVENTS
324 NRF_SAADC_INT_END = SAADC_INTENSET_DMAEND_Msk, ///< Interrupt on EVENTS_END event.
325 #else
326 NRF_SAADC_INT_END = SAADC_INTENSET_END_Msk, ///< Interrupt on EVENTS_END event.
327 #endif
328 NRF_SAADC_INT_DONE = SAADC_INTENSET_DONE_Msk, ///< Interrupt on EVENTS_DONE event.
329 NRF_SAADC_INT_RESULTDONE = SAADC_INTENSET_RESULTDONE_Msk, ///< Interrupt on EVENTS_RESULTDONE event.
330 NRF_SAADC_INT_CALIBRATEDONE = SAADC_INTENSET_CALIBRATEDONE_Msk, ///< Interrupt on EVENTS_CALIBRATEDONE event.
331 NRF_SAADC_INT_STOPPED = SAADC_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event.
332 NRF_SAADC_INT_CH0LIMITH = SAADC_INTENSET_CH0LIMITH_Msk, ///< Interrupt on EVENTS_CH[0].LIMITH event.
333 NRF_SAADC_INT_CH0LIMITL = SAADC_INTENSET_CH0LIMITL_Msk, ///< Interrupt on EVENTS_CH[0].LIMITL event.
334 NRF_SAADC_INT_CH1LIMITH = SAADC_INTENSET_CH1LIMITH_Msk, ///< Interrupt on EVENTS_CH[1].LIMITH event.
335 NRF_SAADC_INT_CH1LIMITL = SAADC_INTENSET_CH1LIMITL_Msk, ///< Interrupt on EVENTS_CH[1].LIMITL event.
336 NRF_SAADC_INT_CH2LIMITH = SAADC_INTENSET_CH2LIMITH_Msk, ///< Interrupt on EVENTS_CH[2].LIMITH event.
337 NRF_SAADC_INT_CH2LIMITL = SAADC_INTENSET_CH2LIMITL_Msk, ///< Interrupt on EVENTS_CH[2].LIMITL event.
338 NRF_SAADC_INT_CH3LIMITH = SAADC_INTENSET_CH3LIMITH_Msk, ///< Interrupt on EVENTS_CH[3].LIMITH event.
339 NRF_SAADC_INT_CH3LIMITL = SAADC_INTENSET_CH3LIMITL_Msk, ///< Interrupt on EVENTS_CH[3].LIMITL event.
340 NRF_SAADC_INT_CH4LIMITH = SAADC_INTENSET_CH4LIMITH_Msk, ///< Interrupt on EVENTS_CH[4].LIMITH event.
341 NRF_SAADC_INT_CH4LIMITL = SAADC_INTENSET_CH4LIMITL_Msk, ///< Interrupt on EVENTS_CH[4].LIMITL event.
342 NRF_SAADC_INT_CH5LIMITH = SAADC_INTENSET_CH5LIMITH_Msk, ///< Interrupt on EVENTS_CH[5].LIMITH event.
343 NRF_SAADC_INT_CH5LIMITL = SAADC_INTENSET_CH5LIMITL_Msk, ///< Interrupt on EVENTS_CH[5].LIMITL event.
344 NRF_SAADC_INT_CH6LIMITH = SAADC_INTENSET_CH6LIMITH_Msk, ///< Interrupt on EVENTS_CH[6].LIMITH event.
345 NRF_SAADC_INT_CH6LIMITL = SAADC_INTENSET_CH6LIMITL_Msk, ///< Interrupt on EVENTS_CH[6].LIMITL event.
346 NRF_SAADC_INT_CH7LIMITH = SAADC_INTENSET_CH7LIMITH_Msk, ///< Interrupt on EVENTS_CH[7].LIMITH event.
347 NRF_SAADC_INT_CH7LIMITL = SAADC_INTENSET_CH7LIMITL_Msk, ///< Interrupt on EVENTS_CH[7].LIMITL event.
348 NRF_SAADC_INT_ALL = 0x7FFFFFFFUL ///< Mask of all interrupts.
349 } nrf_saadc_int_mask_t;
350
351 /** @brief Analog-to-digital converter value limit type. */
352 typedef enum
353 {
354 NRF_SAADC_LIMIT_LOW = 0, ///< Low limit type.
355 NRF_SAADC_LIMIT_HIGH = 1 ///< High limit type.
356 } nrf_saadc_limit_t;
357
358 /** @brief Type of a single ADC conversion result. */
359 typedef int16_t nrf_saadc_value_t;
360
361 /** @brief Analog-to-digital converter configuration structure. */
362 typedef struct
363 {
364 nrf_saadc_resolution_t resolution; ///< Resolution of samples.
365 nrf_saadc_oversample_t oversample; ///< Oversampling configuration.
366 nrf_saadc_value_t * buffer; ///< Pointer to sample buffer.
367 uint32_t buffer_size; ///< Size of the sample buffer.
368 } nrf_saadc_config_t;
369
370 /** @brief Analog-to-digital converter channel configuration structure. */
371 typedef struct
372 {
373 #if NRF_SAADC_HAS_CH_CONFIG_RES
374 nrf_saadc_resistor_t resistor_p; ///< Resistor value on positive input.
375 nrf_saadc_resistor_t resistor_n; ///< Resistor value on negative input.
376 #endif
377 nrf_saadc_gain_t gain; ///< Gain control value.
378 nrf_saadc_reference_t reference; ///< Reference control value.
379 nrf_saadc_acqtime_t acq_time; ///< Acquisition time.
380 nrf_saadc_mode_t mode; ///< SAADC mode. Single-ended or differential.
381 nrf_saadc_burst_t burst; ///< Burst mode configuration.
382 #if NRF_SAADC_HAS_CONVTIME
383 uint8_t conv_time; ///< Conversion time.
384 #endif
385 } nrf_saadc_channel_config_t;
386
387
388 /**
389 * @brief Function for triggering the specified SAADC task.
390 *
391 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
392 * @param[in] task SAADC task.
393 */
394 NRF_STATIC_INLINE void nrf_saadc_task_trigger(NRF_SAADC_Type * p_reg,
395 nrf_saadc_task_t task);
396
397 /**
398 * @brief Function for getting the address of the specified SAADC task register.
399 *
400 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
401 * @param[in] task SAADC task.
402 *
403 * @return Address of the specified SAADC task.
404 */
405 NRF_STATIC_INLINE uint32_t nrf_saadc_task_address_get(NRF_SAADC_Type const * p_reg,
406 nrf_saadc_task_t task);
407
408 /**
409 * @brief Function for retrieving the state of the SAADC event.
410 *
411 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
412 * @param[in] event Event to be checked.
413 *
414 * @retval true The event has been generated.
415 * @retval false The event has not been generated.
416 */
417 NRF_STATIC_INLINE bool nrf_saadc_event_check(NRF_SAADC_Type const * p_reg,
418 nrf_saadc_event_t event);
419
420 /**
421 * @brief Function for clearing the specific SAADC event.
422 *
423 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
424 * @param[in] event SAADC event.
425 */
426 NRF_STATIC_INLINE void nrf_saadc_event_clear(NRF_SAADC_Type * p_reg,
427 nrf_saadc_event_t event);
428
429 /**
430 * @brief Function for getting the address of the specified SAADC event register.
431 *
432 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
433 * @param[in] event SAADC event.
434 *
435 * @return Address of the specified SAADC event.
436 */
437 NRF_STATIC_INLINE uint32_t nrf_saadc_event_address_get(NRF_SAADC_Type const * p_reg,
438 nrf_saadc_event_t event);
439
440 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
441 /**
442 * @brief Function for setting the subscribe configuration for a given
443 * SAADC task.
444 *
445 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
446 * @param[in] task Task for which to set the configuration.
447 * @param[in] channel Channel through which to subscribe events.
448 */
449 NRF_STATIC_INLINE void nrf_saadc_subscribe_set(NRF_SAADC_Type * p_reg,
450 nrf_saadc_task_t task,
451 uint8_t channel);
452
453 /**
454 * @brief Function for clearing the subscribe configuration for a given
455 * SAADC task.
456 *
457 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
458 * @param[in] task Task for which to clear the configuration.
459 */
460 NRF_STATIC_INLINE void nrf_saadc_subscribe_clear(NRF_SAADC_Type * p_reg,
461 nrf_saadc_task_t task);
462
463 /**
464 * @brief Function for setting the publish configuration for a given
465 * SAADC event.
466 *
467 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
468 * @param[in] event Event for which to set the configuration.
469 * @param[in] channel Channel through which to publish the event.
470 */
471 NRF_STATIC_INLINE void nrf_saadc_publish_set(NRF_SAADC_Type * p_reg,
472 nrf_saadc_event_t event,
473 uint8_t channel);
474
475 /**
476 * @brief Function for clearing the publish configuration for a given
477 * SAADC event.
478 *
479 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
480 * @param[in] event Event for which to clear the configuration.
481 */
482 NRF_STATIC_INLINE void nrf_saadc_publish_clear(NRF_SAADC_Type * p_reg,
483 nrf_saadc_event_t event);
484 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
485
486 /**
487 * @brief Function for getting the SAADC channel monitoring limit events.
488 *
489 * @param[in] channel Channel number.
490 * @param[in] limit_type Low limit or high limit.
491 *
492 * @return The SAADC channel monitoring limit event.
493 */
494 NRF_STATIC_INLINE nrf_saadc_event_t nrf_saadc_limit_event_get(uint8_t channel,
495 nrf_saadc_limit_t limit_type);
496
497 /**
498 * @brief Function for configuring the input pins for the specified SAADC channel.
499 *
500 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
501 * @param[in] channel Channel number.
502 * @param[in] pselp Positive input.
503 * @param[in] pseln Negative input. Set to @ref NRF_SAADC_INPUT_DISABLED in single ended mode.
504 */
505 NRF_STATIC_INLINE void nrf_saadc_channel_input_set(NRF_SAADC_Type * p_reg,
506 uint8_t channel,
507 nrf_saadc_input_t pselp,
508 nrf_saadc_input_t pseln);
509
510 /**
511 * @brief Function for configuring the positive input pin for the specified SAADC channel.
512 *
513 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
514 * @param[in] channel Channel number.
515 * @param[in] pselp Positive input.
516 */
517 NRF_STATIC_INLINE void nrf_saadc_channel_pos_input_set(NRF_SAADC_Type * p_reg,
518 uint8_t channel,
519 nrf_saadc_input_t pselp);
520
521 /**
522 * @brief Function for setting the SAADC channel monitoring limits.
523 *
524 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
525 * @param[in] channel Channel number.
526 * @param[in] low Low limit.
527 * @param[in] high High limit.
528 */
529 NRF_STATIC_INLINE void nrf_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,
530 uint8_t channel,
531 int16_t low,
532 int16_t high);
533
534 /**
535 * @brief Function for setting the configuration of SAADC interrupts.
536 *
537 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
538 * @param[in] mask Interrupts configuration to be set.
539 */
540 NRF_STATIC_INLINE void nrf_saadc_int_set(NRF_SAADC_Type * p_reg, uint32_t mask);
541
542 /**
543 * @brief Function for enabling specified SAADC interrupts.
544 *
545 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
546 * @param[in] mask Mask of interrupts to be enabled.
547 */
548 NRF_STATIC_INLINE void nrf_saadc_int_enable(NRF_SAADC_Type * p_reg, uint32_t mask);
549
550 /**
551 * @brief Function for checking if the specified interrupts are enabled.
552 *
553 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
554 * @param[in] mask Mask of interrupts to be checked.
555 *
556 * @return Mask of enabled interrupts.
557 */
558 NRF_STATIC_INLINE uint32_t nrf_saadc_int_enable_check(NRF_SAADC_Type const * p_reg, uint32_t mask);
559
560 /**
561 * @brief Function for disabling specified interrupts.
562 *
563 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
564 * @param[in] mask Mask of interrupts to be disabled.
565 */
566 NRF_STATIC_INLINE void nrf_saadc_int_disable(NRF_SAADC_Type * p_reg, uint32_t mask);
567
568 /**
569 * @brief Function for generating masks for SAADC channel limit interrupts.
570 *
571 * @param[in] channel SAADC channel number.
572 * @param[in] limit_type Limit type.
573 *
574 * @return Interrupt mask.
575 */
576 NRF_STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel,
577 nrf_saadc_limit_t limit_type);
578
579 /**
580 * @brief Function for checking whether the SAADC is busy.
581 *
582 * This function checks whether the analog-to-digital converter is busy with a conversion.
583 *
584 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
585 *
586 * @retval true The SAADC is busy.
587 * @retval false The SAADC is not busy.
588 */
589 NRF_STATIC_INLINE bool nrf_saadc_busy_check(NRF_SAADC_Type const * p_reg);
590
591 /**
592 * @brief Function for enabling the SAADC.
593 *
594 * The analog-to-digital converter must be enabled before use.
595 *
596 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
597 */
598 NRF_STATIC_INLINE void nrf_saadc_enable(NRF_SAADC_Type * p_reg);
599
600 /**
601 * @brief Function for disabling the SAADC.
602 *
603 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
604 */
605 NRF_STATIC_INLINE void nrf_saadc_disable(NRF_SAADC_Type * p_reg);
606
607 /**
608 * @brief Function for checking if the SAADC is enabled.
609 *
610 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
611 *
612 * @retval true The SAADC is enabled.
613 * @retval false The SAADC is not enabled.
614 */
615 NRF_STATIC_INLINE bool nrf_saadc_enable_check(NRF_SAADC_Type const * p_reg);
616
617 /**
618 * @brief Function for initializing the SAADC result buffer.
619 *
620 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
621 * @param[in] p_buffer Pointer to the result buffer.
622 * @param[in] size Size of the buffer (in 16-bit samples).
623 */
624 NRF_STATIC_INLINE void nrf_saadc_buffer_init(NRF_SAADC_Type * p_reg,
625 nrf_saadc_value_t * p_buffer,
626 uint32_t size);
627
628 /**
629 * @brief Function for setting the SAADC result buffer pointer.
630 *
631 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
632 * @param[in] p_buffer Pointer to the result buffer.
633 */
634 NRF_STATIC_INLINE void nrf_saadc_buffer_pointer_set(NRF_SAADC_Type * p_reg,
635 nrf_saadc_value_t * p_buffer);
636
637 /**
638 * @brief Function for getting the SAADC result buffer pointer.
639 *
640 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
641 *
642 * @return Pointer to the result buffer.
643 */
644 NRF_STATIC_INLINE nrf_saadc_value_t * nrf_saadc_buffer_pointer_get(NRF_SAADC_Type const * p_reg);
645
646 /**
647 * @brief Function for getting the number of samples written to the result
648 * buffer since the previous START task.
649 *
650 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
651 *
652 * @return Number of 16-bit samples written to the buffer.
653 */
654 NRF_STATIC_INLINE uint16_t nrf_saadc_amount_get(NRF_SAADC_Type const * p_reg);
655
656 /**
657 * @brief Function for setting the SAADC sample resolution.
658 *
659 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
660 * @param[in] resolution Bit resolution.
661 */
662 NRF_STATIC_INLINE void nrf_saadc_resolution_set(NRF_SAADC_Type * p_reg,
663 nrf_saadc_resolution_t resolution);
664
665 /**
666 * @brief Function for getting the SAADC sample resolution.
667 *
668 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
669 *
670 * @return Sample resolution.
671 */
672 NRF_STATIC_INLINE nrf_saadc_resolution_t nrf_saadc_resolution_get(NRF_SAADC_Type const * p_reg);
673
674 /**
675 * @brief Function for configuring the oversampling feature.
676 *
677 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
678 * @param[in] oversample Oversampling mode.
679 */
680 NRF_STATIC_INLINE void nrf_saadc_oversample_set(NRF_SAADC_Type * p_reg,
681 nrf_saadc_oversample_t oversample);
682
683 /**
684 * @brief Function for getting the oversampling feature configuration.
685 *
686 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
687 *
688 * @return Oversampling configuration.
689 */
690 NRF_STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(NRF_SAADC_Type const * p_reg);
691
692 /**
693 * @brief Function for getting the sample count needed for one averaged result for a given
694 * oversampling configuration.
695 *
696 * @param[in] oversample Oversampling configuration.
697 *
698 * @return Sample count.
699 */
700 NRF_STATIC_INLINE uint32_t nrf_saadc_oversample_sample_count_get(nrf_saadc_oversample_t oversample);
701
702 /**
703 * @brief Function for enabling the continuous sampling.
704 *
705 * This function configures the SAADC internal timer to automatically take new samples at a fixed
706 * sample rate. Trigger the START task to begin continuous sampling. To stop the sampling, trigger
707 * the STOP task.
708 *
709 * @note The internal timer can only be used when a single input channel is enabled.
710 *
711 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
712 * @param[in] cc Capture and compare value. Sample rate is 16 MHz/cc.
713 * Valid @c CC range is from 80 to 2047.
714 */
715 NRF_STATIC_INLINE void nrf_saadc_continuous_mode_enable(NRF_SAADC_Type * p_reg,
716 uint16_t cc);
717
718 /**
719 * @brief Function for checking if the continuous sampling is enabled.
720 *
721 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
722 *
723 * @retval true The continuous sampling is enabled.
724 * @retval false The continuous sampling is disabled.
725 */
726 NRF_STATIC_INLINE bool nrf_saadc_continuous_mode_enable_check(NRF_SAADC_Type const * p_reg);
727
728 /**
729 * @brief Function for disabling the continuous sampling.
730 *
731 * New samples can still be acquired by manually triggering the SAMPLE task or by PPI.
732 *
733 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
734 */
735 NRF_STATIC_INLINE void nrf_saadc_continuous_mode_disable(NRF_SAADC_Type * p_reg);
736
737 #if NRF_SAADC_HAS_LIN_CAL
738 /**
739 * @brief Function for setting linearity calibration coefficient.
740 *
741 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
742 * @param[in] index Coefficient number.
743 * @param[in] coeff Value of the coefficient.
744 */
745 NRF_STATIC_INLINE void nrf_saadc_linearity_calibration_coeff_set(NRF_SAADC_Type * p_reg,
746 uint8_t index,
747 uint32_t coeff);
748
749 /**
750 * @brief Function for getting linearity calibration coefficient.
751 *
752 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
753 * @param[in] index Coefficient number.
754 *
755 * @return Value of the coefficient.
756 */
757 NRF_STATIC_INLINE uint32_t nrf_saadc_linearity_calibration_coeff_get(NRF_SAADC_Type const * p_reg,
758 uint8_t index);
759 #endif
760
761 /**
762 * @brief Function for initializing the SAADC channel.
763 *
764 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
765 * @param[in] channel Channel number.
766 * @param[in] config Pointer to the channel configuration structure.
767 */
768 NRF_STATIC_INLINE void nrf_saadc_channel_init(NRF_SAADC_Type * p_reg,
769 uint8_t channel,
770 nrf_saadc_channel_config_t const * config);
771
772 /**
773 * @brief Function for configuring the burst mode for the specified channel.
774 *
775 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
776 * @param[in] channel Channel number.
777 * @param[in] burst Burst mode setting.
778 */
779 NRF_STATIC_INLINE void nrf_saadc_burst_set(NRF_SAADC_Type * p_reg,
780 uint8_t channel,
781 nrf_saadc_burst_t burst);
782
783 /**
784 * @brief Function for getting the minimum value of the conversion result.
785 *
786 * The minimum value of the conversion result depends on the configured resolution.
787 *
788 * @param[in] resolution Bit resolution.
789 *
790 * @return Minimum value of the conversion result.
791 */
792 NRF_STATIC_INLINE nrf_saadc_value_t nrf_saadc_value_min_get(nrf_saadc_resolution_t resolution);
793
794 /**
795 * @brief Function for getting the maximum value of the conversion result.
796 *
797 * The maximum value of the conversion result depends on the configured resolution.
798 *
799 * @param[in] resolution Bit resolution.
800 *
801 * @return Maximum value of the conversion result.
802 */
803 NRF_STATIC_INLINE nrf_saadc_value_t nrf_saadc_value_max_get(nrf_saadc_resolution_t resolution);
804
805 #ifndef NRF_DECLARE_ONLY
806
nrf_saadc_task_trigger(NRF_SAADC_Type * p_reg,nrf_saadc_task_t task)807 NRF_STATIC_INLINE void nrf_saadc_task_trigger(NRF_SAADC_Type * p_reg, nrf_saadc_task_t task)
808 {
809 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
810 }
811
nrf_saadc_task_address_get(NRF_SAADC_Type const * p_reg,nrf_saadc_task_t task)812 NRF_STATIC_INLINE uint32_t nrf_saadc_task_address_get(NRF_SAADC_Type const * p_reg,
813 nrf_saadc_task_t task)
814 {
815 return (uint32_t)((uint8_t *)p_reg + (uint32_t)task);
816 }
817
nrf_saadc_event_check(NRF_SAADC_Type const * p_reg,nrf_saadc_event_t event)818 NRF_STATIC_INLINE bool nrf_saadc_event_check(NRF_SAADC_Type const * p_reg, nrf_saadc_event_t event)
819 {
820 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
821 }
822
nrf_saadc_event_clear(NRF_SAADC_Type * p_reg,nrf_saadc_event_t event)823 NRF_STATIC_INLINE void nrf_saadc_event_clear(NRF_SAADC_Type * p_reg, nrf_saadc_event_t event)
824 {
825 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
826 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
827 }
828
nrf_saadc_event_address_get(NRF_SAADC_Type const * p_reg,nrf_saadc_event_t event)829 NRF_STATIC_INLINE uint32_t nrf_saadc_event_address_get(NRF_SAADC_Type const * p_reg,
830 nrf_saadc_event_t event)
831 {
832 return (uint32_t )((uint8_t *)p_reg + (uint32_t)event);
833 }
834
835 #if defined(DPPI_PRESENT)
nrf_saadc_subscribe_set(NRF_SAADC_Type * p_reg,nrf_saadc_task_t task,uint8_t channel)836 NRF_STATIC_INLINE void nrf_saadc_subscribe_set(NRF_SAADC_Type * p_reg,
837 nrf_saadc_task_t task,
838 uint8_t channel)
839 {
840 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
841 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
842 }
843
nrf_saadc_subscribe_clear(NRF_SAADC_Type * p_reg,nrf_saadc_task_t task)844 NRF_STATIC_INLINE void nrf_saadc_subscribe_clear(NRF_SAADC_Type * p_reg, nrf_saadc_task_t task)
845 {
846 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
847 }
848
nrf_saadc_publish_set(NRF_SAADC_Type * p_reg,nrf_saadc_event_t event,uint8_t channel)849 NRF_STATIC_INLINE void nrf_saadc_publish_set(NRF_SAADC_Type * p_reg,
850 nrf_saadc_event_t event,
851 uint8_t channel)
852 {
853 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
854 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
855 }
856
nrf_saadc_publish_clear(NRF_SAADC_Type * p_reg,nrf_saadc_event_t event)857 NRF_STATIC_INLINE void nrf_saadc_publish_clear(NRF_SAADC_Type * p_reg, nrf_saadc_event_t event)
858 {
859 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
860 }
861 #endif // defined(DPPI_PRESENT)
862
nrf_saadc_limit_event_get(uint8_t channel,nrf_saadc_limit_t limit_type)863 NRF_STATIC_INLINE nrf_saadc_event_t nrf_saadc_limit_event_get(uint8_t channel,
864 nrf_saadc_limit_t limit_type)
865 {
866 if (limit_type == NRF_SAADC_LIMIT_HIGH)
867 {
868 return (nrf_saadc_event_t)NRFX_OFFSETOF(NRF_SAADC_Type, EVENTS_CH[channel].LIMITH);
869 }
870 else
871 {
872 return (nrf_saadc_event_t)NRFX_OFFSETOF(NRF_SAADC_Type, EVENTS_CH[channel].LIMITL);
873 }
874 }
875
nrf_saadc_channel_input_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_input_t pselp,nrf_saadc_input_t pseln)876 NRF_STATIC_INLINE void nrf_saadc_channel_input_set(NRF_SAADC_Type * p_reg,
877 uint8_t channel,
878 nrf_saadc_input_t pselp,
879 nrf_saadc_input_t pseln)
880 {
881 #if NRF_SAADC_HAS_AIN_AS_PIN
882 p_reg->CH[channel].PSELN = (NRF_PIN_NUMBER_TO_PIN(pseln) << SAADC_CH_PSELP_PIN_Pos)
883 | (NRF_PIN_NUMBER_TO_PORT(pseln) << SAADC_CH_PSELP_PORT_Pos)
884 | (SAADC_CH_PSELP_CONNECT_AnalogInput << SAADC_CH_PSELP_CONNECT_Pos);
885 p_reg->CH[channel].PSELP = (NRF_PIN_NUMBER_TO_PIN(pselp) << SAADC_CH_PSELP_PIN_Pos)
886 | (NRF_PIN_NUMBER_TO_PORT(pselp) << SAADC_CH_PSELP_PORT_Pos)
887 | (SAADC_CH_PSELP_CONNECT_AnalogInput << SAADC_CH_PSELP_CONNECT_Pos);
888 #else
889 p_reg->CH[channel].PSELN = pseln;
890 p_reg->CH[channel].PSELP = pselp;
891 #endif
892 }
893
nrf_saadc_channel_pos_input_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_input_t pselp)894 NRF_STATIC_INLINE void nrf_saadc_channel_pos_input_set(NRF_SAADC_Type * p_reg,
895 uint8_t channel,
896 nrf_saadc_input_t pselp)
897 {
898 #if NRF_SAADC_HAS_AIN_AS_PIN
899 p_reg->CH[channel].PSELP = (NRF_PIN_NUMBER_TO_PIN(pselp) << SAADC_CH_PSELP_PIN_Pos)
900 | (NRF_PIN_NUMBER_TO_PORT(pselp) << SAADC_CH_PSELP_PORT_Pos)
901 | (SAADC_CH_PSELP_CONNECT_AnalogInput << SAADC_CH_PSELP_CONNECT_Pos);
902 #else
903 p_reg->CH[channel].PSELP = pselp;
904 #endif
905 }
906
nrf_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,uint8_t channel,int16_t low,int16_t high)907 NRF_STATIC_INLINE void nrf_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,
908 uint8_t channel,
909 int16_t low,
910 int16_t high)
911 {
912 p_reg->CH[channel].LIMIT = (
913 (((uint32_t) low << SAADC_CH_LIMIT_LOW_Pos) & SAADC_CH_LIMIT_LOW_Msk)
914 | (((uint32_t) high << SAADC_CH_LIMIT_HIGH_Pos) & SAADC_CH_LIMIT_HIGH_Msk));
915 }
916
nrf_saadc_int_set(NRF_SAADC_Type * p_reg,uint32_t mask)917 NRF_STATIC_INLINE void nrf_saadc_int_set(NRF_SAADC_Type * p_reg, uint32_t mask)
918 {
919 p_reg->INTEN = mask;
920 }
921
nrf_saadc_int_enable(NRF_SAADC_Type * p_reg,uint32_t mask)922 NRF_STATIC_INLINE void nrf_saadc_int_enable(NRF_SAADC_Type * p_reg, uint32_t mask)
923 {
924 p_reg->INTENSET = mask;
925 }
926
nrf_saadc_int_enable_check(NRF_SAADC_Type const * p_reg,uint32_t mask)927 NRF_STATIC_INLINE uint32_t nrf_saadc_int_enable_check(NRF_SAADC_Type const * p_reg, uint32_t mask)
928 {
929 return p_reg->INTENSET & mask;
930 }
931
nrf_saadc_int_disable(NRF_SAADC_Type * p_reg,uint32_t mask)932 NRF_STATIC_INLINE void nrf_saadc_int_disable(NRF_SAADC_Type * p_reg, uint32_t mask)
933 {
934 p_reg->INTENCLR = mask;
935 }
936
nrf_saadc_limit_int_get(uint8_t channel,nrf_saadc_limit_t limit_type)937 NRF_STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel,
938 nrf_saadc_limit_t limit_type)
939 {
940 NRFX_ASSERT(channel < SAADC_CH_NUM);
941 uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ?
942 NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH;
943 return mask << (channel * 2);
944 }
945
nrf_saadc_busy_check(NRF_SAADC_Type const * p_reg)946 NRF_STATIC_INLINE bool nrf_saadc_busy_check(NRF_SAADC_Type const * p_reg)
947 {
948 return (p_reg->STATUS == (SAADC_STATUS_STATUS_Busy << SAADC_STATUS_STATUS_Pos));
949 }
950
nrf_saadc_enable(NRF_SAADC_Type * p_reg)951 NRF_STATIC_INLINE void nrf_saadc_enable(NRF_SAADC_Type * p_reg)
952 {
953 p_reg->ENABLE = (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos);
954 }
955
nrf_saadc_disable(NRF_SAADC_Type * p_reg)956 NRF_STATIC_INLINE void nrf_saadc_disable(NRF_SAADC_Type * p_reg)
957 {
958 p_reg->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos);
959 }
960
nrf_saadc_enable_check(NRF_SAADC_Type const * p_reg)961 NRF_STATIC_INLINE bool nrf_saadc_enable_check(NRF_SAADC_Type const * p_reg)
962 {
963 return (p_reg->ENABLE == (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos));
964 }
965
nrf_saadc_buffer_init(NRF_SAADC_Type * p_reg,nrf_saadc_value_t * p_buffer,uint32_t size)966 NRF_STATIC_INLINE void nrf_saadc_buffer_init(NRF_SAADC_Type * p_reg,
967 nrf_saadc_value_t * p_buffer,
968 uint32_t size)
969 {
970 #if NRF_SAADC_HAS_DMA_REG
971 p_reg->DMA.PTR = (uint32_t)p_buffer;
972 p_reg->DMA.MAXCNT = size;
973 #else
974 p_reg->RESULT.PTR = (uint32_t)p_buffer;
975 p_reg->RESULT.MAXCNT = size;
976 #endif
977 }
978
nrf_saadc_buffer_pointer_set(NRF_SAADC_Type * p_reg,nrf_saadc_value_t * p_buffer)979 NRF_STATIC_INLINE void nrf_saadc_buffer_pointer_set(NRF_SAADC_Type * p_reg,
980 nrf_saadc_value_t * p_buffer)
981 {
982 #if NRF_SAADC_HAS_DMA_REG
983 p_reg->DMA.PTR = (uint32_t)p_buffer;
984 #else
985 p_reg->RESULT.PTR = (uint32_t)p_buffer;
986 #endif
987 }
988
nrf_saadc_buffer_pointer_get(NRF_SAADC_Type const * p_reg)989 NRF_STATIC_INLINE nrf_saadc_value_t * nrf_saadc_buffer_pointer_get(NRF_SAADC_Type const * p_reg)
990 {
991 #if NRF_SAADC_HAS_DMA_REG
992 return (nrf_saadc_value_t *)p_reg->DMA.PTR;
993 #else
994 return (nrf_saadc_value_t *)p_reg->RESULT.PTR;
995 #endif
996 }
997
nrf_saadc_amount_get(NRF_SAADC_Type const * p_reg)998 NRF_STATIC_INLINE uint16_t nrf_saadc_amount_get(NRF_SAADC_Type const * p_reg)
999 {
1000 #if NRF_SAADC_HAS_DMA_REG
1001 return (uint16_t)p_reg->DMA.AMOUNT;
1002 #else
1003 return (uint16_t)p_reg->RESULT.AMOUNT;
1004 #endif
1005 }
1006
nrf_saadc_resolution_set(NRF_SAADC_Type * p_reg,nrf_saadc_resolution_t resolution)1007 NRF_STATIC_INLINE void nrf_saadc_resolution_set(NRF_SAADC_Type * p_reg,
1008 nrf_saadc_resolution_t resolution)
1009 {
1010 p_reg->RESOLUTION = resolution;
1011 }
1012
nrf_saadc_resolution_get(NRF_SAADC_Type const * p_reg)1013 NRF_STATIC_INLINE nrf_saadc_resolution_t nrf_saadc_resolution_get(NRF_SAADC_Type const * p_reg)
1014 {
1015 return (nrf_saadc_resolution_t)p_reg->RESOLUTION;
1016 }
1017
nrf_saadc_oversample_set(NRF_SAADC_Type * p_reg,nrf_saadc_oversample_t oversample)1018 NRF_STATIC_INLINE void nrf_saadc_oversample_set(NRF_SAADC_Type * p_reg,
1019 nrf_saadc_oversample_t oversample)
1020 {
1021 p_reg->OVERSAMPLE = oversample;
1022 }
1023
nrf_saadc_oversample_get(NRF_SAADC_Type const * p_reg)1024 NRF_STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(NRF_SAADC_Type const * p_reg)
1025 {
1026 return (nrf_saadc_oversample_t)p_reg->OVERSAMPLE;
1027 }
1028
nrf_saadc_oversample_sample_count_get(nrf_saadc_oversample_t oversample)1029 NRF_STATIC_INLINE uint32_t nrf_saadc_oversample_sample_count_get(nrf_saadc_oversample_t oversample)
1030 {
1031 return (1 << (uint32_t)oversample);
1032 }
1033
nrf_saadc_continuous_mode_enable(NRF_SAADC_Type * p_reg,uint16_t cc)1034 NRF_STATIC_INLINE void nrf_saadc_continuous_mode_enable(NRF_SAADC_Type * p_reg, uint16_t cc)
1035 {
1036 NRFX_ASSERT((cc >= 80) && (cc <= 2047));
1037 p_reg->SAMPLERATE = (SAADC_SAMPLERATE_MODE_Timers << SAADC_SAMPLERATE_MODE_Pos)
1038 | ((uint32_t)cc << SAADC_SAMPLERATE_CC_Pos);
1039 }
1040
nrf_saadc_continuous_mode_enable_check(NRF_SAADC_Type const * p_reg)1041 NRF_STATIC_INLINE bool nrf_saadc_continuous_mode_enable_check(NRF_SAADC_Type const * p_reg)
1042 {
1043 return (bool)((p_reg->SAMPLERATE & SAADC_SAMPLERATE_MODE_Msk)
1044 == (SAADC_SAMPLERATE_MODE_Timers << SAADC_SAMPLERATE_MODE_Pos));
1045 }
1046
nrf_saadc_continuous_mode_disable(NRF_SAADC_Type * p_reg)1047 NRF_STATIC_INLINE void nrf_saadc_continuous_mode_disable(NRF_SAADC_Type * p_reg)
1048 {
1049 p_reg->SAMPLERATE = SAADC_SAMPLERATE_MODE_Task << SAADC_SAMPLERATE_MODE_Pos;
1050 }
1051
1052 #if NRF_SAADC_HAS_LIN_CAL
nrf_saadc_linearity_calibration_coeff_set(NRF_SAADC_Type * p_reg,uint8_t index,uint32_t coeff)1053 NRF_STATIC_INLINE void nrf_saadc_linearity_calibration_coeff_set(NRF_SAADC_Type * p_reg,
1054 uint8_t index,
1055 uint32_t coeff)
1056 {
1057 NRFX_ASSERT(index < NRF_SAADC_LIN_CAL_MAX_COUNT);
1058 NRFX_ASSERT(coeff <= NRF_SAADC_LIN_CAL_MAX);
1059 p_reg->TRIM.LINCALCOEFF[index] = coeff;
1060 }
1061
nrf_saadc_linearity_calibration_coeff_get(NRF_SAADC_Type const * p_reg,uint8_t index)1062 NRF_STATIC_INLINE uint32_t nrf_saadc_linearity_calibration_coeff_get(NRF_SAADC_Type const * p_reg,
1063 uint8_t index)
1064 {
1065 NRFX_ASSERT(index < NRF_SAADC_LIN_CAL_MAX_COUNT);
1066 return p_reg->TRIM.LINCALCOEFF[index];
1067 }
1068 #endif
1069
nrf_saadc_channel_init(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_channel_config_t const * config)1070 NRF_STATIC_INLINE void nrf_saadc_channel_init(NRF_SAADC_Type * p_reg,
1071 uint8_t channel,
1072 nrf_saadc_channel_config_t const * config)
1073 {
1074 #if !NRF_SAADC_HAS_ACQTIME_ENUM
1075 NRFX_ASSERT(config->acq_time <= NRF_SAADC_ACQTIME_MAX);
1076 #endif
1077 #if NRF_SAADC_HAS_CONVTIME
1078 NRFX_ASSERT(config->conv_time <= NRF_SAADC_CONVTIME_MAX);
1079 #endif
1080 p_reg->CH[channel].CONFIG =
1081 ((config->gain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk)
1082 | ((config->reference << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk)
1083 | ((config->acq_time << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk)
1084 #if NRF_SAADC_HAS_CH_CONTROL_RES
1085 | ((config->resistor_p << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk)
1086 | ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk)
1087 #endif
1088 #if NRF_SAADC_HAS_CONVTIME
1089 | ((config->conv_time << SAADC_CH_CONFIG_TCONV_Pos) & SAADC_CH_CONFIG_TCONV_Msk)
1090 #endif
1091 | ((config->mode << SAADC_CH_CONFIG_MODE_Pos) & SAADC_CH_CONFIG_MODE_Msk)
1092 | ((config->burst << SAADC_CH_CONFIG_BURST_Pos) & SAADC_CH_CONFIG_BURST_Msk);
1093 }
1094
nrf_saadc_burst_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_burst_t burst)1095 NRF_STATIC_INLINE void nrf_saadc_burst_set(NRF_SAADC_Type * p_reg,
1096 uint8_t channel,
1097 nrf_saadc_burst_t burst)
1098 {
1099 p_reg->CH[channel].CONFIG = (p_reg->CH[channel].CONFIG & ~SAADC_CH_CONFIG_BURST_Msk) |
1100 (burst << SAADC_CH_CONFIG_BURST_Pos);
1101 }
1102
nrf_saadc_value_min_get(nrf_saadc_resolution_t resolution)1103 NRF_STATIC_INLINE nrf_saadc_value_t nrf_saadc_value_min_get(nrf_saadc_resolution_t resolution)
1104 {
1105 uint8_t res_bits = 0;
1106 switch (resolution)
1107 {
1108 case NRF_SAADC_RESOLUTION_8BIT:
1109 res_bits = 8;
1110 break;
1111 case NRF_SAADC_RESOLUTION_10BIT:
1112 res_bits = 10;
1113 break;
1114 case NRF_SAADC_RESOLUTION_12BIT:
1115 res_bits = 12;
1116 break;
1117 case NRF_SAADC_RESOLUTION_14BIT:
1118 res_bits = 14;
1119 break;
1120 default:
1121 NRFX_ASSERT(false);
1122 }
1123 return (nrf_saadc_value_t)(-(1 << res_bits));
1124 }
1125
nrf_saadc_value_max_get(nrf_saadc_resolution_t resolution)1126 NRF_STATIC_INLINE nrf_saadc_value_t nrf_saadc_value_max_get(nrf_saadc_resolution_t resolution)
1127 {
1128 uint8_t res_bits = 0;
1129 switch (resolution)
1130 {
1131 case NRF_SAADC_RESOLUTION_8BIT:
1132 res_bits = 8;
1133 break;
1134 case NRF_SAADC_RESOLUTION_10BIT:
1135 res_bits = 10;
1136 break;
1137 case NRF_SAADC_RESOLUTION_12BIT:
1138 res_bits = 12;
1139 break;
1140 case NRF_SAADC_RESOLUTION_14BIT:
1141 res_bits = 14;
1142 break;
1143 default:
1144 NRFX_ASSERT(false);
1145 }
1146 return (nrf_saadc_value_t)((1 << res_bits) - 1);
1147 }
1148
1149 #endif // NRF_DECLARE_ONLY
1150
1151 /** @} */
1152
1153 #ifdef __cplusplus
1154 }
1155 #endif
1156
1157 #endif // NRF_SAADC_H_
1158
