1 /*
2 * Copyright (c) 2015 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_SAADC_H_
35 #define NRF_SAADC_H_
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_saadc_hal SAADC HAL
45 * @{
46 * @ingroup nrf_saadc
47 * @brief Hardware access layer for managing the SAADC peripheral.
48 */
49
50 /** @brief Symbol specifying the offset of interrupt bitmask for limits of all channels. */
51 #define NRF_SAADC_LIMITS_INT_OFFSET \
52 NRFX_MIN(SAADC_INTENSET_CH0LIMITH_Pos, SAADC_INTENSET_CH0LIMITL_Pos)
53
54 /** @brief Symbol specifying number of LIMIT events per channel. */
55 #define NRF_SAADC_LIMITS_PER_CHANNEL (2)
56
57 /** @brief Symbol specifying the interrupt bitmask for limits of all channels. */
58 #define NRF_SAADC_ALL_CHANNELS_LIMITS_INT_MASK \
59 ((uint32_t)(NRFX_BIT_MASK(SAADC_CH_NUM * NRF_SAADC_LIMITS_PER_CHANNEL) \
60 << NRF_SAADC_LIMITS_INT_OFFSET))
61
62 #if defined(SAADC_CH_CONFIG_TACQ_3us) || defined(__NRFX_DOXYGEN__)
63 /** @brief Symbol indicating whether the configuration of acquisition time using predefined values is present. */
64 #define NRF_SAADC_HAS_ACQTIME_ENUM 1
65 #else
66 #define NRF_SAADC_HAS_ACQTIME_ENUM 0
67 #endif
68
69 #if defined(SAADC_CH_CONFIG_TCONV_Msk) || defined(__NRFX_DOXYGEN__)
70 /** @brief Symbol indicating whether the configuration of conversion time is present. */
71 #define NRF_SAADC_HAS_CONVTIME 1
72 #else
73 #define NRF_SAADC_HAS_CONVTIME 0
74 #endif
75
76 #if defined(SAADC_TRIM_LINCALCOEFF_VAL_Msk) || defined(__NRFX_DOXYGEN__)
77 /** @brief Symbol indicating whether the configuration of linearity calibration coefficients is present. */
78 #define NRF_SAADC_HAS_LIN_CAL 1
79 #else
80 #define NRF_SAADC_HAS_LIN_CAL 0
81 #endif
82
83 #if defined(SAADC_CH_PSELP_PIN_Msk) || defined(__NRFX_DOXYGEN__)
84 /** @brief Symbol indicating whether configuration of analog input using pin number is present. */
85 #define NRF_SAADC_HAS_AIN_AS_PIN 1
86 #else
87 #define NRF_SAADC_HAS_AIN_AS_PIN 0
88 #endif
89
90 #if defined(SAADC_CH_CONFIG_RESP_Msk) || defined(__NRFX_DOXYGEN__)
91 /** @brief Symbol indicating whether SAADC channel resistor control is present. */
92 #define NRF_SAADC_HAS_CH_CONFIG_RES 1
93 #else
94 #define NRF_SAADC_HAS_CH_CONFIG_RES 0
95 #endif
96
97 #if defined(SAADC_CH_PSELP_INTERNAL_Msk) || defined(__NRFX_DOXYGEN__)
98 /** @brief Symbol indicating whether SAADC positive internal inputs for pin number configurations are present. */
99 #define NRF_SAADC_HAS_CH_PSELP_INTERNAL 1
100 #else
101 #define NRF_SAADC_HAS_CH_PSELP_INTERNAL 0
102 #endif
103
104 #if defined(SAADC_CH_PSELN_INTERNAL_Msk) || defined(__NRFX_DOXYGEN__)
105 /** @brief Symbol indicating whether SAADC negative internal inputs for pin number configurations are present. */
106 #define NRF_SAADC_HAS_CH_PSELN_INTERNAL 1
107 #else
108 #define NRF_SAADC_HAS_CH_PSELN_INTERNAL 0
109 #endif
110
111 #if !NRF_SAADC_HAS_ACQTIME_ENUM
112 /** @brief Maximum value of acquire time. */
113 #define NRF_SAADC_ACQTIME_MAX SAADC_CH_CONFIG_TACQ_Max
114 #endif
115
116 #if NRF_SAADC_HAS_CONVTIME
117 /** @brief Symbol specifying maximum value of conversion time. */
118 #define NRF_SAADC_CONVTIME_MAX SAADC_CH_CONFIG_TCONV_Max
119 #endif
120
121 #if NRF_SAADC_HAS_LIN_CAL
122 /** @brief Symbol specifying maximum count of linearity calibration coefficients. */
123 #define NRF_SAADC_LIN_CAL_MAX_COUNT SAADC_TRIM_LINCALCOEFF_MaxCount
124
125 /** @brief Symbol specifying maximum value of linearity calibration coefficient. */
126 #define NRF_SAADC_LIN_CAL_MAX SAADC_TRIM_LINCALCOEFF_VAL_Max
127 #endif
128
129 #if defined(NRF54H_SERIES) || defined(NRF54L_SERIES) || defined(__NRFX_DOXYGEN__)
130 /** @brief Symbol specifying width of the 8-bit sample in bits. */
131 #define NRF_SAADC_8BIT_SAMPLE_WIDTH 8
132 #else
133 #define NRF_SAADC_8BIT_SAMPLE_WIDTH 16
134 #endif
135
136 /** @brief Resolution of the analog-to-digital converter. */
137 typedef enum
138 {
139 NRF_SAADC_RESOLUTION_8BIT = SAADC_RESOLUTION_VAL_8bit, ///< 8 bit resolution.
140 NRF_SAADC_RESOLUTION_10BIT = SAADC_RESOLUTION_VAL_10bit, ///< 10 bit resolution.
141 NRF_SAADC_RESOLUTION_12BIT = SAADC_RESOLUTION_VAL_12bit, ///< 12 bit resolution.
142 NRF_SAADC_RESOLUTION_14BIT = SAADC_RESOLUTION_VAL_14bit ///< 14 bit resolution.
143 } nrf_saadc_resolution_t;
144
145 #if NRF_SAADC_HAS_AIN_AS_PIN
146 /** @brief Analog input type. */
147 typedef uint32_t nrf_saadc_input_t;
148
149 #if defined(SAADC_CH_PSELP_INTERNAL_Avdd) || defined(__NRFX_DOXYGEN__)
150 /** @brief Symbol specifying internal 0.9 V analog supply rail as input. */
151 #define NRF_SAADC_INPUT_AVDD ((SAADC_CH_PSELP_INTERNAL_Avdd + 1) << SAADC_CH_PSELP_INTERNAL_Pos)
152 #endif
153
154 #if defined(SAADC_CH_PSELP_INTERNAL_Dvdd) || defined(__NRFX_DOXYGEN__)
155 /** @brief Symbol specifying internal 0.9 V digital supply rail as input. */
156 #define NRF_SAADC_INPUT_DVDD ((SAADC_CH_PSELP_INTERNAL_Dvdd + 1) << SAADC_CH_PSELP_INTERNAL_Pos)
157 #endif
158
159 #if defined(SAADC_CH_PSELP_INTERNAL_Vdd) || defined(__NRFX_DOXYGEN__)
160 /** @brief Symbol specifying VDD as input. */
161 #define NRF_SAADC_INPUT_VDD ((SAADC_CH_PSELP_INTERNAL_Vdd + 1) << SAADC_CH_PSELP_INTERNAL_Pos)
162 #endif
163
164 #if defined(SAADC_CH_PSELP_INTERNAL_VDDAO1V8) || defined(__NRFX_DOXYGEN__)
165 /** @brief Symbol specifying AVDD_AO_1V8 as input. */
166 #define NRF_SAADC_INPUT_VDDAO1V8 ((SAADC_CH_PSELP_INTERNAL_VDDAO1V8 + 1) \
167 << SAADC_CH_PSELP_INTERNAL_Pos)
168 #endif
169
170 #if defined(SAADC_CH_PSELP_INTERNAL_VDDAO0V8) || defined(__NRFX_DOXYGEN__)
171 /** @brief Symbol specifying VDD_AO_0V8 as input. */
172 #define NRF_SAADC_INPUT_VDDAO0V8 ((SAADC_CH_PSELP_INTERNAL_VDDAO0V8 + 1) \
173 << SAADC_CH_PSELP_INTERNAL_Pos)
174 #endif
175
176 #if defined(SAADC_CH_PSELP_INTERNAL_VDDRF) || defined(__NRFX_DOXYGEN__)
177 /** @brief Symbol specifying VDDRF as input. */
178 #define NRF_SAADC_INPUT_VDDRF ((SAADC_CH_PSELP_INTERNAL_VDDRF + 1) << SAADC_CH_PSELP_INTERNAL_Pos)
179 #endif
180
181 #if defined(SAADC_CH_PSELP_INTERNAL_VBAT) || defined(__NRFX_DOXYGEN__)
182 /** @brief Symbol specifying VBat as input. */
183 #define NRF_SAADC_INPUT_VBAT ((SAADC_CH_PSELP_INTERNAL_VBAT + 1) << SAADC_CH_PSELP_INTERNAL_Pos)
184 #endif
185
186 /** @brief Symbol specifying disconnected analog input. */
187 #define NRF_SAADC_INPUT_DISABLED ((nrf_saadc_input_t)UINT32_MAX)
188 #else
189 /** @brief Input selection for the analog-to-digital converter. */
190 typedef enum
191 {
192 NRF_SAADC_INPUT_DISABLED = SAADC_CH_PSELP_PSELP_NC, ///< Not connected.
193 NRF_SAADC_INPUT_AIN0 = SAADC_CH_PSELP_PSELP_AnalogInput0, ///< Analog input 0 (AIN0).
194 NRF_SAADC_INPUT_AIN1 = SAADC_CH_PSELP_PSELP_AnalogInput1, ///< Analog input 1 (AIN1).
195 NRF_SAADC_INPUT_AIN2 = SAADC_CH_PSELP_PSELP_AnalogInput2, ///< Analog input 2 (AIN2).
196 NRF_SAADC_INPUT_AIN3 = SAADC_CH_PSELP_PSELP_AnalogInput3, ///< Analog input 3 (AIN3).
197 NRF_SAADC_INPUT_AIN4 = SAADC_CH_PSELP_PSELP_AnalogInput4, ///< Analog input 4 (AIN4).
198 NRF_SAADC_INPUT_AIN5 = SAADC_CH_PSELP_PSELP_AnalogInput5, ///< Analog input 5 (AIN5).
199 NRF_SAADC_INPUT_AIN6 = SAADC_CH_PSELP_PSELP_AnalogInput6, ///< Analog input 6 (AIN6).
200 NRF_SAADC_INPUT_AIN7 = SAADC_CH_PSELP_PSELP_AnalogInput7, ///< Analog input 7 (AIN7).
201 #if defined(SAADC_CH_PSELP_PSELP_VDD) || defined(__NRFX_DOXYGEN__)
202 NRF_SAADC_INPUT_VDD = SAADC_CH_PSELP_PSELP_VDD, ///< VDD as input.
203 #endif
204 #if defined(SAADC_CH_PSELP_PSELP_VDDHDIV5) || defined(__NRFX_DOXYGEN__)
205 NRF_SAADC_INPUT_VDDHDIV5 = SAADC_CH_PSELP_PSELP_VDDHDIV5 ///< VDDH/5 as input.
206 #endif
207 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput8) || defined(__NRFX_DOXYGEN__)
208 NRF_SAADC_INPUT_AIN8 = SAADC_CH_PSELP_PSELP_AnalogInput8, ///< Analog input 8 (AIN8).
209 #endif
210 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput9) || defined(__NRFX_DOXYGEN__)
211 NRF_SAADC_INPUT_AIN9 = SAADC_CH_PSELP_PSELP_AnalogInput9, ///< Analog input 9 (AIN9).
212 #endif
213 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput10) || defined(__NRFX_DOXYGEN__)
214 NRF_SAADC_INPUT_AIN10 = SAADC_CH_PSELP_PSELP_AnalogInput10, ///< Analog input 10 (AIN10).
215 #endif
216 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput11) || defined(__NRFX_DOXYGEN__)
217 NRF_SAADC_INPUT_AIN11 = SAADC_CH_PSELP_PSELP_AnalogInput11, ///< Analog input 11 (AIN11).
218 #endif
219 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput12) || defined(__NRFX_DOXYGEN__)
220 NRF_SAADC_INPUT_AIN12 = SAADC_CH_PSELP_PSELP_AnalogInput12, ///< Analog input 12 (AIN12).
221 #endif
222 #if defined(SAADC_CH_PSELP_PSELP_AnalogInput13) || defined(__NRFX_DOXYGEN__)
223 NRF_SAADC_INPUT_AIN13 = SAADC_CH_PSELP_PSELP_AnalogInput13, ///< Analog input 13 (AIN13).
224 #endif
225 } nrf_saadc_input_t;
226 #endif
227
228 /** @brief Analog-to-digital converter oversampling mode. */
229 typedef enum
230 {
231 NRF_SAADC_OVERSAMPLE_DISABLED = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass, ///< No oversampling.
232 NRF_SAADC_OVERSAMPLE_2X = SAADC_OVERSAMPLE_OVERSAMPLE_Over2x, ///< Oversample 2x.
233 NRF_SAADC_OVERSAMPLE_4X = SAADC_OVERSAMPLE_OVERSAMPLE_Over4x, ///< Oversample 4x.
234 NRF_SAADC_OVERSAMPLE_8X = SAADC_OVERSAMPLE_OVERSAMPLE_Over8x, ///< Oversample 8x.
235 NRF_SAADC_OVERSAMPLE_16X = SAADC_OVERSAMPLE_OVERSAMPLE_Over16x, ///< Oversample 16x.
236 NRF_SAADC_OVERSAMPLE_32X = SAADC_OVERSAMPLE_OVERSAMPLE_Over32x, ///< Oversample 32x.
237 NRF_SAADC_OVERSAMPLE_64X = SAADC_OVERSAMPLE_OVERSAMPLE_Over64x, ///< Oversample 64x.
238 NRF_SAADC_OVERSAMPLE_128X = SAADC_OVERSAMPLE_OVERSAMPLE_Over128x, ///< Oversample 128x.
239 NRF_SAADC_OVERSAMPLE_256X = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x ///< Oversample 256x.
240 } nrf_saadc_oversample_t;
241
242 #if NRF_SAADC_HAS_CH_CONFIG_RES
243 /** @brief Analog-to-digital converter channel resistor control. */
244 typedef enum
245 {
246 NRF_SAADC_RESISTOR_DISABLED = SAADC_CH_CONFIG_RESP_Bypass, ///< Bypass resistor ladder.
247 NRF_SAADC_RESISTOR_PULLDOWN = SAADC_CH_CONFIG_RESP_Pulldown, ///< Pull-down to GND.
248 NRF_SAADC_RESISTOR_PULLUP = SAADC_CH_CONFIG_RESP_Pullup, ///< Pull-up to VDD.
249 #if defined(SAADC_CH_CONFIG_RESP_VDD1_2) || defined(__NRFX_DOXYGEN__)
250 NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDD1_2, ///< Set input at VDD/2.
251 #endif
252 #if defined(SAADC_CH_CONFIG_RESP_VDDAO1V8div2)
253 NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDDAO1V8div2, ///< Set input at VDD/2.
254 #endif
255 } nrf_saadc_resistor_t;
256 #endif
257
258 /** @brief Gain factor of the analog-to-digital converter input. */
259 typedef enum
260 {
261 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_6) || defined(__NRFX_DOXYGEN__)
262 NRF_SAADC_GAIN1_6 = SAADC_CH_CONFIG_GAIN_Gain1_6, ///< Gain factor 1/6.
263 #endif
264 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_5) || defined(__NRFX_DOXYGEN__)
265 NRF_SAADC_GAIN1_5 = SAADC_CH_CONFIG_GAIN_Gain1_5, ///< Gain factor 1/5.
266 #endif
267 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_4) || defined(__NRFX_DOXYGEN__)
268 NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain1_4, ///< Gain factor 1/4.
269 #elif defined(SAADC_CH_CONFIG_GAIN_Gain2_8) || defined(__NRFX_DOXYGEN__)
270 NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain2_8, ///< Gain factor 1/4.
271 #endif
272 #if defined(SAADC_CH_CONFIG_GAIN_Gain2_7) || defined(__NRFX_DOXYGEN__)
273 NRF_SAADC_GAIN2_7 = SAADC_CH_CONFIG_GAIN_Gain2_7, ///< Gain factor 2/7.
274 #endif
275 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_3) || defined(__NRFX_DOXYGEN__)
276 NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain1_3, ///< Gain factor 1/3.
277 #elif defined(SAADC_CH_CONFIG_GAIN_Gain2_6) || defined(__NRFX_DOXYGEN__)
278 NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain2_6, ///< Gain factor 1/3.
279 #endif
280 #if defined(SAADC_CH_CONFIG_GAIN_Gain2_5) || defined(__NRFX_DOXYGEN__)
281 NRF_SAADC_GAIN2_5 = SAADC_CH_CONFIG_GAIN_Gain2_5, ///< Gain factor 2/5.
282 #endif
283 #if defined(SAADC_CH_CONFIG_GAIN_Gain1_2) || defined(__NRFX_DOXYGEN__)
284 NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain1_2, ///< Gain factor 1/2.
285 #elif defined(SAADC_CH_CONFIG_GAIN_Gain2_4) || defined(__NRFX_DOXYGEN__)
286 NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain2_4, ///< Gain factor 1/2.
287 #endif
288 #if defined(SAADC_CH_CONFIG_GAIN_Gain2_3) || defined(__NRFX_DOXYGEN__)
289 NRF_SAADC_GAIN2_3 = SAADC_CH_CONFIG_GAIN_Gain2_3, ///< Gain factor 2/3.
290 #endif
291 NRF_SAADC_GAIN1 = SAADC_CH_CONFIG_GAIN_Gain1, ///< Gain factor 1.
292 NRF_SAADC_GAIN2 = SAADC_CH_CONFIG_GAIN_Gain2, ///< Gain factor 2.
293 #if defined(SAADC_CH_CONFIG_GAIN_Gain4) || defined(__NRFX_DOXYGEN__)
294 NRF_SAADC_GAIN4 = SAADC_CH_CONFIG_GAIN_Gain4, ///< Gain factor 4.
295 #endif
296 } nrf_saadc_gain_t;
297
298 /** @brief Reference selection for the analog-to-digital converter. */
299 typedef enum
300 {
301 #if defined(SAADC_CH_CONFIG_REFSEL_Internal) || defined(__NRFX_DOXYGEN__)
302 NRF_SAADC_REFERENCE_INTERNAL = SAADC_CH_CONFIG_REFSEL_Internal, ///< Internal reference.
303 #endif
304 #if defined(SAADC_CH_CONFIG_REFSEL_VDD1_4) || defined(__NRFX_DOXYGEN__)
305 NRF_SAADC_REFERENCE_VDD4 = SAADC_CH_CONFIG_REFSEL_VDD1_4 ///< VDD/4 as reference.
306 #endif
307 #if defined(SAADC_CH_CONFIG_REFSEL_External) || defined(__NRFX_DOXYGEN__)
308 NRF_SAADC_REFERENCE_EXTERNAL = SAADC_CH_CONFIG_REFSEL_External, ///< External reference.
309 #endif
310 } nrf_saadc_reference_t;
311
312 #if NRF_SAADC_HAS_ACQTIME_ENUM
313 /** @brief Analog-to-digital converter acquisition time. */
314 typedef enum
315 {
316 NRF_SAADC_ACQTIME_3US = SAADC_CH_CONFIG_TACQ_3us, ///< 3 us.
317 NRF_SAADC_ACQTIME_5US = SAADC_CH_CONFIG_TACQ_5us, ///< 5 us.
318 NRF_SAADC_ACQTIME_10US = SAADC_CH_CONFIG_TACQ_10us, ///< 10 us.
319 NRF_SAADC_ACQTIME_15US = SAADC_CH_CONFIG_TACQ_15us, ///< 15 us.
320 NRF_SAADC_ACQTIME_20US = SAADC_CH_CONFIG_TACQ_20us, ///< 20 us.
321 NRF_SAADC_ACQTIME_40US = SAADC_CH_CONFIG_TACQ_40us ///< 40 us.
322 } nrf_saadc_acqtime_t;
323 #else
324 typedef uint16_t nrf_saadc_acqtime_t;
325 #endif
326
327 /** @brief Analog-to-digital converter channel mode. */
328 typedef enum
329 {
330 NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE, ///< Single-ended mode. PSELN will be ignored, negative input to ADC shorted to GND.
331 NRF_SAADC_MODE_DIFFERENTIAL = SAADC_CH_CONFIG_MODE_Diff ///< Differential mode.
332 } nrf_saadc_mode_t;
333
334 /** @brief Analog-to-digital converter channel burst mode. */
335 typedef enum
336 {
337 NRF_SAADC_BURST_DISABLED = SAADC_CH_CONFIG_BURST_Disabled, ///< Burst mode is disabled (normal operation).
338 NRF_SAADC_BURST_ENABLED = SAADC_CH_CONFIG_BURST_Enabled ///< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.
339 } nrf_saadc_burst_t;
340
341 /** @brief Analog-to-digital converter tasks. */
342 typedef enum
343 {
344 NRF_SAADC_TASK_START = offsetof(NRF_SAADC_Type, TASKS_START), ///< Start the ADC and prepare the result buffer in RAM.
345 NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_STOP), ///< Stop the ADC and terminate any ongoing conversion.
346 NRF_SAADC_TASK_SAMPLE = offsetof(NRF_SAADC_Type, TASKS_SAMPLE), ///< Take one ADC sample. If scan is enabled, all channels are sampled.
347 NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration.
348 } nrf_saadc_task_t;
349
350 /** @brief Analog-to-digital converter events. */
351 typedef enum
352 {
353 NRF_SAADC_EVENT_STARTED = offsetof(NRF_SAADC_Type, EVENTS_STARTED), ///< The ADC has started.
354 NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_END), ///< The ADC has filled up the result buffer.
355 NRF_SAADC_EVENT_DONE = offsetof(NRF_SAADC_Type, EVENTS_DONE), ///< A conversion task has been completed.
356 NRF_SAADC_EVENT_RESULTDONE = offsetof(NRF_SAADC_Type, EVENTS_RESULTDONE), ///< A result is ready to get transferred to RAM.
357 NRF_SAADC_EVENT_CALIBRATEDONE = offsetof(NRF_SAADC_Type, EVENTS_CALIBRATEDONE), ///< Calibration is complete.
358 NRF_SAADC_EVENT_STOPPED = offsetof(NRF_SAADC_Type, EVENTS_STOPPED), ///< The ADC has stopped.
359 NRF_SAADC_EVENT_CH0_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITH), ///< Last result is equal or above CH[0].LIMIT.HIGH.
360 NRF_SAADC_EVENT_CH0_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITL), ///< Last result is equal or below CH[0].LIMIT.LOW.
361 NRF_SAADC_EVENT_CH1_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITH), ///< Last result is equal or above CH[1].LIMIT.HIGH.
362 NRF_SAADC_EVENT_CH1_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITL), ///< Last result is equal or below CH[1].LIMIT.LOW.
363 NRF_SAADC_EVENT_CH2_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITH), ///< Last result is equal or above CH[2].LIMIT.HIGH.
364 NRF_SAADC_EVENT_CH2_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITL), ///< Last result is equal or below CH[2].LIMIT.LOW.
365 NRF_SAADC_EVENT_CH3_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITH), ///< Last result is equal or above CH[3].LIMIT.HIGH.
366 NRF_SAADC_EVENT_CH3_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITL), ///< Last result is equal or below CH[3].LIMIT.LOW.
367 NRF_SAADC_EVENT_CH4_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITH), ///< Last result is equal or above CH[4].LIMIT.HIGH.
368 NRF_SAADC_EVENT_CH4_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITL), ///< Last result is equal or below CH[4].LIMIT.LOW.
369 NRF_SAADC_EVENT_CH5_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITH), ///< Last result is equal or above CH[5].LIMIT.HIGH.
370 NRF_SAADC_EVENT_CH5_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITL), ///< Last result is equal or below CH[5].LIMIT.LOW.
371 NRF_SAADC_EVENT_CH6_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITH), ///< Last result is equal or above CH[6].LIMIT.HIGH.
372 NRF_SAADC_EVENT_CH6_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITL), ///< Last result is equal or below CH[6].LIMIT.LOW.
373 NRF_SAADC_EVENT_CH7_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITH), ///< Last result is equal or above CH[7].LIMIT.HIGH.
374 NRF_SAADC_EVENT_CH7_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL) ///< Last result is equal or below CH[7].LIMIT.LOW.
375 } nrf_saadc_event_t;
376
377 /** @brief Analog-to-digital converter interrupt masks. */
378 typedef enum
379 {
380 NRF_SAADC_INT_STARTED = SAADC_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event.
381 NRF_SAADC_INT_END = SAADC_INTENSET_END_Msk, ///< Interrupt on EVENTS_END event.
382 NRF_SAADC_INT_DONE = SAADC_INTENSET_DONE_Msk, ///< Interrupt on EVENTS_DONE event.
383 NRF_SAADC_INT_RESULTDONE = SAADC_INTENSET_RESULTDONE_Msk, ///< Interrupt on EVENTS_RESULTDONE event.
384 NRF_SAADC_INT_CALIBRATEDONE = SAADC_INTENSET_CALIBRATEDONE_Msk, ///< Interrupt on EVENTS_CALIBRATEDONE event.
385 NRF_SAADC_INT_STOPPED = SAADC_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event.
386 NRF_SAADC_INT_CH0LIMITH = SAADC_INTENSET_CH0LIMITH_Msk, ///< Interrupt on EVENTS_CH[0].LIMITH event.
387 NRF_SAADC_INT_CH0LIMITL = SAADC_INTENSET_CH0LIMITL_Msk, ///< Interrupt on EVENTS_CH[0].LIMITL event.
388 NRF_SAADC_INT_CH1LIMITH = SAADC_INTENSET_CH1LIMITH_Msk, ///< Interrupt on EVENTS_CH[1].LIMITH event.
389 NRF_SAADC_INT_CH1LIMITL = SAADC_INTENSET_CH1LIMITL_Msk, ///< Interrupt on EVENTS_CH[1].LIMITL event.
390 NRF_SAADC_INT_CH2LIMITH = SAADC_INTENSET_CH2LIMITH_Msk, ///< Interrupt on EVENTS_CH[2].LIMITH event.
391 NRF_SAADC_INT_CH2LIMITL = SAADC_INTENSET_CH2LIMITL_Msk, ///< Interrupt on EVENTS_CH[2].LIMITL event.
392 NRF_SAADC_INT_CH3LIMITH = SAADC_INTENSET_CH3LIMITH_Msk, ///< Interrupt on EVENTS_CH[3].LIMITH event.
393 NRF_SAADC_INT_CH3LIMITL = SAADC_INTENSET_CH3LIMITL_Msk, ///< Interrupt on EVENTS_CH[3].LIMITL event.
394 NRF_SAADC_INT_CH4LIMITH = SAADC_INTENSET_CH4LIMITH_Msk, ///< Interrupt on EVENTS_CH[4].LIMITH event.
395 NRF_SAADC_INT_CH4LIMITL = SAADC_INTENSET_CH4LIMITL_Msk, ///< Interrupt on EVENTS_CH[4].LIMITL event.
396 NRF_SAADC_INT_CH5LIMITH = SAADC_INTENSET_CH5LIMITH_Msk, ///< Interrupt on EVENTS_CH[5].LIMITH event.
397 NRF_SAADC_INT_CH5LIMITL = SAADC_INTENSET_CH5LIMITL_Msk, ///< Interrupt on EVENTS_CH[5].LIMITL event.
398 NRF_SAADC_INT_CH6LIMITH = SAADC_INTENSET_CH6LIMITH_Msk, ///< Interrupt on EVENTS_CH[6].LIMITH event.
399 NRF_SAADC_INT_CH6LIMITL = SAADC_INTENSET_CH6LIMITL_Msk, ///< Interrupt on EVENTS_CH[6].LIMITL event.
400 NRF_SAADC_INT_CH7LIMITH = SAADC_INTENSET_CH7LIMITH_Msk, ///< Interrupt on EVENTS_CH[7].LIMITH event.
401 NRF_SAADC_INT_CH7LIMITL = SAADC_INTENSET_CH7LIMITL_Msk, ///< Interrupt on EVENTS_CH[7].LIMITL event.
402 NRF_SAADC_INT_ALL = 0x7FFFFFFFUL ///< Mask of all interrupts.
403 } nrf_saadc_int_mask_t;
404
405 /** @brief Analog-to-digital converter value limit type. */
406 typedef enum
407 {
408 NRF_SAADC_LIMIT_LOW = 0, ///< Low limit type.
409 NRF_SAADC_LIMIT_HIGH = 1 ///< High limit type.
410 } nrf_saadc_limit_t;
411
412 #if NRFX_API_VER_AT_LEAST(3, 2, 0) || defined(__NRFX_DOXYGEN__)
413 /** @brief Type of a single ADC conversion result. */
414 typedef void nrf_saadc_value_t;
415 #else
416 typedef uint16_t nrf_saadc_value_t;
417 #endif
418
419 /** @brief Analog-to-digital converter configuration structure. */
420 typedef struct
421 {
422 nrf_saadc_resolution_t resolution; ///< Resolution of samples.
423 nrf_saadc_oversample_t oversample; ///< Oversampling configuration.
424 nrf_saadc_value_t * buffer; ///< Pointer to sample buffer.
425 uint32_t buffer_size; ///< Size of the sample buffer.
426 } nrf_saadc_config_t;
427
428 /** @brief Analog-to-digital converter channel configuration structure. */
429 typedef struct
430 {
431 #if NRF_SAADC_HAS_CH_CONFIG_RES
432 nrf_saadc_resistor_t resistor_p; ///< Resistor value on positive input.
433 nrf_saadc_resistor_t resistor_n; ///< Resistor value on negative input.
434 #endif
435 nrf_saadc_gain_t gain; ///< Gain control value.
436 nrf_saadc_reference_t reference; ///< Reference control value.
437 nrf_saadc_acqtime_t acq_time; ///< Acquisition time.
438 nrf_saadc_mode_t mode; ///< SAADC mode. Single-ended or differential.
439 nrf_saadc_burst_t burst; ///< Burst mode configuration.
440 #if NRF_SAADC_HAS_CONVTIME
441 uint8_t conv_time; ///< Conversion time.
442 #endif
443 } nrf_saadc_channel_config_t;
444
445
446 /**
447 * @brief Function for triggering the specified SAADC task.
448 *
449 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
450 * @param[in] task SAADC task.
451 */
452 NRF_STATIC_INLINE void nrf_saadc_task_trigger(NRF_SAADC_Type * p_reg,
453 nrf_saadc_task_t task);
454
455 /**
456 * @brief Function for getting the address of the specified SAADC task register.
457 *
458 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
459 * @param[in] task SAADC task.
460 *
461 * @return Address of the specified SAADC task.
462 */
463 NRF_STATIC_INLINE uint32_t nrf_saadc_task_address_get(NRF_SAADC_Type const * p_reg,
464 nrf_saadc_task_t task);
465
466 /**
467 * @brief Function for retrieving the state of the SAADC event.
468 *
469 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
470 * @param[in] event Event to be checked.
471 *
472 * @retval true The event has been generated.
473 * @retval false The event has not been generated.
474 */
475 NRF_STATIC_INLINE bool nrf_saadc_event_check(NRF_SAADC_Type const * p_reg,
476 nrf_saadc_event_t event);
477
478 /**
479 * @brief Function for clearing the specific SAADC event.
480 *
481 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
482 * @param[in] event SAADC event.
483 */
484 NRF_STATIC_INLINE void nrf_saadc_event_clear(NRF_SAADC_Type * p_reg,
485 nrf_saadc_event_t event);
486
487 /**
488 * @brief Function for getting the address of the specified SAADC event register.
489 *
490 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
491 * @param[in] event SAADC event.
492 *
493 * @return Address of the specified SAADC event.
494 */
495 NRF_STATIC_INLINE uint32_t nrf_saadc_event_address_get(NRF_SAADC_Type const * p_reg,
496 nrf_saadc_event_t event);
497
498 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
499 /**
500 * @brief Function for setting the subscribe configuration for a given
501 * SAADC task.
502 *
503 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
504 * @param[in] task Task for which to set the configuration.
505 * @param[in] channel Channel through which to subscribe events.
506 */
507 NRF_STATIC_INLINE void nrf_saadc_subscribe_set(NRF_SAADC_Type * p_reg,
508 nrf_saadc_task_t task,
509 uint8_t channel);
510
511 /**
512 * @brief Function for clearing the subscribe configuration for a given
513 * SAADC task.
514 *
515 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
516 * @param[in] task Task for which to clear the configuration.
517 */
518 NRF_STATIC_INLINE void nrf_saadc_subscribe_clear(NRF_SAADC_Type * p_reg,
519 nrf_saadc_task_t task);
520
521 /**
522 * @brief Function for setting the publish configuration for a given
523 * SAADC event.
524 *
525 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
526 * @param[in] event Event for which to set the configuration.
527 * @param[in] channel Channel through which to publish the event.
528 */
529 NRF_STATIC_INLINE void nrf_saadc_publish_set(NRF_SAADC_Type * p_reg,
530 nrf_saadc_event_t event,
531 uint8_t channel);
532
533 /**
534 * @brief Function for clearing the publish configuration for a given
535 * SAADC event.
536 *
537 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
538 * @param[in] event Event for which to clear the configuration.
539 */
540 NRF_STATIC_INLINE void nrf_saadc_publish_clear(NRF_SAADC_Type * p_reg,
541 nrf_saadc_event_t event);
542 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
543
544 /**
545 * @brief Function for getting the SAADC channel monitoring limit events.
546 *
547 * @param[in] channel Channel number.
548 * @param[in] limit_type Low limit or high limit.
549 *
550 * @return The SAADC channel monitoring limit event.
551 */
552 NRF_STATIC_INLINE nrf_saadc_event_t nrf_saadc_limit_event_get(uint8_t channel,
553 nrf_saadc_limit_t limit_type);
554
555 /**
556 * @brief Function for configuring the input pins for the specified SAADC channel.
557 *
558 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
559 * @param[in] channel Channel number.
560 * @param[in] pselp Positive input.
561 * @param[in] pseln Negative input. Set to @ref NRF_SAADC_INPUT_DISABLED in single ended mode.
562 */
563 NRF_STATIC_INLINE void nrf_saadc_channel_input_set(NRF_SAADC_Type * p_reg,
564 uint8_t channel,
565 nrf_saadc_input_t pselp,
566 nrf_saadc_input_t pseln);
567
568 /**
569 * @brief Function for configuring the positive input pin for the specified SAADC channel.
570 *
571 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
572 * @param[in] channel Channel number.
573 * @param[in] pselp Positive input.
574 */
575 NRF_STATIC_INLINE void nrf_saadc_channel_pos_input_set(NRF_SAADC_Type * p_reg,
576 uint8_t channel,
577 nrf_saadc_input_t pselp);
578
579 /**
580 * @brief Function for configuring the negative input pin for the specified SAADC channel.
581 *
582 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
583 * @param[in] channel Channel number.
584 * @param[in] pseln Negative input.
585 */
586 NRF_STATIC_INLINE void nrf_saadc_channel_neg_input_set(NRF_SAADC_Type * p_reg,
587 uint8_t channel,
588 nrf_saadc_input_t pseln);
589
590 /**
591 * @brief Function for setting the SAADC channel monitoring limits.
592 *
593 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
594 * @param[in] channel Channel number.
595 * @param[in] low Low limit.
596 * @param[in] high High limit.
597 */
598 NRF_STATIC_INLINE void nrf_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,
599 uint8_t channel,
600 int16_t low,
601 int16_t high);
602
603 /**
604 * @brief Function for setting the configuration of SAADC interrupts.
605 *
606 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
607 * @param[in] mask Interrupts configuration to be set.
608 * Use @ref nrf_saadc_int_mask_t values for bit masking.
609 */
610 NRF_STATIC_INLINE void nrf_saadc_int_set(NRF_SAADC_Type * p_reg, uint32_t mask);
611
612 /**
613 * @brief Function for enabling specified SAADC interrupts.
614 *
615 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
616 * @param[in] mask Mask of interrupts to be enabled.
617 * Use @ref nrf_saadc_int_mask_t values for bit masking.
618 */
619 NRF_STATIC_INLINE void nrf_saadc_int_enable(NRF_SAADC_Type * p_reg, uint32_t mask);
620
621 /**
622 * @brief Function for checking if the specified interrupts are enabled.
623 *
624 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
625 * @param[in] mask Mask of interrupts to be checked.
626 * Use @ref nrf_saadc_int_mask_t values for bit masking.
627 *
628 * @return Mask of enabled interrupts.
629 */
630 NRF_STATIC_INLINE uint32_t nrf_saadc_int_enable_check(NRF_SAADC_Type const * p_reg, uint32_t mask);
631
632 /**
633 * @brief Function for disabling specified interrupts.
634 *
635 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
636 * @param[in] mask Mask of interrupts to be disabled.
637 * Use @ref nrf_saadc_int_mask_t values for bit masking.
638 */
639 NRF_STATIC_INLINE void nrf_saadc_int_disable(NRF_SAADC_Type * p_reg, uint32_t mask);
640
641 /**
642 * @brief Function for generating masks for SAADC channel limit interrupts.
643 *
644 * @param[in] channel SAADC channel number.
645 * @param[in] limit_type Limit type.
646 *
647 * @return Interrupt mask.
648 */
649 NRF_STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel,
650 nrf_saadc_limit_t limit_type);
651
652 /**
653 * @brief Function for checking whether the SAADC is busy.
654 *
655 * This function checks whether the analog-to-digital converter is busy with a conversion.
656 *
657 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
658 *
659 * @retval true The SAADC is busy.
660 * @retval false The SAADC is not busy.
661 */
662 NRF_STATIC_INLINE bool nrf_saadc_busy_check(NRF_SAADC_Type const * p_reg);
663
664 /**
665 * @brief Function for enabling the SAADC.
666 *
667 * The analog-to-digital converter must be enabled before use.
668 *
669 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
670 */
671 NRF_STATIC_INLINE void nrf_saadc_enable(NRF_SAADC_Type * p_reg);
672
673 /**
674 * @brief Function for disabling the SAADC.
675 *
676 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
677 */
678 NRF_STATIC_INLINE void nrf_saadc_disable(NRF_SAADC_Type * p_reg);
679
680 /**
681 * @brief Function for checking if the SAADC is enabled.
682 *
683 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
684 *
685 * @retval true The SAADC is enabled.
686 * @retval false The SAADC is not enabled.
687 */
688 NRF_STATIC_INLINE bool nrf_saadc_enable_check(NRF_SAADC_Type const * p_reg);
689
690 /**
691 * @brief Function for initializing the SAADC result buffer.
692 *
693 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
694 * @param[in] p_buffer Pointer to the result buffer.
695 * @param[in] size Size of the buffer (in 8-bit or 16-bit samples).
696 */
697 NRF_STATIC_INLINE void nrf_saadc_buffer_init(NRF_SAADC_Type * p_reg,
698 nrf_saadc_value_t * p_buffer,
699 uint32_t size);
700
701 /**
702 * @brief Function for setting the SAADC result buffer pointer.
703 *
704 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
705 * @param[in] p_buffer Pointer to the result buffer.
706 */
707 NRF_STATIC_INLINE void nrf_saadc_buffer_pointer_set(NRF_SAADC_Type * p_reg,
708 nrf_saadc_value_t * p_buffer);
709
710 /**
711 * @brief Function for getting the SAADC result buffer pointer.
712 *
713 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
714 *
715 * @return Pointer to the result buffer.
716 */
717 NRF_STATIC_INLINE nrf_saadc_value_t * nrf_saadc_buffer_pointer_get(NRF_SAADC_Type const * p_reg);
718
719 /**
720 * @brief Function for getting the number of samples written to the result
721 * buffer since the previous START task.
722 *
723 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
724 *
725 * @return Number of 8-bit or 16-bit samples written to the buffer.
726 */
727 NRF_STATIC_INLINE uint16_t nrf_saadc_amount_get(NRF_SAADC_Type const * p_reg);
728
729 /**
730 * @brief Function for setting the SAADC sample resolution.
731 *
732 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
733 * @param[in] resolution Bit resolution.
734 */
735 NRF_STATIC_INLINE void nrf_saadc_resolution_set(NRF_SAADC_Type * p_reg,
736 nrf_saadc_resolution_t resolution);
737
738 /**
739 * @brief Function for getting the SAADC sample resolution.
740 *
741 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
742 *
743 * @return Sample resolution.
744 */
745 NRF_STATIC_INLINE nrf_saadc_resolution_t nrf_saadc_resolution_get(NRF_SAADC_Type const * p_reg);
746
747 /**
748 * @brief Function for configuring the oversampling feature.
749 *
750 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
751 * @param[in] oversample Oversampling mode.
752 */
753 NRF_STATIC_INLINE void nrf_saadc_oversample_set(NRF_SAADC_Type * p_reg,
754 nrf_saadc_oversample_t oversample);
755
756 /**
757 * @brief Function for getting the oversampling feature configuration.
758 *
759 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
760 *
761 * @return Oversampling configuration.
762 */
763 NRF_STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(NRF_SAADC_Type const * p_reg);
764
765 /**
766 * @brief Function for getting the sample count needed for one averaged result for a given
767 * oversampling configuration.
768 *
769 * @param[in] oversample Oversampling configuration.
770 *
771 * @return Sample count.
772 */
773 NRF_STATIC_INLINE uint32_t nrf_saadc_oversample_sample_count_get(nrf_saadc_oversample_t oversample);
774
775 /**
776 * @brief Function for enabling the continuous sampling.
777 *
778 * This function configures the SAADC internal timer to automatically take new samples at a fixed
779 * sample rate. Trigger the START task to begin continuous sampling. To stop the sampling, trigger
780 * the STOP task.
781 *
782 * @note The internal timer can only be used when a single input channel is enabled.
783 *
784 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
785 * @param[in] cc Capture and compare value. Sample rate is 16 MHz/cc.
786 * Valid @c CC range is from 80 to 2047.
787 */
788 NRF_STATIC_INLINE void nrf_saadc_continuous_mode_enable(NRF_SAADC_Type * p_reg,
789 uint16_t cc);
790
791 /**
792 * @brief Function for checking if the continuous sampling is enabled.
793 *
794 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
795 *
796 * @retval true The continuous sampling is enabled.
797 * @retval false The continuous sampling is disabled.
798 */
799 NRF_STATIC_INLINE bool nrf_saadc_continuous_mode_enable_check(NRF_SAADC_Type const * p_reg);
800
801 /**
802 * @brief Function for disabling the continuous sampling.
803 *
804 * New samples can still be acquired by manually triggering the SAMPLE task or by PPI.
805 *
806 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
807 */
808 NRF_STATIC_INLINE void nrf_saadc_continuous_mode_disable(NRF_SAADC_Type * p_reg);
809
810 #if NRF_SAADC_HAS_LIN_CAL
811 /**
812 * @brief Function for setting linearity calibration coefficient.
813 *
814 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
815 * @param[in] index Coefficient number.
816 * @param[in] coeff Value of the coefficient.
817 */
818 NRF_STATIC_INLINE void nrf_saadc_linearity_calibration_coeff_set(NRF_SAADC_Type * p_reg,
819 uint8_t index,
820 uint32_t coeff);
821
822 /**
823 * @brief Function for getting linearity calibration coefficient.
824 *
825 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
826 * @param[in] index Coefficient number.
827 *
828 * @return Value of the coefficient.
829 */
830 NRF_STATIC_INLINE uint32_t nrf_saadc_linearity_calibration_coeff_get(NRF_SAADC_Type const * p_reg,
831 uint8_t index);
832 #endif
833
834 /**
835 * @brief Function for initializing the SAADC channel.
836 *
837 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
838 * @param[in] channel Channel number.
839 * @param[in] config Pointer to the channel configuration structure.
840 */
841 NRF_STATIC_INLINE void nrf_saadc_channel_init(NRF_SAADC_Type * p_reg,
842 uint8_t channel,
843 nrf_saadc_channel_config_t const * config);
844
845 /**
846 * @brief Function for configuring the burst mode for the specified channel.
847 *
848 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
849 * @param[in] channel Channel number.
850 * @param[in] burst Burst mode setting.
851 */
852 NRF_STATIC_INLINE void nrf_saadc_burst_set(NRF_SAADC_Type * p_reg,
853 uint8_t channel,
854 nrf_saadc_burst_t burst);
855
856 /**
857 * @brief Function for getting the minimum value of the conversion result.
858 *
859 * The minimum value of the conversion result depends on the configured resolution.
860 *
861 * @param[in] resolution Bit resolution.
862 *
863 * @return Minimum value of the conversion result.
864 */
865 NRF_STATIC_INLINE int16_t nrf_saadc_value_min_get(nrf_saadc_resolution_t resolution);
866
867 /**
868 * @brief Function for getting the maximum value of the conversion result.
869 *
870 * The maximum value of the conversion result depends on the configured resolution.
871 *
872 * @param[in] resolution Bit resolution.
873 *
874 * @return Maximum value of the conversion result.
875 */
876 NRF_STATIC_INLINE int16_t nrf_saadc_value_max_get(nrf_saadc_resolution_t resolution);
877
878 #ifndef NRF_DECLARE_ONLY
879
nrf_saadc_task_trigger(NRF_SAADC_Type * p_reg,nrf_saadc_task_t task)880 NRF_STATIC_INLINE void nrf_saadc_task_trigger(NRF_SAADC_Type * p_reg, nrf_saadc_task_t task)
881 {
882 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
883 }
884
nrf_saadc_task_address_get(NRF_SAADC_Type const * p_reg,nrf_saadc_task_t task)885 NRF_STATIC_INLINE uint32_t nrf_saadc_task_address_get(NRF_SAADC_Type const * p_reg,
886 nrf_saadc_task_t task)
887 {
888 return nrf_task_event_address_get(p_reg, task);
889 }
890
nrf_saadc_event_check(NRF_SAADC_Type const * p_reg,nrf_saadc_event_t event)891 NRF_STATIC_INLINE bool nrf_saadc_event_check(NRF_SAADC_Type const * p_reg, nrf_saadc_event_t event)
892 {
893 return nrf_event_check(p_reg, event);
894 }
895
nrf_saadc_event_clear(NRF_SAADC_Type * p_reg,nrf_saadc_event_t event)896 NRF_STATIC_INLINE void nrf_saadc_event_clear(NRF_SAADC_Type * p_reg, nrf_saadc_event_t event)
897 {
898 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
899 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
900 }
901
nrf_saadc_event_address_get(NRF_SAADC_Type const * p_reg,nrf_saadc_event_t event)902 NRF_STATIC_INLINE uint32_t nrf_saadc_event_address_get(NRF_SAADC_Type const * p_reg,
903 nrf_saadc_event_t event)
904 {
905 return nrf_task_event_address_get(p_reg, event);
906 }
907
908 #if defined(DPPI_PRESENT)
nrf_saadc_subscribe_set(NRF_SAADC_Type * p_reg,nrf_saadc_task_t task,uint8_t channel)909 NRF_STATIC_INLINE void nrf_saadc_subscribe_set(NRF_SAADC_Type * p_reg,
910 nrf_saadc_task_t task,
911 uint8_t channel)
912 {
913 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
914 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
915 }
916
nrf_saadc_subscribe_clear(NRF_SAADC_Type * p_reg,nrf_saadc_task_t task)917 NRF_STATIC_INLINE void nrf_saadc_subscribe_clear(NRF_SAADC_Type * p_reg, nrf_saadc_task_t task)
918 {
919 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
920 }
921
nrf_saadc_publish_set(NRF_SAADC_Type * p_reg,nrf_saadc_event_t event,uint8_t channel)922 NRF_STATIC_INLINE void nrf_saadc_publish_set(NRF_SAADC_Type * p_reg,
923 nrf_saadc_event_t event,
924 uint8_t channel)
925 {
926 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
927 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
928 }
929
nrf_saadc_publish_clear(NRF_SAADC_Type * p_reg,nrf_saadc_event_t event)930 NRF_STATIC_INLINE void nrf_saadc_publish_clear(NRF_SAADC_Type * p_reg, nrf_saadc_event_t event)
931 {
932 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
933 }
934 #endif // defined(DPPI_PRESENT)
935
nrf_saadc_limit_event_get(uint8_t channel,nrf_saadc_limit_t limit_type)936 NRF_STATIC_INLINE nrf_saadc_event_t nrf_saadc_limit_event_get(uint8_t channel,
937 nrf_saadc_limit_t limit_type)
938 {
939 if (limit_type == NRF_SAADC_LIMIT_HIGH)
940 {
941 return (nrf_saadc_event_t)NRFX_OFFSETOF(NRF_SAADC_Type, EVENTS_CH[channel].LIMITH);
942 }
943 else
944 {
945 return (nrf_saadc_event_t)NRFX_OFFSETOF(NRF_SAADC_Type, EVENTS_CH[channel].LIMITL);
946 }
947 }
948
nrf_saadc_channel_input_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_input_t pselp,nrf_saadc_input_t pseln)949 NRF_STATIC_INLINE void nrf_saadc_channel_input_set(NRF_SAADC_Type * p_reg,
950 uint8_t channel,
951 nrf_saadc_input_t pselp,
952 nrf_saadc_input_t pseln)
953 {
954 nrf_saadc_channel_pos_input_set(p_reg, channel, pselp);
955 nrf_saadc_channel_neg_input_set(p_reg, channel, pseln);
956 }
957
nrf_saadc_channel_pos_input_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_input_t pselp)958 NRF_STATIC_INLINE void nrf_saadc_channel_pos_input_set(NRF_SAADC_Type * p_reg,
959 uint8_t channel,
960 nrf_saadc_input_t pselp)
961 {
962 uint32_t pselp_reg = pselp;
963 #if NRF_SAADC_HAS_AIN_AS_PIN
964 if (pselp == NRF_SAADC_INPUT_DISABLED)
965 {
966 pselp_reg = 0;
967 }
968 #if NRF_SAADC_HAS_CH_PSELP_INTERNAL
969 else if (pselp >> SAADC_CH_PSELP_INTERNAL_Pos)
970 {
971 /* Substract shifted '1' before setting register value,
972 * as it was artifically added before in the internal input definition */
973 pselp_reg = (pselp - (1 << SAADC_CH_PSELP_INTERNAL_Pos)) |
974 (SAADC_CH_PSELP_CONNECT_Internal << SAADC_CH_PSELP_CONNECT_Pos);
975 }
976 #endif
977 else
978 {
979 pselp_reg = (NRF_PIN_NUMBER_TO_PIN(pselp) << SAADC_CH_PSELP_PIN_Pos) |
980 (NRF_PIN_NUMBER_TO_PORT(pselp) << SAADC_CH_PSELP_PORT_Pos) |
981 (SAADC_CH_PSELP_CONNECT_AnalogInput << SAADC_CH_PSELP_CONNECT_Pos);
982 }
983 #endif
984 p_reg->CH[channel].PSELP = pselp_reg;
985 }
986
nrf_saadc_channel_neg_input_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_input_t pseln)987 NRF_STATIC_INLINE void nrf_saadc_channel_neg_input_set(NRF_SAADC_Type * p_reg,
988 uint8_t channel,
989 nrf_saadc_input_t pseln)
990 {
991 uint32_t pseln_reg = pseln;
992 #if NRF_SAADC_HAS_AIN_AS_PIN
993 if (pseln == NRF_SAADC_INPUT_DISABLED)
994 {
995 pseln_reg = 0;
996 }
997 #if NRF_SAADC_HAS_CH_PSELN_INTERNAL
998 else if (pseln >> SAADC_CH_PSELN_INTERNAL_Pos)
999 {
1000 /* Substract shifted '1' before setting register value,
1001 * as it was artifically added before in the internal input definition */
1002 pseln_reg = (pseln - (1 << SAADC_CH_PSELN_INTERNAL_Pos)) |
1003 (SAADC_CH_PSELN_CONNECT_Internal << SAADC_CH_PSELN_CONNECT_Pos);
1004 }
1005 #endif
1006 else
1007 {
1008 pseln_reg = (NRF_PIN_NUMBER_TO_PIN(pseln) << SAADC_CH_PSELN_PIN_Pos) |
1009 (NRF_PIN_NUMBER_TO_PORT(pseln) << SAADC_CH_PSELN_PORT_Pos) |
1010 (SAADC_CH_PSELN_CONNECT_AnalogInput << SAADC_CH_PSELN_CONNECT_Pos);
1011 }
1012 #endif
1013 p_reg->CH[channel].PSELN = pseln_reg;
1014 }
1015
nrf_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,uint8_t channel,int16_t low,int16_t high)1016 NRF_STATIC_INLINE void nrf_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,
1017 uint8_t channel,
1018 int16_t low,
1019 int16_t high)
1020 {
1021 p_reg->CH[channel].LIMIT = (
1022 (((uint32_t) low << SAADC_CH_LIMIT_LOW_Pos) & SAADC_CH_LIMIT_LOW_Msk)
1023 | (((uint32_t) high << SAADC_CH_LIMIT_HIGH_Pos) & SAADC_CH_LIMIT_HIGH_Msk));
1024 }
1025
nrf_saadc_int_set(NRF_SAADC_Type * p_reg,uint32_t mask)1026 NRF_STATIC_INLINE void nrf_saadc_int_set(NRF_SAADC_Type * p_reg, uint32_t mask)
1027 {
1028 p_reg->INTEN = mask;
1029 }
1030
nrf_saadc_int_enable(NRF_SAADC_Type * p_reg,uint32_t mask)1031 NRF_STATIC_INLINE void nrf_saadc_int_enable(NRF_SAADC_Type * p_reg, uint32_t mask)
1032 {
1033 p_reg->INTENSET = mask;
1034 }
1035
nrf_saadc_int_enable_check(NRF_SAADC_Type const * p_reg,uint32_t mask)1036 NRF_STATIC_INLINE uint32_t nrf_saadc_int_enable_check(NRF_SAADC_Type const * p_reg, uint32_t mask)
1037 {
1038 return p_reg->INTENSET & mask;
1039 }
1040
nrf_saadc_int_disable(NRF_SAADC_Type * p_reg,uint32_t mask)1041 NRF_STATIC_INLINE void nrf_saadc_int_disable(NRF_SAADC_Type * p_reg, uint32_t mask)
1042 {
1043 p_reg->INTENCLR = mask;
1044 }
1045
nrf_saadc_limit_int_get(uint8_t channel,nrf_saadc_limit_t limit_type)1046 NRF_STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel,
1047 nrf_saadc_limit_t limit_type)
1048 {
1049 NRFX_ASSERT(channel < SAADC_CH_NUM);
1050 uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ?
1051 NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH;
1052 return mask << (channel * 2);
1053 }
1054
nrf_saadc_busy_check(NRF_SAADC_Type const * p_reg)1055 NRF_STATIC_INLINE bool nrf_saadc_busy_check(NRF_SAADC_Type const * p_reg)
1056 {
1057 return (p_reg->STATUS == (SAADC_STATUS_STATUS_Busy << SAADC_STATUS_STATUS_Pos));
1058 }
1059
nrf_saadc_enable(NRF_SAADC_Type * p_reg)1060 NRF_STATIC_INLINE void nrf_saadc_enable(NRF_SAADC_Type * p_reg)
1061 {
1062 p_reg->ENABLE = (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos);
1063 }
1064
nrf_saadc_disable(NRF_SAADC_Type * p_reg)1065 NRF_STATIC_INLINE void nrf_saadc_disable(NRF_SAADC_Type * p_reg)
1066 {
1067 p_reg->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos);
1068 }
1069
nrf_saadc_enable_check(NRF_SAADC_Type const * p_reg)1070 NRF_STATIC_INLINE bool nrf_saadc_enable_check(NRF_SAADC_Type const * p_reg)
1071 {
1072 return (p_reg->ENABLE == (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos));
1073 }
1074
nrf_saadc_buffer_init(NRF_SAADC_Type * p_reg,nrf_saadc_value_t * p_buffer,uint32_t size)1075 NRF_STATIC_INLINE void nrf_saadc_buffer_init(NRF_SAADC_Type * p_reg,
1076 nrf_saadc_value_t * p_buffer,
1077 uint32_t size)
1078 {
1079 #if (NRF_SAADC_8BIT_SAMPLE_WIDTH == 8)
1080 if (nrf_saadc_resolution_get(p_reg) != NRF_SAADC_RESOLUTION_8BIT)
1081 {
1082 size = size * 2;
1083 }
1084 #endif
1085
1086 p_reg->RESULT.PTR = (uint32_t)p_buffer;
1087 p_reg->RESULT.MAXCNT = size;
1088 }
1089
nrf_saadc_buffer_pointer_set(NRF_SAADC_Type * p_reg,nrf_saadc_value_t * p_buffer)1090 NRF_STATIC_INLINE void nrf_saadc_buffer_pointer_set(NRF_SAADC_Type * p_reg,
1091 nrf_saadc_value_t * p_buffer)
1092 {
1093 p_reg->RESULT.PTR = (uint32_t)p_buffer;
1094 }
1095
nrf_saadc_buffer_pointer_get(NRF_SAADC_Type const * p_reg)1096 NRF_STATIC_INLINE nrf_saadc_value_t * nrf_saadc_buffer_pointer_get(NRF_SAADC_Type const * p_reg)
1097 {
1098 return (nrf_saadc_value_t *)p_reg->RESULT.PTR;
1099 }
1100
nrf_saadc_amount_get(NRF_SAADC_Type const * p_reg)1101 NRF_STATIC_INLINE uint16_t nrf_saadc_amount_get(NRF_SAADC_Type const * p_reg)
1102 {
1103 uint16_t result = (uint16_t)p_reg->RESULT.AMOUNT;
1104
1105 #if (NRF_SAADC_8BIT_SAMPLE_WIDTH == 8)
1106 if (nrf_saadc_resolution_get(p_reg) != NRF_SAADC_RESOLUTION_8BIT)
1107 {
1108 result = result / 2;
1109 }
1110 #endif
1111
1112 return result;
1113 }
1114
nrf_saadc_resolution_set(NRF_SAADC_Type * p_reg,nrf_saadc_resolution_t resolution)1115 NRF_STATIC_INLINE void nrf_saadc_resolution_set(NRF_SAADC_Type * p_reg,
1116 nrf_saadc_resolution_t resolution)
1117 {
1118 p_reg->RESOLUTION = resolution;
1119 }
1120
nrf_saadc_resolution_get(NRF_SAADC_Type const * p_reg)1121 NRF_STATIC_INLINE nrf_saadc_resolution_t nrf_saadc_resolution_get(NRF_SAADC_Type const * p_reg)
1122 {
1123 return (nrf_saadc_resolution_t)p_reg->RESOLUTION;
1124 }
1125
nrf_saadc_oversample_set(NRF_SAADC_Type * p_reg,nrf_saadc_oversample_t oversample)1126 NRF_STATIC_INLINE void nrf_saadc_oversample_set(NRF_SAADC_Type * p_reg,
1127 nrf_saadc_oversample_t oversample)
1128 {
1129 p_reg->OVERSAMPLE = oversample;
1130 }
1131
nrf_saadc_oversample_get(NRF_SAADC_Type const * p_reg)1132 NRF_STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(NRF_SAADC_Type const * p_reg)
1133 {
1134 return (nrf_saadc_oversample_t)p_reg->OVERSAMPLE;
1135 }
1136
nrf_saadc_oversample_sample_count_get(nrf_saadc_oversample_t oversample)1137 NRF_STATIC_INLINE uint32_t nrf_saadc_oversample_sample_count_get(nrf_saadc_oversample_t oversample)
1138 {
1139 return (1 << (uint32_t)oversample);
1140 }
1141
nrf_saadc_continuous_mode_enable(NRF_SAADC_Type * p_reg,uint16_t cc)1142 NRF_STATIC_INLINE void nrf_saadc_continuous_mode_enable(NRF_SAADC_Type * p_reg, uint16_t cc)
1143 {
1144 NRFX_ASSERT((cc >= 80) && (cc <= 2047));
1145 p_reg->SAMPLERATE = (SAADC_SAMPLERATE_MODE_Timers << SAADC_SAMPLERATE_MODE_Pos)
1146 | ((uint32_t)cc << SAADC_SAMPLERATE_CC_Pos);
1147 }
1148
nrf_saadc_continuous_mode_enable_check(NRF_SAADC_Type const * p_reg)1149 NRF_STATIC_INLINE bool nrf_saadc_continuous_mode_enable_check(NRF_SAADC_Type const * p_reg)
1150 {
1151 return (bool)((p_reg->SAMPLERATE & SAADC_SAMPLERATE_MODE_Msk)
1152 == (SAADC_SAMPLERATE_MODE_Timers << SAADC_SAMPLERATE_MODE_Pos));
1153 }
1154
nrf_saadc_continuous_mode_disable(NRF_SAADC_Type * p_reg)1155 NRF_STATIC_INLINE void nrf_saadc_continuous_mode_disable(NRF_SAADC_Type * p_reg)
1156 {
1157 p_reg->SAMPLERATE = SAADC_SAMPLERATE_MODE_Task << SAADC_SAMPLERATE_MODE_Pos;
1158 }
1159
1160 #if NRF_SAADC_HAS_LIN_CAL
nrf_saadc_linearity_calibration_coeff_set(NRF_SAADC_Type * p_reg,uint8_t index,uint32_t coeff)1161 NRF_STATIC_INLINE void nrf_saadc_linearity_calibration_coeff_set(NRF_SAADC_Type * p_reg,
1162 uint8_t index,
1163 uint32_t coeff)
1164 {
1165 NRFX_ASSERT(index < NRF_SAADC_LIN_CAL_MAX_COUNT);
1166 NRFX_ASSERT(coeff <= NRF_SAADC_LIN_CAL_MAX);
1167 p_reg->TRIM.LINCALCOEFF[index] = coeff;
1168 }
1169
nrf_saadc_linearity_calibration_coeff_get(NRF_SAADC_Type const * p_reg,uint8_t index)1170 NRF_STATIC_INLINE uint32_t nrf_saadc_linearity_calibration_coeff_get(NRF_SAADC_Type const * p_reg,
1171 uint8_t index)
1172 {
1173 NRFX_ASSERT(index < NRF_SAADC_LIN_CAL_MAX_COUNT);
1174 return p_reg->TRIM.LINCALCOEFF[index];
1175 }
1176 #endif
1177
nrf_saadc_channel_init(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_channel_config_t const * config)1178 NRF_STATIC_INLINE void nrf_saadc_channel_init(NRF_SAADC_Type * p_reg,
1179 uint8_t channel,
1180 nrf_saadc_channel_config_t const * config)
1181 {
1182 #if !NRF_SAADC_HAS_ACQTIME_ENUM
1183 NRFX_ASSERT(config->acq_time <= NRF_SAADC_ACQTIME_MAX);
1184 #endif
1185 #if NRF_SAADC_HAS_CONVTIME
1186 NRFX_ASSERT(config->conv_time <= NRF_SAADC_CONVTIME_MAX);
1187 #endif
1188 p_reg->CH[channel].CONFIG =
1189 ((config->gain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk)
1190 | ((config->reference << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk)
1191 | ((config->acq_time << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk)
1192 #if NRF_SAADC_HAS_CH_CONFIG_RES
1193 | ((config->resistor_p << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk)
1194 | ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk)
1195 #endif
1196 #if NRF_SAADC_HAS_CONVTIME
1197 | ((config->conv_time << SAADC_CH_CONFIG_TCONV_Pos) & SAADC_CH_CONFIG_TCONV_Msk)
1198 #endif
1199 | ((config->mode << SAADC_CH_CONFIG_MODE_Pos) & SAADC_CH_CONFIG_MODE_Msk)
1200 | ((config->burst << SAADC_CH_CONFIG_BURST_Pos) & SAADC_CH_CONFIG_BURST_Msk);
1201 }
1202
nrf_saadc_burst_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_burst_t burst)1203 NRF_STATIC_INLINE void nrf_saadc_burst_set(NRF_SAADC_Type * p_reg,
1204 uint8_t channel,
1205 nrf_saadc_burst_t burst)
1206 {
1207 p_reg->CH[channel].CONFIG = (p_reg->CH[channel].CONFIG & ~SAADC_CH_CONFIG_BURST_Msk) |
1208 (burst << SAADC_CH_CONFIG_BURST_Pos);
1209 }
1210
nrf_saadc_value_min_get(nrf_saadc_resolution_t resolution)1211 NRF_STATIC_INLINE int16_t nrf_saadc_value_min_get(nrf_saadc_resolution_t resolution)
1212 {
1213 uint8_t res_bits = 0;
1214 switch (resolution)
1215 {
1216 case NRF_SAADC_RESOLUTION_8BIT:
1217 res_bits = 8;
1218 break;
1219 case NRF_SAADC_RESOLUTION_10BIT:
1220 res_bits = 10;
1221 break;
1222 case NRF_SAADC_RESOLUTION_12BIT:
1223 res_bits = 12;
1224 break;
1225 case NRF_SAADC_RESOLUTION_14BIT:
1226 res_bits = 14;
1227 break;
1228 default:
1229 NRFX_ASSERT(false);
1230 }
1231 return (int16_t)(-(1 << res_bits));
1232 }
1233
nrf_saadc_value_max_get(nrf_saadc_resolution_t resolution)1234 NRF_STATIC_INLINE int16_t nrf_saadc_value_max_get(nrf_saadc_resolution_t resolution)
1235 {
1236 uint8_t res_bits = 0;
1237 switch (resolution)
1238 {
1239 case NRF_SAADC_RESOLUTION_8BIT:
1240 res_bits = 8;
1241 break;
1242 case NRF_SAADC_RESOLUTION_10BIT:
1243 res_bits = 10;
1244 break;
1245 case NRF_SAADC_RESOLUTION_12BIT:
1246 res_bits = 12;
1247 break;
1248 case NRF_SAADC_RESOLUTION_14BIT:
1249 res_bits = 14;
1250 break;
1251 default:
1252 NRFX_ASSERT(false);
1253 }
1254 return (int16_t)((1 << res_bits) - 1);
1255 }
1256
1257 #endif // NRF_DECLARE_ONLY
1258
1259 /** @} */
1260
1261 #ifdef __cplusplus
1262 }
1263 #endif
1264
1265 #endif // NRF_SAADC_H_
1266
