1 /*
2 * Copyright (c) 2015 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_PWM_H__
35 #define NRF_PWM_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_pwm_hal PWM HAL
45 * @{
46 * @ingroup nrf_pwm
47 * @brief Hardware access layer for managing the Pulse Width Modulation (PWM) peripheral.
48 */
49
50 #if defined(PWM_DMA_SEQ_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
51 /** @brief Symbol indicating whether dedicated DMA register is present. */
52 #define NRF_PWM_HAS_DMA_REG 1
53 #else
54 #define NRF_PWM_HAS_DMA_REG 0
55 #endif
56
57 #if defined(PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk) || \
58 defined(PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Msk) || defined(__NRFX_DOXYGEN__)
59 /** @brief Symbol indicating whether shorting SEQSTART task with LOOPSDONE event is available. */
60 #define NRF_PWM_HAS_SHORT_LOOPSDONE_SEQSTART 1
61 #else
62 #define NRF_PWM_HAS_SHORT_LOOPSDONE_SEQSTART 0
63 #endif
64
65 #if (defined(PWM_TASKS_DMA_SEQ_START_START_Msk) && defined(PWM_EVENTS_DMA_SEQ_END_END_Msk)) || \
66 defined(__NRFX_DOXYGEN__)
67 /** @brief Symbol indicating whether PWM DMA tasks and events are present. */
68 #define NRF_PWM_HAS_DMA_TASKS_EVENTS 1
69 #else
70 #define NRF_PWM_HAS_DMA_TASKS_EVENTS 0
71 #endif
72
73 #if defined(PWM_SEQ_CNT_CNT_Msk) || defined(__NRFX_DOXYGEN__)
74 /** @brief Symbol indicating whether setting the number of duty cycle values for a sequence is available. */
75 #define NRF_PWM_HAS_SEQ_CNT 1
76 #else
77 #define NRF_PWM_HAS_SEQ_CNT 0
78 #endif
79
80 #if defined(PWM_IDLEOUT_ResetValue) || defined(__NRFX_DOXYGEN__)
81 /** @brief Symbol indicating whether PWM has IDLEOUT register. */
82 #define NRF_PWM_HAS_IDLEOUT 1
83 #else
84 #define NRF_PWM_HAS_IDLEOUT 0
85 #endif
86
87 /**
88 * @brief Macro getting pointer to the structure of registers of the PWM peripheral.
89 *
90 * @param[in] idx PWM instance index.
91 *
92 * @return Pointer to the structure of registers of the PWM peripheral.
93 */
94 #define NRF_PWM_INST_GET(idx) NRFX_CONCAT(NRF_, PWM, idx)
95
96 /**
97 * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
98 * function call to specify that a given output channel shall not be
99 * connected to a physical pin.
100 */
101 #define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF
102
103 /** @brief Number of channels in each PWM instance. */
104 #define NRF_PWM_CHANNEL_COUNT 4
105
106 /**
107 * @brief Helper macro for calculating the number of 16-bit values in the specified
108 * array of duty cycle values.
109 */
110 #define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / 2UL)
111
112
113 /** @brief PWM tasks. */
114 typedef enum
115 {
116 NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
117 #if NRF_PWM_HAS_DMA_TASKS_EVENTS
118 NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_DMA.SEQ[0].START), ///< Starts playback of sequence 0.
119 NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_DMA.SEQ[1].START), ///< Starts playback of sequence 1.
120 #else
121 NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
122 NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
123 #endif
124 NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
125 } nrf_pwm_task_t;
126
127 /** @brief PWM events. */
128 typedef enum
129 {
130 NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated.
131 NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
132 NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
133 NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
134 NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
135 NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period.
136 NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the specified number of times.
137 } nrf_pwm_event_t;
138
139 /** @brief PWM interrupts. */
140 typedef enum
141 {
142 NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
143 NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk, ///< Interrupt on SEQSTARTED[0] event.
144 NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk, ///< Interrupt on SEQSTARTED[1] event.
145 NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk, ///< Interrupt on SEQEND[0] event.
146 NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk, ///< Interrupt on SEQEND[1] event.
147 NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event.
148 NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event.
149 } nrf_pwm_int_mask_t;
150
151 /** @brief PWM shortcuts. */
152 typedef enum
153 {
154 NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task.
155 NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task.
156 #if defined(PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk) || defined(__NRFX_DOXYGEN__)
157 NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task.
158 NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task.
159 #else
160 NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_DMA_SEQ0_START_Msk, ///< Shortcut between LOOPSDONE event and DMA.SEQ[0].START task.
161 NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_DMA_SEQ1_START_Msk, ///< Shortcut between LOOPSDONE event and DMA.SEQ[1].START task.
162 #endif
163 NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task.
164 } nrf_pwm_short_mask_t;
165
166 /** @brief PWM modes of operation. */
167 typedef enum
168 {
169 NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle).
170 NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
171 } nrf_pwm_mode_t;
172
173 /** @brief PWM base clock frequencies. */
174 typedef enum
175 {
176 NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz.
177 NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2, ///< 16 MHz / 2 = 8 MHz.
178 NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4, ///< 16 MHz / 4 = 4 MHz.
179 NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8, ///< 16 MHz / 8 = 2 MHz.
180 NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz.
181 NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz.
182 NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz.
183 NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz.
184 } nrf_pwm_clk_t;
185
186 /**
187 * @brief PWM decoder load modes.
188 *
189 * The selected mode determines how the sequence data is read from RAM and
190 * spread to the compare registers.
191 */
192 typedef enum
193 {
194 NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common, ///< 1st half word (16-bit) used in all PWM channels (0-3).
195 NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped, ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3.
196 NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3.
197 NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter.
198 } nrf_pwm_dec_load_t;
199
200 /**
201 * @brief PWM decoder next step modes.
202 *
203 * The selected mode determines when the next value from the active sequence
204 * is loaded.
205 */
206 typedef enum
207 {
208 NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times.
209 NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
210 } nrf_pwm_dec_step_t;
211
212 /**
213 * @brief Type used for defining duty cycle values for a sequence
214 * loaded in @ref NRF_PWM_LOAD_COMMON mode.
215 */
216 typedef uint16_t nrf_pwm_values_common_t;
217
218 /**
219 * @brief Structure for defining duty cycle values for a sequence
220 * loaded in @ref NRF_PWM_LOAD_GROUPED mode.
221 */
222 typedef struct {
223 uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
224 uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
225 } nrf_pwm_values_grouped_t;
226
227 /**
228 * @brief Structure for defining duty cycle values for a sequence
229 * loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
230 */
231 typedef struct
232 {
233 uint16_t channel_0; ///< Duty cycle value for channel 0.
234 uint16_t channel_1; ///< Duty cycle value for channel 1.
235 uint16_t channel_2; ///< Duty cycle value for channel 2.
236 uint16_t channel_3; ///< Duty cycle value for channel 3.
237 } nrf_pwm_values_individual_t;
238
239 /**
240 * @brief Structure for defining duty cycle values for a sequence
241 * loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode.
242 */
243 typedef struct {
244 uint16_t channel_0; ///< Duty cycle value for channel 0.
245 uint16_t channel_1; ///< Duty cycle value for channel 1.
246 uint16_t channel_2; ///< Duty cycle value for channel 2.
247 uint16_t counter_top; ///< Top value for the pulse generator counter.
248 } nrf_pwm_values_wave_form_t;
249
250 /**
251 * @brief Union grouping pointers to arrays of duty cycle values applicable to
252 * various loading modes.
253 */
254 typedef union {
255 nrf_pwm_values_common_t const * p_common; ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode.
256 nrf_pwm_values_grouped_t const * p_grouped; ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode.
257 nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
258 nrf_pwm_values_wave_form_t const * p_wave_form; ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode.
259 uint16_t const * p_raw; ///< Pointer providing raw access to the values.
260 } nrf_pwm_values_t;
261
262 /**
263 * @brief Structure for defining a sequence of PWM duty cycles.
264 *
265 * When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
266 * provided duty cycle values are not copied. The @p values pointer is stored
267 * in the internal register of the peripheral, and the values are loaded from RAM
268 * during the sequence playback. Therefore, you must ensure that the values
269 * do not change before and during the sequence playback (for example,
270 * the values cannot be placed in a local variable that is allocated on stack).
271 * If the sequence is played in a loop and the values are to be updated
272 * before the next iteration, it is safe to modify them when the corresponding
273 * event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
274 * or @ref NRF_PWM_EVENT_SEQEND1, respectively).
275 *
276 * @note The @p repeats and @p end_delay values (which are written to the
277 * SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
278 * respectively) are ignored at the end of a complex sequence
279 * playback, indicated by the LOOPSDONE event.
280 * See the Product Specification for more information.
281 */
282 typedef struct
283 {
284 nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
285 /**< This field is defined as an union of pointers
286 * to provide a convenient way to define duty
287 * cycle values in various loading modes
288 * (see @ref nrf_pwm_dec_load_t).
289 * In each value, the most significant bit (15)
290 * determines the polarity of the output and the
291 * others (14-0) compose the 15-bit value to be
292 * compared with the pulse generator counter. */
293 uint16_t length; ///< Number of 16-bit values in the array pointed by @p values.
294 uint32_t repeats; ///< Number of times that each duty cycle is to be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
295 uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
296 } nrf_pwm_sequence_t;
297
298
299 /**
300 * @brief Function for activating the specified PWM task.
301 *
302 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
303 * @param[in] task Task to be activated.
304 */
305 NRF_STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
306 nrf_pwm_task_t task);
307
308 /**
309 * @brief Function for getting the address of the specified PWM task register.
310 *
311 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
312 * @param[in] task PWM task.
313 *
314 * @return Address of the specified task register.
315 */
316 NRF_STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
317 nrf_pwm_task_t task);
318
319 /**
320 * @brief Function for clearing the specified PWM event.
321 *
322 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
323 * @param[in] event Event to clear.
324 */
325 NRF_STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
326 nrf_pwm_event_t event);
327
328 /**
329 * @brief Function for retrieving the state of the PWM event.
330 *
331 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
332 * @param[in] event Event to be checked.
333 *
334 * @retval true The event has been generated.
335 * @retval false The event has not been generated.
336 */
337 NRF_STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
338 nrf_pwm_event_t event);
339
340 /**
341 * @brief Function for getting the address of the specified PWM event register.
342 *
343 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
344 * @param[in] event PWM event.
345 *
346 * @return Address of the specified event register.
347 */
348 NRF_STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
349 nrf_pwm_event_t event);
350
351 /**
352 * @brief Function for enabling the specified shortcuts.
353 *
354 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
355 * @param[in] mask Mask of shortcuts to be enabled.
356 */
357 NRF_STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
358 uint32_t mask);
359
360 /**
361 * @brief Function for disabling the specified shortcuts.
362 *
363 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
364 * @param[in] mask Mask of shortcuts to be disabled.
365 */
366 NRF_STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
367 uint32_t mask);
368
369 /**
370 * @brief Function for setting the configuration of PWM shortcuts.
371 *
372 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
373 * @param[in] mask Shortcuts configuration to be set.
374 */
375 NRF_STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
376 uint32_t mask);
377
378 /**
379 * @brief Function for enabling specified interrupts.
380 *
381 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
382 * @param[in] mask Mask of interrupts to be enabled.
383 * Use @ref nrf_pwm_int_mask_t values for bit masking.
384 */
385 NRF_STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
386 uint32_t mask);
387
388 /**
389 * @brief Function for disabling specified interrupts.
390 *
391 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
392 * @param[in] mask Mask of interrupts to be disabled.
393 * Use @ref nrf_pwm_int_mask_t values for bit masking.
394 */
395 NRF_STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
396 uint32_t mask);
397
398 /**
399 * @brief Function for setting the configuration of PWM interrupts.
400 *
401 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
402 * @param[in] mask Mask of interrupts to be set.
403 * Use @ref nrf_pwm_int_mask_t values for bit masking.
404 */
405 NRF_STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
406 uint32_t mask);
407
408 /**
409 * @brief Function for checking if the specified interrupts are enabled.
410 *
411 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
412 * @param[in] mask Mask of interrupts to be checked.
413 * Use @ref nrf_pwm_int_mask_t values for bit masking.
414 *
415 * @return Mask of enabled interrupts.
416 */
417 NRF_STATIC_INLINE uint32_t nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, uint32_t mask);
418
419 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
420 /**
421 * @brief Function for setting the subscribe configuration for a given
422 * PWM task.
423 *
424 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
425 * @param[in] task Task for which to set the configuration.
426 * @param[in] channel Channel through which to subscribe events.
427 */
428 NRF_STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
429 nrf_pwm_task_t task,
430 uint8_t channel);
431
432 /**
433 * @brief Function for clearing the subscribe configuration for a given
434 * PWM task.
435 *
436 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
437 * @param[in] task Task for which to clear the configuration.
438 */
439 NRF_STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
440 nrf_pwm_task_t task);
441
442 /**
443 * @brief Function for setting the publish configuration for a given
444 * PWM event.
445 *
446 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
447 * @param[in] event Event for which to set the configuration.
448 * @param[in] channel Channel through which to publish the event.
449 */
450 NRF_STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
451 nrf_pwm_event_t event,
452 uint8_t channel);
453
454 /**
455 * @brief Function for clearing the publish configuration for a given
456 * PWM event.
457 *
458 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
459 * @param[in] event Event for which to clear the configuration.
460 */
461 NRF_STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
462 nrf_pwm_event_t event);
463 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
464
465 /**
466 * @brief Function for enabling the PWM peripheral.
467 *
468 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
469 */
470 NRF_STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg);
471
472 /**
473 * @brief Function for disabling the PWM peripheral.
474 *
475 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
476 */
477 NRF_STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg);
478
479 /**
480 * @brief Function for checking if the PWM peripheral is enabled.
481 *
482 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
483 *
484 * @retval true The PWM is enabled.
485 * @retval false The PWM is not enabled.
486 */
487 NRF_STATIC_INLINE bool nrf_pwm_enable_check(NRF_PWM_Type const * p_reg);
488
489 /**
490 * @brief Function for assigning pins to PWM output channels.
491 *
492 * Usage of all PWM output channels is optional. If a given channel is not
493 * needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
494 * number.
495 *
496 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
497 * @param[in] out_pins Array with pin numbers for individual PWM output channels.
498 */
499 NRF_STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
500 uint32_t const out_pins[NRF_PWM_CHANNEL_COUNT]);
501
502 /**
503 * @brief Function for setting pin associated with specified PWM output channel.
504 *
505 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
506 * @param[in] channel PWM output channel.
507 * @param[in] pin PWM output pin associated with specified PWM output channel.
508 */
509 NRF_STATIC_INLINE void nrf_pwm_pin_set(NRF_PWM_Type * p_reg, uint8_t channel, uint32_t pin);
510
511 /**
512 * @brief Function for getting pin selection associated with specified PWM output channel.
513 *
514 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
515 * @param[in] channel PWM output channel.
516 *
517 * @return Pin selection associated with specified PWM output channel.
518 */
519 NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel);
520
521 /**
522 * @brief Function for configuring the PWM peripheral.
523 *
524 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
525 * @param[in] base_clock Base clock frequency.
526 * @param[in] mode Operating mode of the pulse generator counter.
527 * @param[in] top_value Value up to which the pulse generator counter counts.
528 */
529 NRF_STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
530 nrf_pwm_clk_t base_clock,
531 nrf_pwm_mode_t mode,
532 uint16_t top_value);
533
534 /**
535 * @brief Function for defining a sequence of PWM duty cycles.
536 *
537 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
538 * @param[in] seq_id Identifier of the sequence (0 or 1).
539 * @param[in] p_seq Pointer to the sequence definition.
540 */
541 NRF_STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
542 uint8_t seq_id,
543 nrf_pwm_sequence_t const * p_seq);
544
545 /**
546 * @brief Function for modifying the pointer to the duty cycle values
547 * in the specified sequence.
548 *
549 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
550 * @param[in] seq_id Identifier of the sequence (0 or 1).
551 * @param[in] p_values Pointer to an array with duty cycle values.
552 */
553 NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
554 uint8_t seq_id,
555 uint16_t const * p_values);
556
557 /**
558 * @brief Function for modifying the total number of duty cycle values
559 * in the specified sequence.
560 *
561 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
562 * @param[in] seq_id Identifier of the sequence (0 or 1).
563 * @param[in] length Number of duty cycle values (in 16-bit half words).
564 */
565 NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
566 uint8_t seq_id,
567 uint16_t length);
568
569 /**
570 * @brief Function for modifying the additional number of PWM periods spent
571 * on each duty cycle value in the specified sequence.
572 *
573 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
574 * @param[in] seq_id Identifier of the sequence (0 or 1).
575 * @param[in] refresh Number of additional PWM periods for each duty cycle value.
576 */
577 NRF_STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
578 uint8_t seq_id,
579 uint32_t refresh);
580
581 /**
582 * @brief Function for modifying the additional time added after the sequence
583 * is played.
584 *
585 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
586 * @param[in] seq_id Identifier of the sequence (0 or 1).
587 * @param[in] end_delay Number of PWM periods added at the end of the sequence.
588 */
589 NRF_STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
590 uint8_t seq_id,
591 uint32_t end_delay);
592
593 /**
594 * @brief Function for setting the mode of loading sequence data from RAM
595 * and advancing the sequence.
596 *
597 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
598 * @param[in] dec_load Mode of loading sequence data from RAM.
599 * @param[in] dec_step Mode of advancing the active sequence.
600 */
601 NRF_STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
602 nrf_pwm_dec_load_t dec_load,
603 nrf_pwm_dec_step_t dec_step);
604
605 /**
606 * @brief Function for setting the number of times the sequence playback
607 * should be performed.
608 *
609 * This function applies to two-sequence playback (concatenated sequence 0 and 1).
610 * A single sequence can be played back only once.
611 *
612 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
613 * @param[in] loop_count Number of times to perform the sequence playback.
614 */
615 NRF_STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg, uint16_t loop_count);
616
617 /**
618 * @brief Function for getting the specified PWM SEQSTART task.
619 *
620 * @param[in] seq_id Sequence index.
621 *
622 * @return The specified PWM SEQSTART task.
623 */
624 NRF_STATIC_INLINE nrf_pwm_task_t nrf_pwm_seqstart_task_get(uint8_t seq_id);
625
626 /**
627 * @brief Function for getting the specified PWM SEQEND event.
628 *
629 * @param[in] seq_id Sequence index.
630 *
631 * @return The specified PWM SEQEND event.
632 */
633 NRF_STATIC_INLINE nrf_pwm_event_t nrf_pwm_seqend_event_get(uint8_t seq_id);
634
635 #if NRF_PWM_HAS_IDLEOUT
636 /**
637 * @brief Function for setting the output value of specified channel while
638 * PDM is idle.
639 *
640 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
641 * @param[in] channel PWM output channel.
642 * @param[in] value If true, idle output will be high. If false, it will be low.
643 */
644 NRF_STATIC_INLINE void nrf_pwm_channel_idle_set(NRF_PWM_Type * p_reg,
645 uint8_t channel,
646 bool value);
647
648 /**
649 * @brief Function for getting the output value of specified channel while
650 * PDM is idle.
651 *
652 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
653 * @param[in] channel PWM output channel.
654 *
655 * @retval true Idle output value is high.
656 * @retval false Idle output value is low.
657 */
658 NRF_STATIC_INLINE bool nrf_pwm_channel_idle_get(NRF_PWM_Type const * p_reg,
659 uint8_t channel);
660 #endif // NRF_PWM_HAS_IDLEOUT
661
662 #ifndef NRF_DECLARE_ONLY
663
nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)664 NRF_STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
665 nrf_pwm_task_t task)
666 {
667 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
668 }
669
nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_task_t task)670 NRF_STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
671 nrf_pwm_task_t task)
672 {
673 return ((uint32_t)p_reg + (uint32_t)task);
674 }
675
nrf_pwm_event_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)676 NRF_STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
677 nrf_pwm_event_t event)
678 {
679 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
680 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
681 }
682
nrf_pwm_event_check(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)683 NRF_STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
684 nrf_pwm_event_t event)
685 {
686 return nrf_event_check(p_reg, event);
687 }
688
nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)689 NRF_STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
690 nrf_pwm_event_t event)
691 {
692 return ((uint32_t)p_reg + (uint32_t)event);
693 }
694
nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,uint32_t mask)695 NRF_STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg, uint32_t mask)
696 {
697 p_reg->SHORTS |= mask;
698 }
699
nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,uint32_t mask)700 NRF_STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg, uint32_t mask)
701 {
702 p_reg->SHORTS &= ~(mask);
703 }
704
nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,uint32_t mask)705 NRF_STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg, uint32_t mask)
706 {
707 p_reg->SHORTS = mask;
708 }
709
nrf_pwm_int_enable(NRF_PWM_Type * p_reg,uint32_t mask)710 NRF_STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg, uint32_t mask)
711 {
712 p_reg->INTENSET = mask;
713 }
714
nrf_pwm_int_disable(NRF_PWM_Type * p_reg,uint32_t mask)715 NRF_STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg, uint32_t mask)
716 {
717 p_reg->INTENCLR = mask;
718 }
719
nrf_pwm_int_set(NRF_PWM_Type * p_reg,uint32_t mask)720 NRF_STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg, uint32_t mask)
721 {
722 p_reg->INTEN = mask;
723 }
724
nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,uint32_t mask)725 NRF_STATIC_INLINE uint32_t nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, uint32_t mask)
726 {
727 return p_reg->INTENSET & mask;
728 }
729
730 #if defined(DPPI_PRESENT)
nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,nrf_pwm_task_t task,uint8_t channel)731 NRF_STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
732 nrf_pwm_task_t task,
733 uint8_t channel)
734 {
735 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
736 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
737 }
738
nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)739 NRF_STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
740 nrf_pwm_task_t task)
741 {
742 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
743 }
744
nrf_pwm_publish_set(NRF_PWM_Type * p_reg,nrf_pwm_event_t event,uint8_t channel)745 NRF_STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
746 nrf_pwm_event_t event,
747 uint8_t channel)
748 {
749 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
750 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
751 }
752
nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)753 NRF_STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
754 nrf_pwm_event_t event)
755 {
756 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
757 }
758 #endif // defined(DPPI_PRESENT)
759
nrf_pwm_enable(NRF_PWM_Type * p_reg)760 NRF_STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg)
761 {
762 p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
763 }
764
nrf_pwm_disable(NRF_PWM_Type * p_reg)765 NRF_STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg)
766 {
767 p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
768 }
769
nrf_pwm_enable_check(NRF_PWM_Type const * p_reg)770 NRF_STATIC_INLINE bool nrf_pwm_enable_check(NRF_PWM_Type const * p_reg)
771 {
772 return p_reg->ENABLE == PWM_ENABLE_ENABLE_Enabled;
773 }
774
nrf_pwm_pins_set(NRF_PWM_Type * p_reg,uint32_t const out_pins[NRF_PWM_CHANNEL_COUNT])775 NRF_STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
776 uint32_t const out_pins[NRF_PWM_CHANNEL_COUNT])
777 {
778 uint8_t i;
779 for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
780 {
781 p_reg->PSEL.OUT[i] = out_pins[i];
782 }
783 }
784
nrf_pwm_pin_set(NRF_PWM_Type * p_reg,uint8_t channel,uint32_t pin)785 NRF_STATIC_INLINE void nrf_pwm_pin_set(NRF_PWM_Type * p_reg, uint8_t channel, uint32_t pin)
786 {
787 NRFX_ASSERT(channel < NRF_PWM_CHANNEL_COUNT);
788 p_reg->PSEL.OUT[channel] = pin;
789 }
790
nrf_pwm_pin_get(NRF_PWM_Type const * p_reg,uint8_t channel)791 NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel)
792 {
793 NRFX_ASSERT(channel < NRF_PWM_CHANNEL_COUNT);
794 return p_reg->PSEL.OUT[channel];
795 }
796
nrf_pwm_configure(NRF_PWM_Type * p_reg,nrf_pwm_clk_t base_clock,nrf_pwm_mode_t mode,uint16_t top_value)797 NRF_STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
798 nrf_pwm_clk_t base_clock,
799 nrf_pwm_mode_t mode,
800 uint16_t top_value)
801 {
802 NRFX_ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
803
804 p_reg->PRESCALER = base_clock;
805 p_reg->MODE = mode;
806 p_reg->COUNTERTOP = top_value;
807 }
808
nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,uint8_t seq_id,nrf_pwm_sequence_t const * p_seq)809 NRF_STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
810 uint8_t seq_id,
811 nrf_pwm_sequence_t const * p_seq)
812 {
813 NRFX_ASSERT(p_seq != NULL);
814
815 nrf_pwm_seq_ptr_set( p_reg, seq_id, p_seq->values.p_raw);
816 nrf_pwm_seq_cnt_set( p_reg, seq_id, p_seq->length);
817 nrf_pwm_seq_refresh_set( p_reg, seq_id, p_seq->repeats);
818 nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay);
819 }
820
nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t const * p_values)821 NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
822 uint8_t seq_id,
823 uint16_t const * p_values)
824 {
825 NRFX_ASSERT(seq_id <= 1);
826 NRFX_ASSERT(p_values != NULL);
827 #if NRF_PWM_HAS_DMA_REG
828 p_reg->DMA.SEQ[seq_id].PTR = (uint32_t)p_values;
829 #else
830 p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
831 #endif
832 }
833
nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t length)834 NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
835 uint8_t seq_id,
836 uint16_t length)
837 {
838 NRFX_ASSERT(seq_id <= 1);
839 NRFX_ASSERT(length != 0);
840 #if NRF_PWM_HAS_DMA_REG
841 NRFX_ASSERT(length * sizeof(uint16_t) <= PWM_DMA_SEQ_MAXCNT_MAXCNT_Msk);
842 p_reg->DMA.SEQ[seq_id].MAXCNT = length * sizeof(uint16_t);
843 #else
844 NRFX_ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
845 p_reg->SEQ[seq_id].CNT = length;
846 #endif
847 }
848
nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t refresh)849 NRF_STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
850 uint8_t seq_id,
851 uint32_t refresh)
852 {
853 NRFX_ASSERT(seq_id <= 1);
854 NRFX_ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
855 p_reg->SEQ[seq_id].REFRESH = refresh;
856 }
857
nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t end_delay)858 NRF_STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
859 uint8_t seq_id,
860 uint32_t end_delay)
861 {
862 NRFX_ASSERT(seq_id <= 1);
863 NRFX_ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
864 p_reg->SEQ[seq_id].ENDDELAY = end_delay;
865 }
866
nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,nrf_pwm_dec_load_t dec_load,nrf_pwm_dec_step_t dec_step)867 NRF_STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
868 nrf_pwm_dec_load_t dec_load,
869 nrf_pwm_dec_step_t dec_step)
870 {
871 p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
872 ((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
873 }
874
nrf_pwm_loop_set(NRF_PWM_Type * p_reg,uint16_t loop_count)875 NRF_STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
876 uint16_t loop_count)
877 {
878 p_reg->LOOP = loop_count;
879 }
880
nrf_pwm_seqstart_task_get(uint8_t seq_id)881 NRF_STATIC_INLINE nrf_pwm_task_t nrf_pwm_seqstart_task_get(uint8_t seq_id)
882 {
883 NRFX_ASSERT(seq_id <= 1);
884 #if NRF_PWM_HAS_DMA_TASKS_EVENTS
885 return (nrf_pwm_task_t)NRFX_OFFSETOF(NRF_PWM_Type, TASKS_DMA.SEQ[seq_id].START);
886 #else
887 return (nrf_pwm_task_t)NRFX_OFFSETOF(NRF_PWM_Type, TASKS_SEQSTART[seq_id]);
888 #endif
889 }
890
nrf_pwm_seqend_event_get(uint8_t seq_id)891 NRF_STATIC_INLINE nrf_pwm_event_t nrf_pwm_seqend_event_get(uint8_t seq_id)
892 {
893 NRFX_ASSERT(seq_id <= 1);
894 #if NRF_PWM_HAS_DMA_TASKS_EVENTS
895 return (nrf_pwm_event_t)NRFX_OFFSETOF(NRF_PWM_Type, EVENTS_DMA.SEQ[seq_id].END);
896 #else
897 return (nrf_pwm_event_t)NRFX_OFFSETOF(NRF_PWM_Type, EVENTS_SEQEND[seq_id]);
898 #endif
899 }
900
901 #if NRF_PWM_HAS_IDLEOUT
nrf_pwm_channel_idle_set(NRF_PWM_Type * p_reg,uint8_t channel,bool value)902 NRF_STATIC_INLINE void nrf_pwm_channel_idle_set(NRF_PWM_Type * p_reg,
903 uint8_t channel,
904 bool value)
905 {
906 if (value)
907 {
908 p_reg->IDLEOUT |= (1UL << channel);
909 }
910 else
911 {
912 p_reg->IDLEOUT &= ~(1UL << channel);
913 }
914 }
915
nrf_pwm_channel_idle_get(NRF_PWM_Type const * p_reg,uint8_t channel)916 NRF_STATIC_INLINE bool nrf_pwm_channel_idle_get(NRF_PWM_Type const * p_reg,
917 uint8_t channel)
918 {
919 return ((p_reg->IDLEOUT >> channel) & 1UL);
920 }
921 #endif // NRF_PWM_HAS_IDLEOUT
922
923 #endif // NRF_DECLARE_ONLY
924
925 /** @} */
926
927 #ifdef __cplusplus
928 }
929 #endif
930
931 #endif // NRF_PWM_H__
932
933
