1 /*
2 * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_GPIO_H__
35 #define NRF_GPIO_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #ifndef NRF_P0
44 #define NRF_P0 NRF_GPIO
45 #endif
46
47 #define GPIO_PORT_NUM(periph_name, prefix, i, _) i,
48 #define GPIO_REG(periph_name, prefix, i, _) NRFX_CONCAT(NRF_, periph_name, prefix, i),
49 #define GPIO_NUM_OF_PINS(periph_name, prefix, i, _) NRFX_CONCAT(periph_name, prefix, i, _PIN_NUM)
50
51 #define GPIO_PORT_NUM_LIST {NRFX_FOREACH_PRESENT(P, GPIO_PORT_NUM, (), (), _)}
52 #define GPIO_REG_LIST {NRFX_FOREACH_PRESENT(P, GPIO_REG, (), (), _)}
53 #define NUMBER_OF_PINS {NRFX_FOREACH_PRESENT(P, GPIO_NUM_OF_PINS, (+), (0), _)}
54
55 #if !defined(GPIO_REG_LIST)
56 #error "Not supported."
57 #endif
58
59 #if defined(GPIO_PIN_CNF_DRIVE0_Msk)
60 #define GPIO_PIN_CNF_DRIVE1_OFFSET (GPIO_PIN_CNF_DRIVE1_Pos - GPIO_PIN_CNF_DRIVE0_Pos)
61 #endif
62
63 #if defined(NRF52820_XXAA)
64 #include <nrf_erratas.h>
65 #endif
66
67 /*
68 * Macro for generating case code blocks that return token NRF_<periph_name><prefix><i>
69 * for case value equal to <i>.
70 *
71 * Used by NRF_INTERNAL_GPIO_PORT_EXTRACT.
72 */
73 #define NRF_INTERNAL_GPIO_PORT_EXTRACT_1(periph_name, prefix, i, port) \
74 case i: \
75 port = NRFX_CONCAT(NRF_, periph_name, prefix, i); \
76 break;
77
78 /*
79 * Macro for generating case code blocks for switch statement used in function nrf_gpio_pin_port_decode.
80 * It allows extracting the port number relative to the decoded pin.
81 */
82 #define NRF_INTERNAL_GPIO_PORT_EXTRACT(port) \
83 NRFX_FOREACH_PRESENT(P, NRF_INTERNAL_GPIO_PORT_EXTRACT_1, (), (), port)
84
85 /*
86 * Macro for generating case code blocks that set mask to <periph_name><prefix><i>_FEATURE_PINS_PRESENT
87 * for case value equal to <i>.
88 *
89 * Used by NRF_INTERNAL_GPIO_PORT_MASK_SET.
90 */
91 #define NRF_INTERNAL_GPIO_PORT_MASK_SET_1(periph_name, prefix, i, mask) \
92 case i: \
93 mask = NRFX_CONCAT(periph_name, prefix, i, _FEATURE_PINS_PRESENT); \
94 break;
95
96 /*
97 * Macro for generating case code blocks for switch statement used in function nrf_gpio_pin_present_check.
98 * It allows setting the mask to a value associated with the specific port.
99 */
100 #define NRF_INTERNAL_GPIO_PORT_MASK_SET(mask) \
101 NRFX_FOREACH_PRESENT(P, NRF_INTERNAL_GPIO_PORT_MASK_SET_1, (), (), mask)
102
103 /**
104 * @defgroup nrf_gpio_hal GPIO HAL
105 * @{
106 * @ingroup nrf_gpio
107 * @brief Hardware access layer for managing the GPIO peripheral.
108 */
109
110 #if defined(GPIO_LATCH_PIN0_Msk) || defined(__NRFX_DOXYGEN__)
111 /** @brief Symbol indicating whether the functionality of latching GPIO state change is present. */
112 #define NRF_GPIO_LATCH_PRESENT
113 #endif
114
115 #if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(GPIO_PIN_CNF_CTRLSEL_Msk) \
116 || defined(__NRFX_DOXYGEN__)
117 /** @brief Presence of MCU/Subsystem control selection. */
118 #define NRF_GPIO_HAS_SEL 1
119 #else
120 #define NRF_GPIO_HAS_SEL 0
121 #endif
122
123 #if defined(GPIO_PIN_CNF_CTRLSEL_Msk) || defined(__NRFX_DOXYGEN__)
124 /** @brief Presence of MCU/Subsystem control selection for multiple peripherals. */
125 #define NRF_GPIO_HAS_MULTIPERIPH_SEL 1
126 #else
127 #define NRF_GPIO_HAS_MULTIPERIPH_SEL 0
128 #endif
129
130 #if defined(GPIO_PIN_CNF_CLOCKPIN_Msk) || defined(__NRFX_DOXYGEN__)
131 /** @brief Presence of clock pin enable. */
132 #define NRF_GPIO_HAS_CLOCKPIN 1
133 #else
134 #define NRF_GPIO_HAS_CLOCKPIN 0
135 #endif
136
137 #if defined(GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk) || defined(__NRFX_DOXYGEN__)
138 /** @brief Presence of drive control for impedance. */
139 #define NRF_GPIO_HAS_PORT_IMPEDANCE 1
140 #else
141 #define NRF_GPIO_HAS_PORT_IMPEDANCE 0
142 #endif
143
144 #if defined(GPIO_RETAIN_ResetValue) || defined(__NRFX_DOXYGEN__)
145 /** @brief Presence of register retention. */
146 #define NRF_GPIO_HAS_RETENTION 1
147 #else
148 #define NRF_GPIO_HAS_RETENTION 0
149 #endif
150
151 #if defined(GPIO_DETECTMODE_DETECTMODE_Msk) || defined(__NRFX_DOXYGEN__)
152 /** @brief Presence of detect mode. */
153 #define NRF_GPIO_HAS_DETECT_MODE 1
154 #else
155 #define NRF_GPIO_HAS_DETECT_MODE 0
156 #endif
157
158 /** @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. */
159 #define NRF_GPIO_PIN_MAP(port, pin) NRF_PIN_PORT_TO_PIN_NUMBER(pin, port)
160
161 #if NRF_GPIO_HAS_PORT_IMPEDANCE
162 /** @brief Mask of all impedances. */
163 #define NRF_GPIO_PORT_IMPEDANCE_ALL_MASK (GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk | \
164 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Msk | \
165 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Msk | \
166 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Msk | \
167 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Msk | \
168 GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Msk)
169 #endif
170
171 /** @brief Pin direction definitions. */
172 typedef enum
173 {
174 NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input.
175 NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output.
176 } nrf_gpio_pin_dir_t;
177
178 /** @brief Connection of input buffer. */
179 typedef enum
180 {
181 NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer.
182 NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer.
183 } nrf_gpio_pin_input_t;
184
185 /**
186 * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin
187 * configuration.
188 */
189 typedef enum
190 {
191 NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled.
192 NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled.
193 NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled.
194 } nrf_gpio_pin_pull_t;
195
196 /** @brief Enumerator used for selecting output drive mode. */
197 typedef enum
198 {
199 #if defined(GPIO_PIN_CNF_DRIVE_Msk) || defined(__NRFX_DOXYGEN__)
200 NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< Standard '0', standard '1'.
201 NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< High drive '0', standard '1'.
202 NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< Standard '0', high drive '1'.
203 NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< High drive '0', high drive '1'.
204 NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< Disconnect '0' standard '1'.
205 NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< Disconnect '0', high drive '1'.
206 NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< Standard '0', disconnect '1'.
207 NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< High drive '0', disconnect '1'.
208 #if defined(GPIO_PIN_CNF_DRIVE_E0S1) || defined(__NRFX_DOXYGEN__)
209 NRF_GPIO_PIN_E0S1 = GPIO_PIN_CNF_DRIVE_E0S1, ///< Extra high drive '0', standard '1'.
210 #endif
211 #if defined(GPIO_PIN_CNF_DRIVE_S0E1) || defined(__NRFX_DOXYGEN__)
212 NRF_GPIO_PIN_S0E1 = GPIO_PIN_CNF_DRIVE_S0E1, ///< Standard '0', extra high drive '1'.
213 #endif
214 #if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(__NRFX_DOXYGEN__)
215 NRF_GPIO_PIN_E0E1 = GPIO_PIN_CNF_DRIVE_E0E1, ///< Extra high drive '0', extra high drive '1'.
216 #endif
217 #if defined(GPIO_PIN_CNF_DRIVE_E0H1) || defined(__NRFX_DOXYGEN__)
218 NRF_GPIO_PIN_E0H1 = GPIO_PIN_CNF_DRIVE_E0H1, ///< Extra high drive '0', high drive '1'.
219 #endif
220 #if defined(GPIO_PIN_CNF_DRIVE_H0E1) || defined(__NRFX_DOXYGEN__)
221 NRF_GPIO_PIN_H0E1 = GPIO_PIN_CNF_DRIVE_H0E1, ///< High drive '0', extra high drive '1'.
222 #endif
223 #if defined(GPIO_PIN_CNF_DRIVE_D0E1) || defined(__NRFX_DOXYGEN__)
224 NRF_GPIO_PIN_D0E1 = GPIO_PIN_CNF_DRIVE_D0E1, ///< Disconnect '0', extra high drive '1'.
225 #endif
226 #if defined(GPIO_PIN_CNF_DRIVE_E0D1) || defined(__NRFX_DOXYGEN__)
227 NRF_GPIO_PIN_E0D1 = GPIO_PIN_CNF_DRIVE_E0D1, ///< Extra high drive '0', disconnect '1'.
228 #endif
229 #else
230 NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE0_S0 |
231 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
232 NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE0_H0 |
233 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
234 NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE0_S0 |
235 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
236 NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE0_H0 |
237 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
238 NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE0_D0 |
239 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
240 NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE0_D0 |
241 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
242 NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE0_S0 |
243 (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
244 NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE0_H0 |
245 (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
246 NRF_GPIO_PIN_E0S1 = GPIO_PIN_CNF_DRIVE0_E0 |
247 (GPIO_PIN_CNF_DRIVE1_S1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
248 NRF_GPIO_PIN_S0E1 = GPIO_PIN_CNF_DRIVE0_S0 |
249 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
250 NRF_GPIO_PIN_E0E1 = GPIO_PIN_CNF_DRIVE0_E0 |
251 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
252 NRF_GPIO_PIN_E0H1 = GPIO_PIN_CNF_DRIVE0_E0 |
253 (GPIO_PIN_CNF_DRIVE1_H1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
254 NRF_GPIO_PIN_H0E1 = GPIO_PIN_CNF_DRIVE0_H0 |
255 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
256 NRF_GPIO_PIN_D0E1 = GPIO_PIN_CNF_DRIVE0_D0 |
257 (GPIO_PIN_CNF_DRIVE1_E1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
258 NRF_GPIO_PIN_E0D1 = GPIO_PIN_CNF_DRIVE0_E0 |
259 (GPIO_PIN_CNF_DRIVE1_D1 << GPIO_PIN_CNF_DRIVE1_OFFSET),
260 #endif // defined(GPIO_PIN_CNF_DRIVE_Msk) || defined(__NRFX_DOXYGEN__)
261 } nrf_gpio_pin_drive_t;
262
263 /** @brief Enumerator used for selecting the pin to sense high or low level on the pin input. */
264 typedef enum
265 {
266 NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled.
267 NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level.
268 NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level.
269 } nrf_gpio_pin_sense_t;
270
271 #if NRF_GPIO_HAS_SEL
272 /** @brief Enumerator used for selecting the MCU/Subsystem to control the specified pin. */
273 typedef enum
274 {
275 #if defined(GPIO_PIN_CNF_MCUSEL_Msk) || defined(__NRFX_DOXYGEN__)
276 NRF_GPIO_PIN_SEL_APP = GPIO_PIN_CNF_MCUSEL_AppMCU, ///< Pin controlled by Application MCU.
277 NRF_GPIO_PIN_SEL_NETWORK = GPIO_PIN_CNF_MCUSEL_NetworkMCU, ///< Pin controlled by Network MCU.
278 NRF_GPIO_PIN_SEL_PERIPHERAL = GPIO_PIN_CNF_MCUSEL_Peripheral, ///< Pin controlled by dedicated peripheral.
279 NRF_GPIO_PIN_SEL_TND = GPIO_PIN_CNF_MCUSEL_TND, ///< Pin controlled by Trace and Debug Subsystem.
280 #endif
281 #if defined(NRF_GPIO_PIN_SEL_EXT)
282 NRF_GPIO_PIN_SEL_EXT
283 #endif
284 } nrf_gpio_pin_sel_t;
285 #endif // NRF_GPIO_HAS_SEL
286
287 #if NRF_GPIO_HAS_PORT_IMPEDANCE
288 /** @brief Port impedance enable mask. */
289 typedef enum
290 {
291 NRF_GPIO_PORT_IMPEDANCE_50_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk, //< Enable 50 Ohm impedance.
292 NRF_GPIO_PORT_IMPEDANCE_100_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Msk, //< Enable 100 Ohm impedance.
293 NRF_GPIO_PORT_IMPEDANCE_200_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Msk, //< Enable 200 Ohm impedance.
294 NRF_GPIO_PORT_IMPEDANCE_400_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Msk, //< Enable 400 Ohm impedance.
295 NRF_GPIO_PORT_IMPEDANCE_800_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Msk, //< Enable 800 Ohm impedance.
296 NRF_GPIO_PORT_IMPEDANCE_1600_MASK = GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Msk, //< Enable 1600 Ohm impedance.
297 } nrf_gpio_port_impedance_mask_t;
298 #endif
299
300 #if NRF_GPIO_HAS_RETENTION
301 /** @brief Retention enable mask. */
302 typedef enum
303 {
304 NRF_GPIO_RETAIN_EXT ///< Reserved. For internal use only.
305 } nrf_gpio_retain_mask_t;
306 #endif
307
308 /**
309 * @brief Function for configuring the GPIO pin range as output pins with normal drive strength.
310 * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
311 *
312 * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output.
313 * Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
314 *
315 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
316 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
317 */
318 NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end);
319
320 /**
321 * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details.
322 * This function can be used to configure pin range as simple input.
323 *
324 * @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input.
325 * Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
326 *
327 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
328 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
329 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
330 */
331 NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
332 uint32_t pin_range_end,
333 nrf_gpio_pin_pull_t pull_config);
334
335 /**
336 * @brief Pin configuration function.
337 *
338 * The main pin configuration function.
339 * This function allows to set any aspect in PIN_CNF register.
340 *
341 * @param pin_number Specifies the pin number.
342 * @param dir Pin direction.
343 * @param input Connect or disconnect the input buffer.
344 * @param pull Pull configuration.
345 * @param drive Drive configuration.
346 * @param sense Pin sensing mechanism.
347 */
348 NRF_STATIC_INLINE void nrf_gpio_cfg(
349 uint32_t pin_number,
350 nrf_gpio_pin_dir_t dir,
351 nrf_gpio_pin_input_t input,
352 nrf_gpio_pin_pull_t pull,
353 nrf_gpio_pin_drive_t drive,
354 nrf_gpio_pin_sense_t sense);
355
356 /**
357 * @brief Function for reconfiguring pin.
358 *
359 * @note This function selectively updates fields in PIN_CNF register. Reconfiguration
360 * is performed in single register write. Fields for which new configuration is
361 * not provided remain unchanged.
362 *
363 * @param pin_number Specifies the pin number.
364 * @param p_dir Pin direction. If NULL, previous setting remains.
365 * @param p_input Connect or disconnect the input buffer. If NULL, previous setting remains.
366 * @param p_pull Pull configuration. If NULL, previous setting remains.
367 * @param p_drive Drive configuration. If NULL, previous setting remains.
368 * @param p_sense Pin sensing mechanism. If NULL, previous setting remains.
369 */
370 NRF_STATIC_INLINE void nrf_gpio_reconfigure(uint32_t pin_number,
371 const nrf_gpio_pin_dir_t * p_dir,
372 const nrf_gpio_pin_input_t * p_input,
373 const nrf_gpio_pin_pull_t * p_pull,
374 const nrf_gpio_pin_drive_t * p_drive,
375 const nrf_gpio_pin_sense_t * p_sense);
376
377 /**
378 * @brief Function for configuring the given GPIO pin number as output, hiding inner details.
379 * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
380 *
381 * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
382 *
383 * @param pin_number Specifies the pin number.
384 */
385 NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
386
387 /**
388 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
389 * This function can be used to configure a pin as simple input.
390 *
391 * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
392 *
393 * @param pin_number Specifies the pin number.
394 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
395 */
396 NRF_STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config);
397
398 /**
399 * @brief Function for resetting pin configuration to its default state.
400 *
401 * @param pin_number Specifies the pin number.
402 */
403 NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number);
404
405 /**
406 * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected.
407 *
408 * @param pin_number Specifies the pin number.
409 *
410 */
411 NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number);
412
413 /**
414 * @brief Function for disconnecting input for the given GPIO.
415 *
416 * @param pin_number Specifies the pin number.
417 */
418 NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number);
419
420 /**
421 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
422 * This function can be used to configure pin range as simple input.
423 * Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable.
424 *
425 * @param pin_number Specifies the pin number.
426 * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high).
427 * @param sense_config Sense level of the pin (no sense, sense low, or sense high).
428 */
429 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
430 nrf_gpio_pin_pull_t pull_config,
431 nrf_gpio_pin_sense_t sense_config);
432
433 /**
434 * @brief Function for configuring sense level for the given GPIO.
435 *
436 * @param pin_number Specifies the pin number.
437 * @param sense_config Sense configuration.
438 */
439 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number,
440 nrf_gpio_pin_sense_t sense_config);
441
442 /**
443 * @brief Function for setting the direction for a GPIO pin.
444 *
445 * @param pin_number Specifies the pin number for which to set the direction.
446 * @param direction Specifies the direction.
447 */
448 NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction);
449
450 /**
451 * @brief Function for setting a GPIO pin.
452 *
453 * @param pin_number Specifies the pin number to be set.
454 */
455 NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
456
457 /**
458 * @brief Function for clearing a GPIO pin.
459 *
460 * @param pin_number Specifies the pin number to clear.
461 */
462 NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
463
464 /**
465 * @brief Function for toggling a GPIO pin.
466 *
467 * @param pin_number Specifies the pin number to toggle.
468 */
469 NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
470
471 /**
472 * @brief Function for writing a value to a GPIO pin.
473 *
474 * @param pin_number Specifies the pin number to write.
475 * @param value Specifies the value to be written to the pin.
476 * @arg 0 Clears the pin.
477 * @arg >=1 Sets the pin.
478 */
479 NRF_STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
480
481 /**
482 * @brief Function for reading the input level of a GPIO pin.
483 *
484 * If the value returned by this function is to be valid, the pin's input buffer must be connected.
485 *
486 * @param pin_number Specifies the pin number to read.
487 *
488 * @return 0 if the pin input level is low. Positive value if the pin is high.
489 */
490 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number);
491
492 /**
493 * @brief Function for reading the output level of a GPIO pin.
494 *
495 * @param pin_number Specifies the pin number to read.
496 *
497 * @return 0 if the pin output level is low. Positive value if pin output is high.
498 */
499 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number);
500
501 /**
502 * @brief Function for reading the sense configuration of a GPIO pin.
503 *
504 * @param pin_number Specifies the pin number to read.
505 *
506 * @return Sense configuration.
507 */
508 NRF_STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
509
510 /**
511 * @brief Function for reading the direction configuration of a GPIO pin.
512 *
513 * @param pin_number Specifies the pin number to read.
514 *
515 * @return Direction configuration.
516 */
517 NRF_STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number);
518
519 /**
520 * @brief Function for reading the status of GPIO pin input buffer.
521 *
522 * @param pin_number Pin number to be read.
523 *
524 * @retval Input buffer configuration.
525 */
526 NRF_STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number);
527
528 /**
529 * @brief Function for reading the pull configuration of a GPIO pin.
530 *
531 * @param pin_number Specifies the pin number to read.
532 *
533 * @retval Pull configuration.
534 */
535 NRF_STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number);
536
537 /**
538 * @brief Function for setting output direction on the selected pins on the given port.
539 *
540 * @param p_reg Pointer to the structure of registers of the peripheral.
541 * @param out_mask Mask specifying the pins to set as output.
542 */
543 NRF_STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask);
544
545 /**
546 * @brief Function for setting input direction on selected pins on a given port.
547 *
548 * @param p_reg Pointer to the structure of registers of the peripheral.
549 * @param in_mask Mask that specifies the pins to be set as input.
550 */
551 NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask);
552
553 /**
554 * @brief Function for writing the direction configuration of the GPIO pins in the given port.
555 *
556 * @warning This register is retained when retention is enabled.
557 *
558 * @param p_reg Pointer to the structure of registers of the peripheral.
559 * @param dir_mask Mask that specifies the direction of pins. Bit set means that the given pin is configured as output.
560 */
561 NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask);
562
563 /**
564 * @brief Function for reading the direction configuration of a GPIO port.
565 *
566 * @warning This register is retained when retention is enabled.
567 *
568 * @param p_reg Pointer to the structure of registers of the peripheral.
569 *
570 * @return Pin configuration of the current direction settings. Bit set means that the given pin is configured as output.
571 */
572 NRF_STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg);
573
574 /**
575 * @brief Function for reading the input signals of the GPIO pins on the given port.
576 *
577 * @param p_reg Pointer to the peripheral registers structure.
578 *
579 * @return Port input values.
580 */
581 NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg);
582
583 /**
584 * @brief Function for reading the output signals of the GPIO pins on the given port.
585 *
586 * @warning This register is retained when retention is enabled.
587 *
588 * @param p_reg Pointer to the peripheral registers structure.
589 *
590 * @return Port output values.
591 */
592 NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg);
593
594 /**
595 * @brief Function for writing the GPIO pins output on a given port.
596 *
597 * @warning This register is retained when retention is enabled.
598 *
599 * @param p_reg Pointer to the structure of registers of the peripheral.
600 * @param value Output port mask.
601 */
602 NRF_STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value);
603
604 /**
605 * @brief Function for setting high level on selected the GPIO pins on the given port.
606 *
607 * @param p_reg Pointer to the structure of registers of the peripheral.
608 * @param set_mask Mask with pins to be set as logical high level.
609 */
610 NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask);
611
612 /**
613 * @brief Function for setting low level on selected the GPIO pins on the given port.
614 *
615 * @param p_reg Pointer to the structure of registers of the peripheral.
616 * @param clr_mask Mask with pins to be set as logical low level.
617 */
618 NRF_STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask);
619
620 /**
621 * @brief Function for reading pin state of multiple consecutive ports.
622 *
623 * @param start_port Index of the first port to read.
624 * @param length Number of ports to read.
625 * @param p_masks Pointer to output array where port states will be stored.
626 */
627 NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
628 uint32_t length,
629 uint32_t * p_masks);
630
631 #if NRF_GPIO_HAS_PORT_IMPEDANCE
632 /**
633 * @brief Function for setting the impedance matching of the pins on the given port.
634 *
635 * @note Each bit sets certain impedance and have them in parallel when more than one bit is set.
636 * High impedance is set for the pin when all bits are disabled.
637 * When all bits are enabled, the resulting impedance is about 25 Ohm.
638 *
639 * @warning This register is retained when retention is enabled.
640 *
641 * @param p_reg Pointer to the structure of registers of the peripheral.
642 * @param mask Mask of impedances to be set, created using @ref nrf_gpio_port_impedance_mask_t.
643 */
644 NRF_STATIC_INLINE void nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg, uint32_t mask);
645
646 /**
647 * @brief Function for geting the impedance matching of the pins on the given port.
648 *
649 * @warning This register is retained when retention is enabled.
650 *
651 * @param p_reg Pointer to the structure of registers of the peripheral.
652 *
653 * @return Mask of impedances set, created using @ref nrf_gpio_port_impedance_mask_t.
654 */
655 NRF_STATIC_INLINE uint32_t nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg);
656 #endif
657
658 #if NRF_GPIO_HAS_RETENTION
659 /**
660 * @brief Function for setting the retention of the registers.
661 *
662 * @param p_reg Pointer to the structure of registers of the peripheral.
663 * @param mask Mask of retention domains to be enabled, created using @ref nrf_gpio_retain_mask_t.
664 */
665 NRF_STATIC_INLINE void nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg, uint32_t mask);
666
667 /**
668 * @brief Function for geting the retention setting of the registers.
669 *
670 * @param p_reg Pointer to the structure of registers of the peripheral.
671 *
672 * @return Mask of retention domains set, created using @ref nrf_gpio_retain_mask_t.
673 */
674 NRF_STATIC_INLINE uint32_t nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg);
675 #endif
676
677 #if NRF_GPIO_HAS_DETECT_MODE
678 /**
679 * @brief Function for setting the latched detect behaviour.
680 *
681 * @param p_reg Pointer to the structure of registers of the peripheral.
682 * @param enable True if the latched LDETECT behaviour is to be used, false if DETECT is to be
683 * directly connected to PIN DETECT signals.
684 */
685 NRF_STATIC_INLINE void nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg, bool enable);
686
687 /**
688 * @brief Function for checking the latched detect behaviour.
689 *
690 * @param p_reg Pointer to the structure of registers of the peripheral.
691 *
692 * @retval true Latched LDETECT behaviour is used.
693 * @retval false DETECT is directly connected to PIN DETECT signals.
694 */
695 NRF_STATIC_INLINE bool nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg);
696 #endif
697
698 #if defined(NRF_GPIO_LATCH_PRESENT)
699 /**
700 * @brief Function for reading latch state of multiple consecutive ports.
701 *
702 * @warning This register is retained when retention is enabled.
703 *
704 * @param start_port Index of the first port to read.
705 * @param length Number of ports to read.
706 * @param p_masks Pointer to output array where latch states will be stored.
707 */
708 NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
709 uint32_t length,
710 uint32_t * p_masks);
711
712 /**
713 * @brief Function for reading and immediate clearing latch state of multiple consecutive ports.
714 *
715 * @warning This register is retained when retention is enabled.
716 *
717 * @param start_port Index of the first port to read and clear.
718 * @param length Number of ports to read and clear.
719 * @param p_masks Pointer to output array where latch states will be stored.
720 */
721 NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
722 uint32_t length,
723 uint32_t * p_masks);
724
725 /**
726 * @brief Function for reading latch state of single pin.
727 *
728 * @warning This register is retained when retention is enabled.
729 *
730 * @param pin_number Pin number.
731 *
732 * @return 0 if latch is not set. Positive value otherwise.
733 */
734 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
735
736 /**
737 * @brief Function for clearing latch state of a single pin.
738 *
739 * @warning This register is retained when retention is enabled.
740 *
741 * @param pin_number Pin number.
742 */
743 NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
744 #endif // defined(NRF_GPIO_LATCH_PRESENT)
745
746 #if NRF_GPIO_HAS_SEL
747 /**
748 * @brief Function for selecting the MCU or Subsystem to control a GPIO pin.
749 *
750 * @warning This register is retained when retention is enabled.
751 *
752 * @param pin_number Pin_number.
753 * @param ctrl MCU/Subsystem to control the pin.
754 */
755 NRF_STATIC_INLINE void nrf_gpio_pin_control_select(uint32_t pin_number, nrf_gpio_pin_sel_t ctrl);
756 #endif
757
758 #if NRF_GPIO_HAS_CLOCKPIN
759 /**
760 * @brief Function for setting whether the clock should be enabled for the specified GPIO pin.
761 *
762 * @warning This register is retained when retention is enabled.
763 *
764 * @param[in] pin_number Pin number.
765 * @param[in] enable True if clock is to be enabled, false otherwise.
766 */
767 NRF_STATIC_INLINE void nrf_gpio_pin_clock_set(uint32_t pin_number, bool enable);
768
769 /**
770 * @brief Function for getting the clock enable setting for the specified GPIO pin.
771 *
772 * @warning This register is retained when retention is enabled.
773 *
774 * @param[in] pin_number Pin number.
775 *
776 * @retval true Clock is enabled.
777 * @retval false Clock is disabled.
778 */
779 NRF_STATIC_INLINE bool nrf_gpio_pin_clock_check(uint32_t pin_number);
780 #endif
781
782 /**
783 * @brief Function for checking if provided pin is present on the MCU.
784 *
785 * @param[in] pin_number Number of the pin to be checked.
786 *
787 * @retval true Pin is present.
788 * @retval false Pin is not present.
789 */
790 NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number);
791
792 /**
793 * @brief Function for extracting port number and the relative pin number
794 * from the absolute pin number.
795 *
796 * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number
797 * that is relative to the port.
798 *
799 * @return Port number.
800 */
801 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin);
802
803 #ifndef NRF_DECLARE_ONLY
804
805 /**
806 * @brief Function for extracting port and the relative pin number from the absolute pin number.
807 *
808 * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number
809 * that is relative to the port.
810 *
811 * @return Pointer to port register set.
812 */
nrf_gpio_pin_port_decode(uint32_t * p_pin)813 NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin)
814 {
815 NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
816
817 NRF_GPIO_Type * p_port = NULL;
818
819 switch (nrf_gpio_pin_port_number_extract(p_pin))
820 {
821 NRF_INTERNAL_GPIO_PORT_EXTRACT(p_port);
822
823 default:
824 NRFX_ASSERT(0);
825 }
826 return p_port;
827 }
828
829
nrf_gpio_range_cfg_output(uint32_t pin_range_start,uint32_t pin_range_end)830 NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
831 {
832 for (; pin_range_start <= pin_range_end; pin_range_start++)
833 {
834 nrf_gpio_cfg_output(pin_range_start);
835 }
836 }
837
838
nrf_gpio_range_cfg_input(uint32_t pin_range_start,uint32_t pin_range_end,nrf_gpio_pin_pull_t pull_config)839 NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
840 uint32_t pin_range_end,
841 nrf_gpio_pin_pull_t pull_config)
842 {
843 for (; pin_range_start <= pin_range_end; pin_range_start++)
844 {
845 nrf_gpio_cfg_input(pin_range_start, pull_config);
846 }
847 }
848
849
nrf_gpio_cfg(uint32_t pin_number,nrf_gpio_pin_dir_t dir,nrf_gpio_pin_input_t input,nrf_gpio_pin_pull_t pull,nrf_gpio_pin_drive_t drive,nrf_gpio_pin_sense_t sense)850 NRF_STATIC_INLINE void nrf_gpio_cfg(
851 uint32_t pin_number,
852 nrf_gpio_pin_dir_t dir,
853 nrf_gpio_pin_input_t input,
854 nrf_gpio_pin_pull_t pull,
855 nrf_gpio_pin_drive_t drive,
856 nrf_gpio_pin_sense_t sense)
857 {
858 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
859 uint32_t cnf = reg->PIN_CNF[pin_number];
860
861 uint32_t to_update = GPIO_PIN_CNF_DIR_Msk |
862 GPIO_PIN_CNF_INPUT_Msk |
863 GPIO_PIN_CNF_PULL_Msk |
864 #if defined(GPIO_PIN_CNF_DRIVE_Msk)
865 GPIO_PIN_CNF_DRIVE_Msk |
866 #else
867 GPIO_PIN_CNF_DRIVE0_Msk |
868 GPIO_PIN_CNF_DRIVE1_Msk |
869 #endif
870 GPIO_PIN_CNF_SENSE_Msk;
871
872 /* Clear fields that will be updated. */
873 cnf &= ~to_update;
874 cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) |
875 ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) |
876 ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) |
877 #if defined(GPIO_PIN_CNF_DRIVE_Pos)
878 ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
879 #else
880 ((uint32_t)drive << GPIO_PIN_CNF_DRIVE0_Pos) |
881 #endif
882 ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos);
883
884 reg->PIN_CNF[pin_number] = cnf;
885 }
886
nrf_gpio_reconfigure(uint32_t pin_number,const nrf_gpio_pin_dir_t * p_dir,const nrf_gpio_pin_input_t * p_input,const nrf_gpio_pin_pull_t * p_pull,const nrf_gpio_pin_drive_t * p_drive,const nrf_gpio_pin_sense_t * p_sense)887 NRF_STATIC_INLINE void nrf_gpio_reconfigure(uint32_t pin_number,
888 const nrf_gpio_pin_dir_t * p_dir,
889 const nrf_gpio_pin_input_t * p_input,
890 const nrf_gpio_pin_pull_t * p_pull,
891 const nrf_gpio_pin_drive_t * p_drive,
892 const nrf_gpio_pin_sense_t * p_sense)
893 {
894 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
895 uint32_t cnf = reg->PIN_CNF[pin_number];
896 uint32_t to_update = (p_dir ? GPIO_PIN_CNF_DIR_Msk : 0) |
897 (p_input ? GPIO_PIN_CNF_INPUT_Msk : 0) |
898 (p_pull ? GPIO_PIN_CNF_PULL_Msk : 0) |
899 #if defined(GPIO_PIN_CNF_DRIVE_Msk)
900 (p_drive ? GPIO_PIN_CNF_DRIVE_Msk : 0) |
901 #else
902 (p_drive ? (GPIO_PIN_CNF_DRIVE0_Msk | GPIO_PIN_CNF_DRIVE1_Msk) : 0) |
903 #endif
904 (p_sense ? GPIO_PIN_CNF_SENSE_Msk : 0);
905
906 /* Clear fields that will be updated. */
907 cnf &= ~to_update;
908 cnf |= ((uint32_t)(p_dir ? *p_dir : 0) << GPIO_PIN_CNF_DIR_Pos) |
909 ((uint32_t)(p_input ? *p_input : 0) << GPIO_PIN_CNF_INPUT_Pos) |
910 ((uint32_t)(p_pull ? *p_pull : 0) << GPIO_PIN_CNF_PULL_Pos) |
911 #if defined(GPIO_PIN_CNF_DRIVE_Pos)
912 ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE_Pos) |
913 #else
914 ((uint32_t)(p_drive ? *p_drive : 0) << GPIO_PIN_CNF_DRIVE0_Pos) |
915 #endif
916 ((uint32_t)(p_sense ? *p_sense : 0)<< GPIO_PIN_CNF_SENSE_Pos);
917
918 reg->PIN_CNF[pin_number] = cnf;
919 }
920
nrf_gpio_cfg_output(uint32_t pin_number)921 NRF_STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
922 {
923 nrf_gpio_cfg(
924 pin_number,
925 NRF_GPIO_PIN_DIR_OUTPUT,
926 NRF_GPIO_PIN_INPUT_DISCONNECT,
927 NRF_GPIO_PIN_NOPULL,
928 NRF_GPIO_PIN_S0S1,
929 NRF_GPIO_PIN_NOSENSE);
930 }
931
932
nrf_gpio_cfg_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config)933 NRF_STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
934 {
935 nrf_gpio_cfg(
936 pin_number,
937 NRF_GPIO_PIN_DIR_INPUT,
938 NRF_GPIO_PIN_INPUT_CONNECT,
939 pull_config,
940 NRF_GPIO_PIN_S0S1,
941 NRF_GPIO_PIN_NOSENSE);
942 }
943
944
nrf_gpio_cfg_default(uint32_t pin_number)945 NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
946 {
947 nrf_gpio_cfg(
948 pin_number,
949 NRF_GPIO_PIN_DIR_INPUT,
950 NRF_GPIO_PIN_INPUT_DISCONNECT,
951 NRF_GPIO_PIN_NOPULL,
952 NRF_GPIO_PIN_S0S1,
953 NRF_GPIO_PIN_NOSENSE);
954 }
955
956
nrf_gpio_cfg_watcher(uint32_t pin_number)957 NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
958 {
959 nrf_gpio_pin_input_t input = NRF_GPIO_PIN_INPUT_CONNECT;
960
961 nrf_gpio_reconfigure(pin_number, NULL, &input, NULL, NULL, NULL);
962 }
963
964
nrf_gpio_input_disconnect(uint32_t pin_number)965 NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
966 {
967 nrf_gpio_pin_input_t input = NRF_GPIO_PIN_INPUT_DISCONNECT;
968
969 nrf_gpio_reconfigure(pin_number, NULL, &input, NULL, NULL, NULL);
970 }
971
972
nrf_gpio_cfg_sense_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config,nrf_gpio_pin_sense_t sense_config)973 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
974 nrf_gpio_pin_pull_t pull_config,
975 nrf_gpio_pin_sense_t sense_config)
976 {
977 nrf_gpio_cfg(
978 pin_number,
979 NRF_GPIO_PIN_DIR_INPUT,
980 NRF_GPIO_PIN_INPUT_CONNECT,
981 pull_config,
982 NRF_GPIO_PIN_S0S1,
983 sense_config);
984 }
985
986
nrf_gpio_cfg_sense_set(uint32_t pin_number,nrf_gpio_pin_sense_t sense_config)987 NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number,
988 nrf_gpio_pin_sense_t sense_config)
989 {
990 nrf_gpio_reconfigure(pin_number, NULL, NULL, NULL, NULL, &sense_config);
991 }
992
nrf_gpio_pin_dir_set(uint32_t pin_number,nrf_gpio_pin_dir_t direction)993 NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
994 {
995 if (direction == NRF_GPIO_PIN_DIR_INPUT)
996 {
997 nrf_gpio_cfg(
998 pin_number,
999 NRF_GPIO_PIN_DIR_INPUT,
1000 NRF_GPIO_PIN_INPUT_CONNECT,
1001 NRF_GPIO_PIN_NOPULL,
1002 NRF_GPIO_PIN_S0S1,
1003 NRF_GPIO_PIN_NOSENSE);
1004 }
1005 else
1006 {
1007 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1008 reg->DIRSET = (1UL << pin_number);
1009 }
1010 }
1011
1012
nrf_gpio_pin_set(uint32_t pin_number)1013 NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
1014 {
1015 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1016
1017 nrf_gpio_port_out_set(reg, 1UL << pin_number);
1018 }
1019
1020
nrf_gpio_pin_clear(uint32_t pin_number)1021 NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
1022 {
1023 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1024
1025 nrf_gpio_port_out_clear(reg, 1UL << pin_number);
1026 }
1027
1028
nrf_gpio_pin_toggle(uint32_t pin_number)1029 NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
1030 {
1031 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1032 uint32_t pins_state = reg->OUT;
1033
1034 reg->OUTSET = (~pins_state & (1UL << pin_number));
1035 reg->OUTCLR = (pins_state & (1UL << pin_number));
1036 }
1037
1038
nrf_gpio_pin_write(uint32_t pin_number,uint32_t value)1039 NRF_STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
1040 {
1041 if (value == 0)
1042 {
1043 nrf_gpio_pin_clear(pin_number);
1044 }
1045 else
1046 {
1047 nrf_gpio_pin_set(pin_number);
1048 }
1049 }
1050
1051
nrf_gpio_pin_read(uint32_t pin_number)1052 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
1053 {
1054 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1055
1056 return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
1057 }
1058
1059
nrf_gpio_pin_out_read(uint32_t pin_number)1060 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number)
1061 {
1062 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1063
1064 return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL);
1065 }
1066
1067
nrf_gpio_pin_sense_get(uint32_t pin_number)1068 NRF_STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
1069 {
1070 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1071
1072 return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
1073 GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
1074 }
1075
1076
nrf_gpio_pin_dir_get(uint32_t pin_number)1077 NRF_STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number)
1078 {
1079 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1080
1081 return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
1082 GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos);
1083 }
1084
nrf_gpio_pin_input_get(uint32_t pin_number)1085 NRF_STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number)
1086 {
1087 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1088
1089 return (nrf_gpio_pin_input_t)((reg->PIN_CNF[pin_number] &
1090 GPIO_PIN_CNF_INPUT_Msk) >> GPIO_PIN_CNF_INPUT_Pos);
1091 }
1092
nrf_gpio_pin_pull_get(uint32_t pin_number)1093 NRF_STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number)
1094 {
1095 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1096
1097 return (nrf_gpio_pin_pull_t)((reg->PIN_CNF[pin_number] &
1098 GPIO_PIN_CNF_PULL_Msk) >> GPIO_PIN_CNF_PULL_Pos);
1099 }
1100
1101
nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg,uint32_t out_mask)1102 NRF_STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask)
1103 {
1104 p_reg->DIRSET = out_mask;
1105 }
1106
1107
nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg,uint32_t in_mask)1108 NRF_STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask)
1109 {
1110 p_reg->DIRCLR = in_mask;
1111 }
1112
1113
nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg,uint32_t value)1114 NRF_STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value)
1115 {
1116 p_reg->DIR = value;
1117 }
1118
1119
nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)1120 NRF_STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)
1121 {
1122 return p_reg->DIR;
1123 }
1124
1125
nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)1126 NRF_STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)
1127 {
1128 return p_reg->IN;
1129 }
1130
1131
nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)1132 NRF_STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)
1133 {
1134 return p_reg->OUT;
1135 }
1136
1137
nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg,uint32_t value)1138 NRF_STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value)
1139 {
1140 p_reg->OUT = value;
1141 }
1142
1143
nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg,uint32_t set_mask)1144 NRF_STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
1145 {
1146 p_reg->OUTSET = set_mask;
1147 }
1148
1149
nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg,uint32_t clr_mask)1150 NRF_STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask)
1151 {
1152 p_reg->OUTCLR = clr_mask;
1153 }
1154
1155
nrf_gpio_ports_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)1156 NRF_STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port,
1157 uint32_t length,
1158 uint32_t * p_masks)
1159 {
1160 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
1161
1162 NRFX_ASSERT(start_port + length <= GPIO_COUNT);
1163 uint32_t i;
1164
1165 for (i = start_port; i < (start_port + length); i++)
1166 {
1167 *p_masks = nrf_gpio_port_in_read(gpio_regs[i]);
1168 p_masks++;
1169 }
1170 }
1171
1172 #if NRF_GPIO_HAS_PORT_IMPEDANCE
nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg,uint32_t mask)1173 NRF_STATIC_INLINE void nrf_gpio_port_impedance_set(NRF_GPIO_Type * p_reg, uint32_t mask)
1174 {
1175 p_reg->PORTCNF.DRIVECTRL = ((p_reg->PORTCNF.DRIVECTRL & ~NRF_GPIO_PORT_IMPEDANCE_ALL_MASK) |
1176 (mask & NRF_GPIO_PORT_IMPEDANCE_ALL_MASK));
1177 }
1178
nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg)1179 NRF_STATIC_INLINE uint32_t nrf_gpio_port_impedance_get(NRF_GPIO_Type const * p_reg)
1180 {
1181 return p_reg->PORTCNF.DRIVECTRL & NRF_GPIO_PORT_IMPEDANCE_ALL_MASK;
1182 }
1183 #endif
1184
1185 #if NRF_GPIO_HAS_RETENTION
nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg,uint32_t mask)1186 NRF_STATIC_INLINE void nrf_gpio_port_retain_set(NRF_GPIO_Type * p_reg, uint32_t mask)
1187 {
1188 p_reg->RETAIN = mask;
1189 }
1190
nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg)1191 NRF_STATIC_INLINE uint32_t nrf_gpio_port_retain_get(NRF_GPIO_Type const * p_reg)
1192 {
1193 return p_reg->RETAIN;
1194 }
1195 #endif
1196
1197 #if NRF_GPIO_HAS_DETECT_MODE
nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg,bool enable)1198 NRF_STATIC_INLINE void nrf_gpio_port_detect_latch_set(NRF_GPIO_Type * p_reg, bool enable)
1199 {
1200 p_reg->DETECTMODE = (enable ? GPIO_DETECTMODE_DETECTMODE_LDETECT :
1201 GPIO_DETECTMODE_DETECTMODE_Default);
1202 }
1203
nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg)1204 NRF_STATIC_INLINE bool nrf_gpio_port_detect_latch_check(NRF_GPIO_Type const * p_reg)
1205 {
1206 return (p_reg->DETECTMODE == GPIO_DETECTMODE_DETECTMODE_LDETECT);
1207 }
1208 #endif
1209
1210 #if defined(NRF_GPIO_LATCH_PRESENT)
nrf_gpio_latches_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)1211 NRF_STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port,
1212 uint32_t length,
1213 uint32_t * p_masks)
1214 {
1215 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
1216 uint32_t i;
1217
1218 for (i = start_port; i < (start_port + length); i++)
1219 {
1220 *p_masks = gpio_regs[i]->LATCH;
1221 p_masks++;
1222 }
1223 }
1224
nrf_gpio_latches_read_and_clear(uint32_t start_port,uint32_t length,uint32_t * p_masks)1225 NRF_STATIC_INLINE void nrf_gpio_latches_read_and_clear(uint32_t start_port,
1226 uint32_t length,
1227 uint32_t * p_masks)
1228 {
1229 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
1230 uint32_t i;
1231
1232 for (i = start_port; i < (start_port + length); i++)
1233 {
1234 *p_masks = gpio_regs[i]->LATCH;
1235
1236 // The LATCH register is cleared by writing a '1' to the bit that shall be cleared.
1237 gpio_regs[i]->LATCH = *p_masks;
1238
1239 p_masks++;
1240 }
1241 }
1242
nrf_gpio_pin_latch_get(uint32_t pin_number)1243 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number)
1244 {
1245 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1246
1247 return (reg->LATCH & (1 << pin_number)) ? 1 : 0;
1248 }
1249
1250
nrf_gpio_pin_latch_clear(uint32_t pin_number)1251 NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number)
1252 {
1253 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1254
1255 reg->LATCH = (1 << pin_number);
1256 }
1257 #endif // defined(NRF_GPIO_LATCH_PRESENT)
1258
1259 #if NRF_GPIO_HAS_SEL
nrf_gpio_pin_control_select(uint32_t pin_number,nrf_gpio_pin_sel_t ctrl)1260 NRF_STATIC_INLINE void nrf_gpio_pin_control_select(uint32_t pin_number, nrf_gpio_pin_sel_t ctrl)
1261 {
1262 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1263 #if defined(GPIO_PIN_CNF_MCUSEL_Msk)
1264 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_MCUSEL_Msk;
1265 reg->PIN_CNF[pin_number] = cnf | (ctrl << GPIO_PIN_CNF_MCUSEL_Pos);
1266 #else
1267 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_CTRLSEL_Msk;
1268 reg->PIN_CNF[pin_number] = cnf | (ctrl << GPIO_PIN_CNF_CTRLSEL_Pos);
1269 #endif
1270 }
1271 #endif // NRF_GPIO_HAS_SEL
1272
1273 #if NRF_GPIO_HAS_CLOCKPIN
nrf_gpio_pin_clock_set(uint32_t pin_number,bool enable)1274 NRF_STATIC_INLINE void nrf_gpio_pin_clock_set(uint32_t pin_number, bool enable)
1275 {
1276 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1277
1278 reg->PIN_CNF[pin_number] = ((reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_CLOCKPIN_Msk) |
1279 ((enable ? GPIO_PIN_CNF_CLOCKPIN_Enabled :
1280 GPIO_PIN_CNF_CLOCKPIN_Disabled) << GPIO_PIN_CNF_CLOCKPIN_Pos));
1281 }
1282
nrf_gpio_pin_clock_check(uint32_t pin_number)1283 NRF_STATIC_INLINE bool nrf_gpio_pin_clock_check(uint32_t pin_number)
1284 {
1285 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
1286
1287 return (((reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_CLOCKPIN_Msk) >> GPIO_PIN_CNF_CLOCKPIN_Pos)
1288 == GPIO_PIN_CNF_CLOCKPIN_Enabled);
1289 }
1290 #endif
1291
nrf_gpio_pin_present_check(uint32_t pin_number)1292 NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number)
1293 {
1294 uint32_t port = pin_number >> 5;
1295 uint32_t mask = 0;
1296
1297 switch (port)
1298 {
1299 NRF_INTERNAL_GPIO_PORT_MASK_SET(mask);
1300
1301 default:
1302 return false;
1303 }
1304
1305 #ifdef P0_FEATURE_PINS_PRESENT
1306 #if defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
1307 /* Allow use of the following additional GPIOs that are connected to LEDs and buttons
1308 * on the nRF52833 DK:
1309 * - P0.11 - Button 1
1310 * - P0.12 - Button 2
1311 * - P0.13 - LED 1
1312 * - P0.24 - Button 3
1313 * - P0.25 - Button 4
1314 */
1315 mask |= 0x03003800;
1316 #endif // defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
1317 #endif
1318
1319 pin_number &= 0x1F;
1320
1321 return (mask & (1UL << pin_number)) ? true : false;
1322 }
1323
nrf_gpio_pin_port_number_extract(uint32_t * p_pin)1324 NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
1325 {
1326 uint32_t pin_number = *p_pin;
1327 *p_pin = NRF_PIN_NUMBER_TO_PIN(pin_number);
1328
1329 return NRF_PIN_NUMBER_TO_PORT(pin_number);
1330 }
1331
1332 #endif // NRF_DECLARE_ONLY
1333
1334 /** @} */
1335
1336 #ifdef __cplusplus
1337 }
1338 #endif
1339
1340 #endif // NRF_GPIO_H__
1341
