1 /* 2 * Copyright (c) 2022 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_ 8 9 /** 10 * @brief nRF-specific GPIO Flags 11 * @defgroup gpio_interface_nrf nRF-specific GPIO Flags 12 * @ingroup gpio_interface 13 * @{ 14 */ 15 16 /** 17 * @name nRF GPIO drive flags 18 * @brief nRF GPIO drive flags 19 * 20 * Standard (S) or High (H) drive modes can be applied to both pin levels, 0 or 21 * 1. High drive mode will increase current capabilities of the pin (refer to 22 * each SoC reference manual). 23 * 24 * When the pin is configured to operate in open-drain mode (wired-and), the 25 * drive mode can only be selected for the 0 level (1 is disconnected). 26 * Similarly, when the pin is configured to operate in open-source mode 27 * (wired-or), the drive mode can only be set for the 1 level 28 * (0 is disconnected). 29 * 30 * The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as 31 * follows: 32 * 33 * - Bit 8: Drive mode for '0' (0=Standard, 1=High) 34 * - Bit 9: Drive mode for '1' (0=Standard, 1=High) 35 * 36 * @{ 37 */ 38 39 /** @cond INTERNAL_HIDDEN */ 40 /** Drive mode field mask */ 41 #define NRF_GPIO_DRIVE_MSK 0x0300U 42 /** @endcond */ 43 44 /** Standard drive for '0' (default, used with GPIO_OPEN_DRAIN) */ 45 #define NRF_GPIO_DRIVE_S0 (0U << 8U) 46 /** High drive for '0' (used with GPIO_OPEN_DRAIN) */ 47 #define NRF_GPIO_DRIVE_H0 (1U << 8U) 48 /** Standard drive for '1' (default, used with GPIO_OPEN_SOURCE) */ 49 #define NRF_GPIO_DRIVE_S1 (0U << 9U) 50 /** High drive for '1' (used with GPIO_OPEN_SOURCE) */ 51 #define NRF_GPIO_DRIVE_H1 (1U << 9U) 52 /** Standard drive for '0' and '1' (default) */ 53 #define NRF_GPIO_DRIVE_S0S1 (NRF_GPIO_DRIVE_S0 | NRF_GPIO_DRIVE_S1) 54 /** Standard drive for '0' and high for '1' */ 55 #define NRF_GPIO_DRIVE_S0H1 (NRF_GPIO_DRIVE_S0 | NRF_GPIO_DRIVE_H1) 56 /** High drive for '0' and standard for '1' */ 57 #define NRF_GPIO_DRIVE_H0S1 (NRF_GPIO_DRIVE_H0 | NRF_GPIO_DRIVE_S1) 58 /** High drive for '0' and '1' */ 59 #define NRF_GPIO_DRIVE_H0H1 (NRF_GPIO_DRIVE_H0 | NRF_GPIO_DRIVE_H1) 60 61 /** @} */ 62 63 /** @} */ 64 65 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_ */ 66
