1 /* 2 * Copyright (c) 2021 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * nRF SoC specific helpers for pinctrl driver 10 */ 11 12 #ifndef ZEPHYR_SOC_ARM_NORDIC_NRF_COMMON_PINCTRL_SOC_H_ 13 #define ZEPHYR_SOC_ARM_NORDIC_NRF_COMMON_PINCTRL_SOC_H_ 14 15 #include <zephyr/devicetree.h> 16 #include <zephyr/dt-bindings/pinctrl/nrf-pinctrl.h> 17 #include <zephyr/dt-bindings/power/nordic-nrf-gpd.h> 18 #include <zephyr/types.h> 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 /** @cond INTERNAL_HIDDEN */ 25 26 /** Type for nRF pin. */ 27 typedef uint32_t pinctrl_soc_pin_t; 28 29 /** 30 * @brief Utility macro to check if a function requires clockpin enable. 31 * 32 * @param node_id Node identifier. 33 * @param prop Property name. 34 * @param idx Property entry index. 35 * @param p_node_id Parent node identifier. 36 */ 37 #define Z_CHECK_CLOCKPIN_ENABLE(node_id, prop, idx, fun) \ 38 DT_PROP_BY_IDX(node_id, prop, idx) == fun ? BIT(NRF_CLOCKPIN_ENABLE_POS) : 39 40 /** 41 * @brief Utility macro compute the clockpin enable bit. 42 * 43 * @note DT_FOREACH_PROP_ELEM_SEP_VARGS() is used instead of 44 * DT_FOREACH_PROP_ELEM_VARGS() because the latter is already resolved in the 45 * same run. 46 * 47 * @param node_id Node identifier. 48 * @param prop Property name. 49 * @param idx Property entry index. 50 * @param p_node_id Parent node identifier. 51 */ 52 #define Z_GET_CLOCKPIN_ENABLE(node_id, prop, idx, p_node_id) \ 53 COND_CODE_1(DT_NODE_HAS_PROP(p_node_id, nordic_clockpin_enable), \ 54 ((DT_FOREACH_PROP_ELEM_SEP_VARGS( \ 55 p_node_id, nordic_clockpin_enable, Z_CHECK_CLOCKPIN_ENABLE, \ 56 (), NRF_GET_FUN(DT_PROP_BY_IDX(node_id, prop, idx))) \ 57 0)), (0)) 58 59 /** 60 * @brief Utility macro to get the GPD_FAST_ACTIVE1 flag 61 * 62 * @param p_node_id Parent node identifier. 63 */ 64 #define Z_GET_GPD_FAST_ACTIVE1(p_node_id) \ 65 COND_CODE_1(DT_NODE_HAS_PROP(p_node_id, power_domains), \ 66 ((DT_PHA(p_node_id, power_domains, id) == \ 67 NRF_GPD_FAST_ACTIVE1) << NRF_GPD_FAST_ACTIVE1_POS), (0)) 68 69 /** 70 * @brief Utility macro to initialize each pin. 71 * 72 * @param node_id Node identifier. 73 * @param prop Property name. 74 * @param idx Property entry index. 75 * @param p_node_id Parent node identifier. 76 */ 77 #define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx, p_node_id) \ 78 (DT_PROP_BY_IDX(node_id, prop, idx) | \ 79 ((NRF_PULL_DOWN * DT_PROP(node_id, bias_pull_down)) << NRF_PULL_POS) |\ 80 ((NRF_PULL_UP * DT_PROP(node_id, bias_pull_up)) << NRF_PULL_POS) | \ 81 (DT_PROP(node_id, nordic_drive_mode) << NRF_DRIVE_POS) | \ 82 ((NRF_LP_ENABLE * DT_PROP(node_id, low_power_enable)) << NRF_LP_POS) |\ 83 (DT_PROP(node_id, nordic_invert) << NRF_INVERT_POS) | \ 84 Z_GET_CLOCKPIN_ENABLE(node_id, prop, idx, p_node_id) | \ 85 Z_GET_GPD_FAST_ACTIVE1(p_node_id) \ 86 ), 87 88 /** 89 * @brief Utility macro to initialize state pins contained in a given property. 90 * 91 * @param node_id Node identifier. 92 * @param prop Property name describing state pins. 93 */ 94 #define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ 95 {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ 96 DT_FOREACH_PROP_ELEM_VARGS, psels, \ 97 Z_PINCTRL_STATE_PIN_INIT, node_id)} 98 99 /** 100 * @brief Utility macro to obtain pin function. 101 * 102 * @param pincfg Pin configuration bit field. 103 */ 104 #define NRF_GET_FUN(pincfg) (((pincfg) >> NRF_FUN_POS) & NRF_FUN_MSK) 105 106 /** 107 * @brief Utility macro to obtain pin clockpin enable flag. 108 * 109 * @param pincfg Pin configuration bit field. 110 */ 111 #define NRF_GET_CLOCKPIN_ENABLE(pincfg) \ 112 (((pincfg) >> NRF_CLOCKPIN_ENABLE_POS) & NRF_CLOCKPIN_ENABLE_MSK) 113 114 /** 115 * @brief Utility macro to obtain GPD_FAST_ACTIVE1 flag 116 * 117 * @param pincfg Pin configuration bit field. 118 */ 119 #define NRF_GET_GPD_FAST_ACTIVE1(pincfg) \ 120 (((pincfg) >> NRF_GPD_FAST_ACTIVE1_POS) & NRF_GPD_FAST_ACTIVE1_MSK) 121 122 /** 123 * @brief Utility macro to obtain pin inversion flag. 124 * 125 * @param pincfg Pin configuration bit field. 126 */ 127 #define NRF_GET_INVERT(pincfg) (((pincfg) >> NRF_INVERT_POS) & NRF_INVERT_MSK) 128 129 /** 130 * @brief Utility macro to obtain pin low power flag. 131 * 132 * @param pincfg Pin configuration bit field. 133 */ 134 #define NRF_GET_LP(pincfg) (((pincfg) >> NRF_LP_POS) & NRF_LP_MSK) 135 136 /** 137 * @brief Utility macro to obtain pin drive mode. 138 * 139 * @param pincfg Pin configuration bit field. 140 */ 141 #define NRF_GET_DRIVE(pincfg) (((pincfg) >> NRF_DRIVE_POS) & NRF_DRIVE_MSK) 142 143 /** 144 * @brief Utility macro to obtain pin pull configuration. 145 * 146 * @param pincfg Pin configuration bit field. 147 */ 148 #define NRF_GET_PULL(pincfg) (((pincfg) >> NRF_PULL_POS) & NRF_PULL_MSK) 149 150 /** 151 * @brief Utility macro to obtain port and pin combination. 152 * 153 * @param pincfg Pin configuration bit field. 154 */ 155 #define NRF_GET_PIN(pincfg) (((pincfg) >> NRF_PIN_POS) & NRF_PIN_MSK) 156 157 /** @endcond */ 158 159 #ifdef __cplusplus 160 } 161 #endif 162 163 #endif /* ZEPHYR_SOC_ARM_NORDIC_NRF_COMMON_PINCTRL_SOC_H_ */ 164
