1 /*
2  * Copyright (c) 2021 Nordic Semiconductor ASA
3  * SPDX-License-Identifier: Apache-2.0
4  */
5 
6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
7 #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
8 
9 /*
10  * The whole nRF pin configuration information is encoded in a 32-bit bitfield
11  * organized as follows:
12  *
13  * - 31..17: Pin function.
14  * - 16:     Pin inversion mode.
15  * - 15:     Pin low power mode.
16  * - 14..11: Pin output drive configuration.
17  * - 10..9:  Pin pull configuration.
18  * - 8..0:   Pin number (combination of port and pin).
19  */
20 
21 /**
22  * @name nRF pin configuration bit field positions and masks.
23  * @{
24  */
25 
26 /** Position of the function field. */
27 #define NRF_FUN_POS 17U
28 /** Mask for the function field. */
29 #define NRF_FUN_MSK 0x7FFFU
30 /** Position of the invert field. */
31 #define NRF_INVERT_POS 16U
32 /** Mask for the invert field. */
33 #define NRF_INVERT_MSK 0x1U
34 /** Position of the low power field. */
35 #define NRF_LP_POS 15U
36 /** Mask for the low power field. */
37 #define NRF_LP_MSK 0x1U
38 /** Position of the drive configuration field. */
39 #define NRF_DRIVE_POS 11U
40 /** Mask for the drive configuration field. */
41 #define NRF_DRIVE_MSK 0xFU
42 /** Position of the pull configuration field. */
43 #define NRF_PULL_POS 9U
44 /** Mask for the pull configuration field. */
45 #define NRF_PULL_MSK 0x3U
46 /** Position of the pin field. */
47 #define NRF_PIN_POS 0U
48 /** Mask for the pin field. */
49 #define NRF_PIN_MSK 0x1FFU
50 
51 /** @} */
52 
53 /**
54  * @name nRF pinctrl pin functions.
55  * @{
56  */
57 
58 /** UART TX */
59 #define NRF_FUN_UART_TX 0U
60 /** UART RX */
61 #define NRF_FUN_UART_RX 1U
62 /** UART RTS */
63 #define NRF_FUN_UART_RTS 2U
64 /** UART CTS */
65 #define NRF_FUN_UART_CTS 3U
66 /** SPI master SCK */
67 #define NRF_FUN_SPIM_SCK 4U
68 /** SPI master MOSI */
69 #define NRF_FUN_SPIM_MOSI 5U
70 /** SPI master MISO */
71 #define NRF_FUN_SPIM_MISO 6U
72 /** SPI slave SCK */
73 #define NRF_FUN_SPIS_SCK 7U
74 /** SPI slave MOSI */
75 #define NRF_FUN_SPIS_MOSI 8U
76 /** SPI slave MISO */
77 #define NRF_FUN_SPIS_MISO 9U
78 /** SPI slave CSN */
79 #define NRF_FUN_SPIS_CSN 10U
80 /** TWI master SCL */
81 #define NRF_FUN_TWIM_SCL 11U
82 /** TWI master SDA */
83 #define NRF_FUN_TWIM_SDA 12U
84 /** I2S SCK in master mode */
85 #define NRF_FUN_I2S_SCK_M 13U
86 /** I2S SCK in slave mode */
87 #define NRF_FUN_I2S_SCK_S 14U
88 /** I2S LRCK in master mode */
89 #define NRF_FUN_I2S_LRCK_M 15U
90 /** I2S LRCK in slave mode */
91 #define NRF_FUN_I2S_LRCK_S 16U
92 /** I2S SDIN */
93 #define NRF_FUN_I2S_SDIN 17U
94 /** I2S SDOUT */
95 #define NRF_FUN_I2S_SDOUT 18U
96 /** I2S MCK */
97 #define NRF_FUN_I2S_MCK 19U
98 /** PDM CLK */
99 #define NRF_FUN_PDM_CLK 20U
100 /** PDM DIN */
101 #define NRF_FUN_PDM_DIN 21U
102 /** PWM OUT0 */
103 #define NRF_FUN_PWM_OUT0 22U
104 /** PWM OUT1 */
105 #define NRF_FUN_PWM_OUT1 23U
106 /** PWM OUT2 */
107 #define NRF_FUN_PWM_OUT2 24U
108 /** PWM OUT3 */
109 #define NRF_FUN_PWM_OUT3 25U
110 /** QDEC A */
111 #define NRF_FUN_QDEC_A 26U
112 /** QDEC B */
113 #define NRF_FUN_QDEC_B 27U
114 /** QDEC LED */
115 #define NRF_FUN_QDEC_LED 28U
116 /** QSPI SCK */
117 #define NRF_FUN_QSPI_SCK 29U
118 /** QSPI CSN */
119 #define NRF_FUN_QSPI_CSN 30U
120 /** QSPI IO0 */
121 #define NRF_FUN_QSPI_IO0 31U
122 /** QSPI IO1 */
123 #define NRF_FUN_QSPI_IO1 32U
124 /** QSPI IO2 */
125 #define NRF_FUN_QSPI_IO2 33U
126 /** QSPI IO3 */
127 #define NRF_FUN_QSPI_IO3 34U
128 /** EXMIF CK */
129 #define NRF_FUN_EXMIF_CK 35U
130 /** EXMIF DQ0 */
131 #define NRF_FUN_EXMIF_DQ0 36U
132 /** EXMIF DQ1 */
133 #define NRF_FUN_EXMIF_DQ1 37U
134 /** EXMIF DQ2 */
135 #define NRF_FUN_EXMIF_DQ2 38U
136 /** EXMIF DQ3 */
137 #define NRF_FUN_EXMIF_DQ3 39U
138 /** EXMIF DQ4 */
139 #define NRF_FUN_EXMIF_DQ4 40U
140 /** EXMIF DQ5 */
141 #define NRF_FUN_EXMIF_DQ5 41U
142 /** EXMIF DQ6 */
143 #define NRF_FUN_EXMIF_DQ6 42U
144 /** EXMIF DQ7 */
145 #define NRF_FUN_EXMIF_DQ7 43U
146 /** EXMIF CS0 */
147 #define NRF_FUN_EXMIF_CS0 44U
148 /** EXMIF CS1 */
149 #define NRF_FUN_EXMIF_CS1 45U
150 /** CAN TX */
151 #define NRF_FUN_CAN_TX 46U
152 /** CAN RX */
153 #define NRF_FUN_CAN_RX 47U
154 
155 /** @} */
156 
157 /**
158  * @name nRF pinctrl output drive.
159  * @{
160  */
161 
162 /** Standard '0', standard '1'. */
163 #define NRF_DRIVE_S0S1 0U
164 /** High drive '0', standard '1'. */
165 #define NRF_DRIVE_H0S1 1U
166 /** Standard '0', high drive '1'. */
167 #define NRF_DRIVE_S0H1 2U
168 /** High drive '0', high drive '1'. */
169 #define NRF_DRIVE_H0H1 3U
170 /** Disconnect '0' standard '1'. */
171 #define NRF_DRIVE_D0S1 4U
172 /** Disconnect '0', high drive '1'. */
173 #define NRF_DRIVE_D0H1 5U
174 /** Standard '0', disconnect '1'. */
175 #define NRF_DRIVE_S0D1 6U
176 /** High drive '0', disconnect '1'. */
177 #define NRF_DRIVE_H0D1 7U
178 /** Extra high drive '0', extra high drive '1'. */
179 #define NRF_DRIVE_E0E1 8U
180 
181 /** @} */
182 
183 /**
184  * @name nRF pinctrl pull-up/down.
185  * @note Values match nrf_gpio_pin_pull_t constants.
186  * @{
187  */
188 
189 /** Pull-up disabled. */
190 #define NRF_PULL_NONE 0U
191 /** Pull-down enabled. */
192 #define NRF_PULL_DOWN 1U
193 /** Pull-up enabled. */
194 #define NRF_PULL_UP 3U
195 
196 /** @} */
197 
198 /**
199  * @name nRF pinctrl low power mode.
200  * @{
201  */
202 
203 /** Input. */
204 #define NRF_LP_DISABLE 0U
205 /** Output. */
206 #define NRF_LP_ENABLE 1U
207 
208 /** @} */
209 
210 /**
211  * @name nRF pinctrl helpers to indicate disconnected pins.
212  * @{
213  */
214 
215 /** Indicates that a pin is disconnected */
216 #define NRF_PIN_DISCONNECTED NRF_PIN_MSK
217 
218 /** @} */
219 
220 /**
221  * @brief Utility macro to build nRF psels property entry.
222  *
223  * @param fun Pin function configuration (see NRF_FUNC_{name} macros).
224  * @param port Port (0 or 15).
225  * @param pin Pin (0..31).
226  */
227 #define NRF_PSEL(fun, port, pin)						       \
228 	((((((port) * 32U) + (pin)) & NRF_PIN_MSK) << NRF_PIN_POS) |		       \
229 	 ((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
230 
231 /**
232  * @brief Utility macro to build nRF psels property entry when a pin is disconnected.
233  *
234  * This can be useful in situations where code running before Zephyr, e.g. a bootloader
235  * configures pins that later needs to be disconnected.
236  *
237  * @param fun Pin function configuration (see NRF_FUN_{name} macros).
238  */
239 #define NRF_PSEL_DISCONNECTED(fun)						       \
240 	(NRF_PIN_DISCONNECTED |							       \
241 	 ((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
242 
243 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_ */
244