1 /*
2 * Copyright (c) 2018 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_DPPI_H__
35 #define NRF_DPPI_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /*
44 * Macro for generating if statement code blocks that allow extracting
45 * the number of channels associated with the specific DPPIC instance.
46 */
47 #define NRF_INTERNAL_DPPI_CHAN_NUM_EXTRACT(chan_num, p_reg) \
48 if (0) {} \
49 NRFX_FOREACH_PRESENT(DPPIC, NRF_INTERNAL_ELSE_IF_EXTRACT_1, (), (), chan_num, _CH_NUM, p_reg) \
50 else \
51 { \
52 chan_num = 0; \
53 }
54
55 /*
56 * Macro for generating if statement code blocks that allow extracting
57 * the number of groups associated with the specific DPPIC instance.
58 */
59 #define NRF_INTERNAL_DPPI_GROUP_NUM_EXTRACT(group_num, p_reg) \
60 if (0) {} \
61 NRFX_FOREACH_PRESENT(DPPIC, NRF_INTERNAL_ELSE_IF_EXTRACT_1, (), (), group_num, _GROUP_NUM, p_reg) \
62 else \
63 { \
64 group_num = 0; \
65 }
66
67 /* Symbol specifying the maximal number of channels associated with the DPPIC instances. */
68 #define NRF_DPPI_CH_NUM_MAX \
69 NRFX_MAX_N(NRFX_FOREACH_PRESENT(DPPIC, NRFX_INTERNAL_CHAN_NUM, (), (), _) 0)
70
71 /**
72 * @defgroup nrf_dppi_hal DPPI Controller HAL
73 * @{
74 * @ingroup nrf_dppi
75 * @brief Hardware access layer for managing the Distributed Programmable Peripheral
76 * Interconnect Controller (DPPIC).
77 */
78
79 /**
80 * @brief Macro for setting publish/subscribe register corresponding to specified event/task.
81 *
82 * @param[in] task_or_event Address of the event or task for which publish/subscribe
83 * register is to be set.
84 * @param[in] dppi_chan DPPIC channel number.
85 */
86 #define NRF_DPPI_ENDPOINT_SETUP(task_or_event, dppi_chan) \
87 (*((volatile uint32_t *)(task_or_event + 0x80uL)) = \
88 ((uint32_t)dppi_chan | NRF_SUBSCRIBE_PUBLISH_ENABLE))
89
90 /**
91 * @brief Macro for clearing publish/subscribe register corresponding to specified event/task.
92 *
93 * @param[in] task_or_event Address of the event or task for which publish/subscribe
94 * register is to be cleared.
95 */
96 #define NRF_DPPI_ENDPOINT_CLEAR(task_or_event) \
97 (*((volatile uint32_t *)(task_or_event + 0x80uL)) = 0)
98
99 /** @brief DPPI channel groups. */
100 typedef enum
101 {
102 NRF_DPPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
103 NRF_DPPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
104 #if DPPI_GROUP_NUM > 2 || defined(__NRFX_DOXYGEN__)
105 NRF_DPPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
106 NRF_DPPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
107 NRF_DPPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
108 NRF_DPPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
109 #endif
110 } nrf_dppi_channel_group_t;
111
112 /** @brief DPPI tasks. */
113 typedef enum
114 {
115 NRF_DPPI_TASK_CHG0_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].EN), /**< Enable channel group 0. */
116 NRF_DPPI_TASK_CHG0_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].DIS), /**< Disable channel group 0. */
117 NRF_DPPI_TASK_CHG1_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].EN), /**< Enable channel group 1. */
118 NRF_DPPI_TASK_CHG1_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].DIS), /**< Disable channel group 1. */
119 #if DPPI_GROUP_NUM > 2 || defined(__NRFX_DOXYGEN__)
120 NRF_DPPI_TASK_CHG2_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].EN), /**< Enable channel group 2. */
121 NRF_DPPI_TASK_CHG2_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].DIS), /**< Disable channel group 2. */
122 NRF_DPPI_TASK_CHG3_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].EN), /**< Enable channel group 3. */
123 NRF_DPPI_TASK_CHG3_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].DIS), /**< Disable channel group 3. */
124 NRF_DPPI_TASK_CHG4_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].EN), /**< Enable channel group 4. */
125 NRF_DPPI_TASK_CHG4_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].DIS), /**< Disable channel group 4. */
126 NRF_DPPI_TASK_CHG5_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].EN), /**< Enable channel group 5. */
127 NRF_DPPI_TASK_CHG5_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].DIS) /**< Disable channel group 5. */
128 #endif
129 } nrf_dppi_task_t;
130
131 /**
132 * @brief Function for getting the total number of available channels for the given DPPIC instance.
133 *
134 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
135 *
136 * @return Number of available channels.
137 */
138 NRF_STATIC_INLINE uint8_t nrf_dppi_channel_number_get(NRF_DPPIC_Type const * p_reg);
139
140 /**
141 * @brief Function for getting the total number of available groups for the given DPPIC instance.
142 *
143 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
144 *
145 * @return Number of available groups.
146 */
147 NRF_STATIC_INLINE uint8_t nrf_dppi_group_number_get(NRF_DPPIC_Type const * p_reg);
148
149 /**
150 * @brief Function for activating a DPPI task.
151 *
152 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
153 * @param[in] dppi_task Task to be activated.
154 */
155 NRF_STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task);
156
157 /**
158 * @brief Function for getting the address of the specified DPPI task register.
159 *
160 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
161 * @param[in] task Requested task.
162 *
163 * @return Address of the specified task register.
164 */
165 NRF_STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
166 nrf_dppi_task_t task);
167
168 /**
169 * @brief Function for checking the state of a specific DPPI channel.
170 *
171 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
172 * @param[in] channel Channel to be checked.
173 *
174 * @retval true The channel is enabled.
175 * @retval false The channel is not enabled.
176 */
177 NRF_STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel);
178
179 /**
180 * @brief Function for enabling multiple DPPI channels.
181 *
182 * The bits in @c mask value correspond to particular channels. It means that
183 * writing 1 to bit 0 enables channel 0, writing 1 to bit 1 enables channel 1 etc.
184 *
185 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
186 * @param[in] mask Channel mask.
187 */
188 NRF_STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask);
189
190 /**
191 * @brief Function for disabling multiple DPPI channels.
192 *
193 * The bits in @c mask value correspond to particular channels. It means that
194 * writing 1 to bit 0 disables channel 0, writing 1 to bit 1 disables channel 1 etc.
195 *
196 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
197 * @param[in] mask Channel mask.
198 */
199 NRF_STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask);
200
201 /**
202 * @brief Function for disabling all DPPI channels.
203 *
204 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
205 */
206 NRF_STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg);
207
208 /**
209 * @brief Function for setting the subscribe configuration for a given
210 * DPPI task.
211 *
212 * @warning After setting the subscription for a given task, channel group configuration
213 * associated with this task cannot be modified until @ref nrf_dppi_subscribe_clear is used.
214 *
215 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
216 * @param[in] task Task for which to set the configuration.
217 * @param[in] channel Channel through which to subscribe events.
218 */
219 NRF_STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
220 nrf_dppi_task_t task,
221 uint8_t channel);
222
223 /**
224 * @brief Function for clearing the subscribe configuration for a given
225 * DPPI task.
226 *
227 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
228 * @param[in] task Task for which to clear the configuration.
229 */
230 NRF_STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task);
231
232 /**
233 * @brief Function for including multiple DPPI channels in a channel group.
234 *
235 * @details This function adds all specified channels to the group.
236 * The bits in @p channel_mask value correspond to particular channels. It means that
237 * writing 1 to bit 0 includes channel 0, writing 1 to bit 1 includes channel 1 etc.
238 *
239 * @warning Channel group configuration can be modified only if subscriptions for tasks
240 * associated with this group are disabled.
241 *
242 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
243 * @param[in] channel_mask Channels to be included in the group.
244 * @param[in] channel_group Channel group.
245 */
246 NRF_STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
247 uint32_t channel_mask,
248 nrf_dppi_channel_group_t channel_group);
249
250 /**
251 * @brief Function for removing multiple DPPI channels from a channel group.
252 *
253 * @details This function removes all specified channels from the group.
254 * The bits in @c channel_mask value correspond to particular channels. It means that
255 * writing 1 to bit 0 removes channel 0, writing 1 to bit 1 removes channel 1 etc.
256 *
257 * @warning Channel group configuration can be modified only if subscriptions for tasks
258 * associated with this group are disabled.
259 *
260 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
261 * @param[in] channel_mask Channels to be removed from the group.
262 * @param[in] channel_group Channel group.
263 */
264 NRF_STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
265 uint32_t channel_mask,
266 nrf_dppi_channel_group_t channel_group);
267
268 /**
269 * @brief Function for removing all DPPI channels from a channel group.
270 *
271 * @warning Channel group configuration can be modified only if subscriptions for tasks
272 * associated with this group are disabled.
273 *
274 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
275 * @param[in] group Channel group.
276 */
277 NRF_STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
278 nrf_dppi_channel_group_t group);
279
280 /**
281 * @brief Function for enabling a channel group.
282 *
283 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
284 * @param[in] group Channel group.
285 */
286 NRF_STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,
287 nrf_dppi_channel_group_t group);
288
289 /**
290 * @brief Function for disabling a channel group.
291 *
292 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
293 * @param[in] group Channel group.
294 */
295 NRF_STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
296 nrf_dppi_channel_group_t group);
297
298 /**
299 * @brief Function for getting the ENABLE task associated with the specified channel group.
300 *
301 * @param[in] index Channel group index.
302 *
303 * @return Requested ENABLE task.
304 */
305 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index);
306
307 /**
308 * @brief Function for getting the DISABLE task associated with the specified channel group.
309 *
310 * @param[in] index Channel group index.
311 *
312 * @return Requested DISABLE task.
313 */
314 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index);
315
316 #ifndef NRF_DECLARE_ONLY
317
nrf_dppi_channel_number_get(NRF_DPPIC_Type const * p_reg)318 NRF_STATIC_INLINE uint8_t nrf_dppi_channel_number_get(NRF_DPPIC_Type const * p_reg)
319 {
320 #if defined(DPPI_CH_NUM)
321 (void)p_reg;
322 return DPPI_CH_NUM;
323 #else
324 uint8_t chan_num = 0;
325 NRF_INTERNAL_DPPI_CHAN_NUM_EXTRACT(chan_num, p_reg);
326
327 return chan_num;
328 #endif // defined(DPPI_CH_NUM)
329 }
330
nrf_dppi_group_number_get(NRF_DPPIC_Type const * p_reg)331 NRF_STATIC_INLINE uint8_t nrf_dppi_group_number_get(NRF_DPPIC_Type const * p_reg)
332 {
333 #if defined(DPPI_GROUP_NUM)
334 (void)p_reg;
335 return DPPI_GROUP_NUM;
336 #else
337 uint8_t group_num = 0;
338 NRF_INTERNAL_DPPI_GROUP_NUM_EXTRACT(group_num, p_reg);
339
340 return group_num;
341 #endif // defined(DPPI_GROUP_NUM)
342 return 0;
343 }
344
nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t dppi_task)345 NRF_STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task)
346 {
347 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) dppi_task)) = 1;
348 }
349
nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,nrf_dppi_task_t task)350 NRF_STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
351 nrf_dppi_task_t task)
352 {
353 return (uint32_t) ((uint8_t *) p_reg + (uint32_t ) task);
354 }
355
nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg,uint8_t channel)356 NRF_STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel)
357 {
358 NRFX_ASSERT(channel < nrf_dppi_channel_number_get(p_reg));
359 return ((p_reg->CHEN & (DPPIC_CHEN_CH0_Enabled << (DPPIC_CHEN_CH0_Pos + channel))) != 0);
360 }
361
nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg)362 NRF_STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg)
363 {
364 p_reg->CHENCLR = 0xFFFFFFFFuL;
365 }
366
nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg,uint32_t mask)367 NRF_STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask)
368 {
369 p_reg->CHENSET = mask;
370 }
371
nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg,uint32_t mask)372 NRF_STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask)
373 {
374 p_reg->CHENCLR = mask;
375 }
376
nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t task,uint8_t channel)377 NRF_STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
378 nrf_dppi_task_t task,
379 uint8_t channel)
380 {
381 NRFX_ASSERT(channel < nrf_dppi_channel_number_get(p_reg));
382 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
383 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
384 }
385
nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t task)386 NRF_STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task)
387 {
388 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
389 }
390
nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,uint32_t channel_mask,nrf_dppi_channel_group_t channel_group)391 NRF_STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
392 uint32_t channel_mask,
393 nrf_dppi_channel_group_t channel_group)
394 {
395 p_reg->CHG[(uint32_t) channel_group] =
396 p_reg->CHG[(uint32_t) channel_group] | (channel_mask);
397 }
398
nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,uint32_t channel_mask,nrf_dppi_channel_group_t channel_group)399 NRF_STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
400 uint32_t channel_mask,
401 nrf_dppi_channel_group_t channel_group)
402 {
403 p_reg->CHG[(uint32_t) channel_group] =
404 p_reg->CHG[(uint32_t) channel_group] & ~(channel_mask);
405 }
406
nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)407 NRF_STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
408 nrf_dppi_channel_group_t group)
409 {
410 p_reg->CHG[(uint32_t) group] = 0;
411 }
412
nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)413 NRF_STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg, nrf_dppi_channel_group_t group)
414 {
415 p_reg->TASKS_CHG[(uint32_t) group].EN = 1;
416 }
417
nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)418 NRF_STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
419 nrf_dppi_channel_group_t group)
420 {
421 p_reg->TASKS_CHG[(uint32_t) group].DIS = 1;
422 }
423
nrf_dppi_group_enable_task_get(uint8_t index)424 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index)
425 {
426 return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].EN);
427 }
428
nrf_dppi_group_disable_task_get(uint8_t index)429 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index)
430 {
431 return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].DIS);
432 }
433
434 #endif // NRF_DECLARE_ONLY
435
436 /** @} */
437
438 #ifdef __cplusplus
439 }
440 #endif
441
442 #endif // NRF_DPPIC_H__
443
