1 /* 2 * Copyright (c) 2018 Oticon A/S 3 * Copyright (c) 2020-2023 Nordic Semiconductor ASA 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 /* 9 * This file redefines macros from nrf that need to be different for simulated devices. 10 */ 11 12 #ifndef NRF_BSIM_REDEF_H 13 #define NRF_BSIM_REDEF_H 14 15 #include "NHW_config.h" 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 void *nhw_convert_periph_base_addr(void *hw_addr); 22 23 #if defined(NRF52833_XXAA) 24 /* 25 * Redefine the base addresses. 26 */ 27 extern NRF_AAR_Type NRF_AAR_regs; 28 #undef NRF_AAR_BASE 29 #define NRF_AAR_BASE (&NRF_AAR_regs) 30 extern NRF_RNG_Type NRF_RNG_regs; 31 #undef NRF_RNG_BASE 32 #define NRF_RNG_BASE (&NRF_RNG_regs) 33 extern NRF_TEMP_Type NRF_TEMP_regs; 34 #undef NRF_TEMP_BASE 35 #define NRF_TEMP_BASE (&NRF_TEMP_regs) 36 extern NRF_RTC_Type NRF_RTC_regs[]; 37 #undef NRF_RTC0_BASE 38 #define NRF_RTC0_BASE (&NRF_RTC_regs[0]) 39 #undef NRF_RTC1_BASE 40 #define NRF_RTC1_BASE (&NRF_RTC_regs[1]) 41 #undef NRF_RTC2_BASE 42 #define NRF_RTC2_BASE (&NRF_RTC_regs[2]) 43 extern NRF_ECB_Type NRF_ECB_regs; 44 #undef NRF_ECB_BASE 45 #define NRF_ECB_BASE (&NRF_ECB_regs) 46 extern NRF_CCM_Type NRF_CCM_regs; 47 #undef NRF_CCM_BASE 48 #define NRF_CCM_BASE (&NRF_CCM_regs) 49 extern NRF_RADIO_Type NRF_RADIO_regs; 50 #undef NRF_RADIO_BASE 51 #define NRF_RADIO_BASE (&NRF_RADIO_regs) 52 extern NRF_CLOCK_Type *NRF_CLOCK_regs[]; 53 #undef NRF_CLOCK_BASE 54 #define NRF_CLOCK_BASE (NRF_CLOCK_regs[NHW_CLKPWR_0]) 55 extern NRF_FICR_Type NRF_FICR_regs; 56 #undef NRF_FICR_BASE 57 #define NRF_FICR_BASE (&NRF_FICR_regs) 58 extern NRF_PPI_Type NRF_PPI_regs; 59 #undef NRF_PPI_BASE 60 #define NRF_PPI_BASE (&NRF_PPI_regs) 61 extern NRF_TIMER_Type NRF_TIMER_regs[]; 62 #undef NRF_TIMER0_BASE 63 #define NRF_TIMER0_BASE (&NRF_TIMER_regs[0]) 64 #undef NRF_TIMER1_BASE 65 #define NRF_TIMER1_BASE (&NRF_TIMER_regs[1]) 66 #undef NRF_TIMER2_BASE 67 #define NRF_TIMER2_BASE (&NRF_TIMER_regs[2]) 68 #undef NRF_TIMER3_BASE 69 #define NRF_TIMER3_BASE (&NRF_TIMER_regs[3]) 70 #undef NRF_TIMER4_BASE 71 #define NRF_TIMER4_BASE (&NRF_TIMER_regs[4]) 72 #undef NRF_POWER_BASE 73 extern NRF_POWER_Type *NRF_POWER_regs[]; 74 #define NRF_POWER_BASE (NRF_POWER_regs[NHW_CLKPWR_0]) 75 extern NRF_GPIO_Type NRF_GPIO_regs[]; 76 #undef NRF_P0_BASE 77 #define NRF_P0_BASE (&NRF_GPIO_regs[0]) 78 #undef NRF_P1_BASE 79 #define NRF_P1_BASE (&NRF_GPIO_regs[1]) 80 extern NRF_GPIOTE_Type NRF_GPIOTE_regs[]; 81 #undef NRF_GPIOTE_BASE 82 #define NRF_GPIOTE_BASE (&NRF_GPIOTE_regs[NHW_GPIOTE_0]) 83 extern NRF_MWU_Type NRF_MWU_regs; 84 #undef NRF_MWU_BASE 85 #define NRF_MWU_BASE (&NRF_MWU_regs) 86 extern NRF_NFCT_Type NRF_NFCT_regs; 87 #undef NRF_NFCT_BASE 88 #define NRF_NFCT_BASE (&NRF_NFCT_regs) 89 extern NRF_NVMC_Type *NRF_NVMC_regs_p[]; 90 #undef NRF_NVMC_BASE 91 #define NRF_NVMC_BASE (NRF_NVMC_regs_p[0]) 92 extern NRF_EGU_Type NRF_EGU_regs[6]; 93 #undef NRF_EGU0_BASE 94 #define NRF_EGU0_BASE (&NRF_EGU_regs[0]) 95 #undef NRF_EGU1_BASE 96 #define NRF_EGU1_BASE (&NRF_EGU_regs[1]) 97 #undef NRF_EGU2_BASE 98 #define NRF_EGU2_BASE (&NRF_EGU_regs[2]) 99 #undef NRF_EGU3_BASE 100 #define NRF_EGU3_BASE (&NRF_EGU_regs[3]) 101 #undef NRF_EGU4_BASE 102 #define NRF_EGU4_BASE (&NRF_EGU_regs[4]) 103 #undef NRF_EGU5_BASE 104 #define NRF_EGU5_BASE (&NRF_EGU_regs[5]) 105 #undef NRF_UICR_BASE 106 extern NRF_UICR_Type *NRF_UICR_regs_p[]; 107 #define NRF_UICR_BASE (NRF_UICR_regs_p[0]) 108 extern NRF_UARTE_Type NRF_UARTE_regs[]; 109 #undef NRF_UART0_BASE 110 #define NRF_UART0_BASE (&NRF_UARTE_regs[NHW_UART_0]) 111 #undef NRF_UARTE0_BASE 112 #define NRF_UARTE0_BASE (&NRF_UARTE_regs[NHW_UART_0]) 113 #undef NRF_UARTE1_BASE 114 #define NRF_UARTE1_BASE (&NRF_UARTE_regs[NHW_UART_1]) 115 116 /********************************************************************/ 117 /********************************************************************/ 118 /********************************************************************/ 119 #elif defined(NRF5340_XXAA_NETWORK) 120 121 extern void *NRF_FICR_regs_p[]; 122 #undef NRF_FICR_NS_BASE 123 #define NRF_FICR_NS_BASE (NRF_FICR_regs_p[NHW_FICR_NET]) 124 extern NRF_UICR_Type *NRF_UICR_regs_p[]; 125 #undef NRF_UICR_NS_BASE 126 #define NRF_UICR_NS_BASE (NRF_UICR_regs_p[NHW_UICR_NET0]) 127 #undef NRF_CTI_NS_BASE 128 #define NRF_CTI_NS_BASE NULL 129 #undef NRF_DCNF_NS_BASE 130 #define NRF_DCNF_NS_BASE NULL 131 extern NRF_VREQCTRL_Type NRF_VREQCTRL_regs; 132 #undef NRF_VREQCTRL_NS_BASE 133 #define NRF_VREQCTRL_NS_BASE (&NRF_VREQCTRL_regs) 134 extern NRF_CLOCK_Type *NRF_CLOCK_regs[]; 135 #undef NRF_CLOCK_NS_BASE 136 #define NRF_CLOCK_NS_BASE (NRF_CLOCK_regs[NHW_CLKPWR_NET0]) 137 extern NRF_POWER_Type *NRF_POWER_regs[]; 138 #undef NRF_POWER_NS_BASE 139 #define NRF_POWER_NS_BASE (NRF_POWER_regs[NHW_CLKPWR_NET0]) 140 extern NRF_RESET_Type *NRF_RESET_regs[]; 141 #undef NRF_RESET_NS_BASE 142 #define NRF_RESET_NS_BASE (NRF_RESET_regs[NHW_CLKPWR_NET0]) 143 #undef NRF_CTRLAP_NS_BASE 144 #define NRF_CTRLAP_NS_BASE NULL 145 extern NRF_RADIO_Type NRF_RADIO_regs; 146 #undef NRF_RADIO_NS_BASE 147 #define NRF_RADIO_NS_BASE (&NRF_RADIO_regs) 148 extern NRF_RNG_Type NRF_RNG_regs; 149 #undef NRF_RNG_NS_BASE 150 #define NRF_RNG_NS_BASE (&NRF_RNG_regs) 151 extern NRF_GPIOTE_Type NRF_GPIOTE_regs[]; 152 #undef NRF_GPIOTE_NS_BASE 153 #define NRF_GPIOTE_NS_BASE (&NRF_GPIOTE_regs[NHW_GPIOTE_NET]) 154 #undef NRF_WDT_NS_BASE 155 #define NRF_WDT_NS_BASE NULL 156 #undef NRF_ECB_NS_BASE 157 extern NRF_ECB_Type NRF_ECB_regs; 158 #define NRF_ECB_NS_BASE (&NRF_ECB_regs) 159 extern NRF_AAR_Type NRF_AAR_regs; 160 #undef NRF_AAR_NS_BASE 161 #define NRF_AAR_NS_BASE (&NRF_AAR_regs) 162 extern NRF_CCM_Type NRF_CCM_regs; 163 #undef NRF_CCM_NS_BASE 164 #define NRF_CCM_NS_BASE (&NRF_CCM_regs) 165 extern NRF_DPPIC_Type NRF_DPPIC_regs[]; 166 #undef NRF_DPPIC_NS_BASE 167 #define NRF_DPPIC_NS_BASE (&NRF_DPPIC_regs[NHW_DPPI_NET_0]) 168 extern NRF_TEMP_Type NRF_TEMP_regs; 169 #undef NRF_TEMP_NS_BASE 170 #define NRF_TEMP_NS_BASE (&NRF_TEMP_regs) 171 extern NRF_RTC_Type NRF_RTC_regs[]; 172 #undef NRF_RTC0_NS_BASE 173 #define NRF_RTC0_NS_BASE (&NRF_RTC_regs[NHW_RTC_NET0]) 174 #undef NRF_RTC1_NS_BASE 175 #define NRF_RTC1_NS_BASE (&NRF_RTC_regs[NHW_RTC_NET1]) 176 extern NRF_IPC_Type NRF_IPC_regs[NHW_IPC_TOTAL_INST]; 177 #undef NRF_IPC_NS_BASE 178 #define NRF_IPC_NS_BASE (&NRF_IPC_regs[NHW_IPC_NET0]) 179 #undef NRF_SPIM0_NS_BASE 180 #define NRF_SPIM0_NS_BASE NULL 181 #undef NRF_SPIS0_NS_BASE 182 #define NRF_SPIS0_NS_BASE NULL 183 #undef NRF_TWIM0_NS_BASE 184 #define NRF_TWIM0_NS_BASE NULL 185 #undef NRF_TWIS0_NS_BASE 186 #define NRF_TWIS0_NS_BASE NULL 187 extern NRF_UARTE_Type NRF_UARTE_regs[]; 188 #undef NRF_UARTE0_NS_BASE 189 #define NRF_UARTE0_NS_BASE (&NRF_UARTE_regs[NHW_UARTE_NET0]) 190 extern NRF_EGU_Type NRF_EGU_regs[]; 191 #undef NRF_EGU0_NS_BASE 192 #define NRF_EGU0_NS_BASE (&NRF_EGU_regs[NHW_EGU_NET0]) 193 extern NRF_TIMER_Type NRF_TIMER_regs[]; 194 #undef NRF_TIMER0_NS_BASE 195 #define NRF_TIMER0_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_NET0]) 196 #undef NRF_TIMER1_NS_BASE 197 #define NRF_TIMER1_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_NET1]) 198 #undef NRF_TIMER2_NS_BASE 199 #define NRF_TIMER2_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_NET2]) 200 extern int NRF_SWI_regs[]; 201 #undef NRF_SWI0_NS_BASE 202 #define NRF_SWI0_NS_BASE (&NRF_SWI_regs[NHW_SWI_NET0]) 203 #undef NRF_SWI1_NS_BASE 204 #define NRF_SWI1_NS_BASE (&NRF_SWI_regs[NHW_SWI_NET1]) 205 #undef NRF_SWI2_NS_BASE 206 #define NRF_SWI2_NS_BASE (&NRF_SWI_regs[NHW_SWI_NET2]) 207 #undef NRF_SWI3_NS_BASE 208 #define NRF_SWI3_NS_BASE (&NRF_SWI_regs[NHW_SWI_NET3]) 209 extern NRF_MUTEX_Type NRF_MUTEX_regs; 210 #undef NRF_APPMUTEX_NS_BASE 211 #define NRF_APPMUTEX_NS_BASE (&NRF_MUTEX_regs) 212 #undef NRF_APPMUTEX_S_BASE 213 #define NRF_APPMUTEX_S_BASE (&NRF_MUTEX_regs) 214 #undef NRF_ACL_NS_BASE 215 #define NRF_ACL_NS_BASE NULL 216 extern NRF_NVMC_Type *NRF_NVMC_regs_p[]; 217 #undef NRF_NVMC_NS_BASE 218 #define NRF_NVMC_NS_BASE (NRF_NVMC_regs_p[NHW_NVMC_NET0]) 219 #undef NRF_VMC_NS_BASE 220 #define NRF_VMC_NS_BASE NULL 221 extern NRF_GPIO_Type NRF_GPIO_regs[]; 222 #undef NRF_P0_NS_BASE 223 #define NRF_P0_NS_BASE (&NRF_GPIO_regs[NHW_GPIO_NET_P0]) 224 #undef NRF_P1_NS_BASE 225 #define NRF_P1_NS_BASE (&NRF_GPIO_regs[NHW_GPIO_NET_P1]) 226 227 /********************************************************************/ 228 /********************************************************************/ 229 /********************************************************************/ 230 #elif defined(NRF5340_XXAA_APPLICATION) 231 232 #undef NRF_CACHEDATA_S_BASE 233 #define NRF_CACHEDATA_S_BASE NULL 234 #undef NRF_CACHEINFO_S_BASE 235 #define NRF_CACHEINFO_S_BASE NULL 236 extern void *NRF_FICR_regs_p[]; 237 #undef NRF_FICR_S_BASE 238 #define NRF_FICR_S_BASE (NRF_FICR_regs_p[NHW_FICR_APP]) 239 extern NRF_UICR_Type *NRF_UICR_regs_p[]; 240 #undef NRF_UICR_S_BASE 241 #define NRF_UICR_S_BASE (NRF_UICR_regs_p[NHW_UICR_APP0]) 242 #undef NRF_CTI_S_BASE 243 #define NRF_CTI_S_BASE NULL 244 #undef NRF_TAD_S_BASE 245 #define NRF_TAD_S_BASE NULL 246 #undef NRF_DCNF_NS_BASE 247 #define NRF_DCNF_NS_BASE NULL 248 #undef NRF_FPU_NS_BASE 249 #define NRF_FPU_NS_BASE NULL 250 #undef NRF_DCNF_S_BASE 251 #define NRF_DCNF_S_BASE NULL 252 #undef NRF_FPU_S_BASE 253 #define NRF_FPU_S_BASE NULL 254 #undef NRF_CACHE_S_BASE 255 #define NRF_CACHE_S_BASE NULL 256 extern NRF_SPU_Type NRF_SPU_regs[]; 257 #undef NRF_SPU_S_BASE 258 #define NRF_SPU_S_BASE (&NRF_SPU_regs[NHW_SPU_APP0]) 259 #undef NRF_OSCILLATORS_NS_BASE 260 #define NRF_OSCILLATORS_NS_BASE NULL 261 #undef NRF_REGULATORS_NS_BASE 262 #define NRF_REGULATORS_NS_BASE NULL 263 #undef NRF_OSCILLATORS_S_BASE 264 #define NRF_OSCILLATORS_S_BASE NULL 265 #undef NRF_REGULATORS_S_BASE 266 #define NRF_REGULATORS_S_BASE NULL 267 extern NRF_CLOCK_Type *NRF_CLOCK_regs[]; 268 #undef NRF_CLOCK_NS_BASE 269 #define NRF_CLOCK_NS_BASE (NRF_CLOCK_regs[NHW_CLKPWR_APP0]) 270 extern NRF_POWER_Type *NRF_POWER_regs[]; 271 #undef NRF_POWER_NS_BASE 272 #define NRF_POWER_NS_BASE (NRF_POWER_regs[NHW_CLKPWR_APP0]) 273 extern NRF_RESET_Type *NRF_RESET_regs[]; 274 #undef NRF_RESET_NS_BASE 275 #define NRF_RESET_NS_BASE (NRF_RESET_regs[NHW_CLKPWR_APP0]) 276 #undef NRF_CLOCK_S_BASE 277 #define NRF_CLOCK_S_BASE (NRF_CLOCK_regs[NHW_CLKPWR_APP0]) 278 #undef NRF_POWER_S_BASE 279 #define NRF_POWER_S_BASE (NRF_POWER_regs[NHW_CLKPWR_APP0]) 280 #undef NRF_RESET_S_BASE 281 #define NRF_RESET_S_BASE (NRF_RESET_regs[NHW_CLKPWR_APP0]) 282 #undef NRF_CTRLAP_NS_BASE 283 #define NRF_CTRLAP_NS_BASE NULL 284 #undef NRF_CTRLAP_S_BASE 285 #define NRF_CTRLAP_S_BASE NULL 286 #undef NRF_SPIM0_NS_BASE 287 #define NRF_SPIM0_NS_BASE NULL 288 #undef NRF_SPIS0_NS_BASE 289 #define NRF_SPIS0_NS_BASE NULL 290 #undef NRF_TWIM0_NS_BASE 291 #define NRF_TWIM0_NS_BASE NULL 292 #undef NRF_TWIS0_NS_BASE 293 #define NRF_TWIS0_NS_BASE NULL 294 extern NRF_UARTE_Type NRF_UARTE_regs[]; 295 #undef NRF_UARTE0_NS_BASE 296 #define NRF_UARTE0_NS_BASE (&NRF_UARTE_regs[NHW_UARTE_APP0]) 297 #undef NRF_SPIM0_S_BASE 298 #define NRF_SPIM0_S_BASE NULL 299 #undef NRF_SPIS0_S_BASE 300 #define NRF_SPIS0_S_BASE NULL 301 #undef NRF_TWIM0_S_BASE 302 #define NRF_TWIM0_S_BASE NULL 303 #undef NRF_TWIS0_S_BASE 304 #define NRF_TWIS0_S_BASE NULL 305 #undef NRF_UARTE0_S_BASE 306 #define NRF_UARTE0_S_BASE (&NRF_UARTE_regs[NHW_UARTE_APP0]) 307 #undef NRF_SPIM1_NS_BASE 308 #define NRF_SPIM1_NS_BASE NULL 309 #undef NRF_SPIS1_NS_BASE 310 #define NRF_SPIS1_NS_BASE NULL 311 #undef NRF_TWIM1_NS_BASE 312 #define NRF_TWIM1_NS_BASE NULL 313 #undef NRF_TWIS1_NS_BASE 314 #define NRF_TWIS1_NS_BASE NULL 315 #undef NRF_UARTE1_NS_BASE 316 #define NRF_UARTE1_NS_BASE (&NRF_UARTE_regs[NHW_UARTE_APP1]) 317 #undef NRF_SPIM1_S_BASE 318 #define NRF_SPIM1_S_BASE NULL 319 #undef NRF_SPIS1_S_BASE 320 #define NRF_SPIS1_S_BASE NULL 321 #undef NRF_TWIM1_S_BASE 322 #define NRF_TWIM1_S_BASE NULL 323 #undef NRF_TWIS1_S_BASE 324 #define NRF_TWIS1_S_BASE NULL 325 #undef NRF_UARTE1_S_BASE 326 #define NRF_UARTE1_S_BASE (&NRF_UARTE_regs[NHW_UARTE_APP1]) 327 #undef NRF_SPIM4_NS_BASE 328 #define NRF_SPIM4_NS_BASE NULL 329 #undef NRF_SPIM4_S_BASE 330 #define NRF_SPIM4_S_BASE NULL 331 #undef NRF_SPIM2_NS_BASE 332 #define NRF_SPIM2_NS_BASE NULL 333 #undef NRF_SPIS2_NS_BASE 334 #define NRF_SPIS2_NS_BASE NULL 335 #undef NRF_TWIM2_NS_BASE 336 #define NRF_TWIM2_NS_BASE NULL 337 #undef NRF_TWIS2_NS_BASE 338 #define NRF_TWIS2_NS_BASE NULL 339 #undef NRF_UARTE2_NS_BASE 340 #define NRF_UARTE2_NS_BASE (&NRF_UARTE_regs[NHW_UARTE_APP2]) 341 #undef NRF_SPIM2_S_BASE 342 #define NRF_SPIM2_S_BASE NULL 343 #undef NRF_SPIS2_S_BASE 344 #define NRF_SPIS2_S_BASE NULL 345 #undef NRF_TWIM2_S_BASE 346 #define NRF_TWIM2_S_BASE NULL 347 #undef NRF_TWIS2_S_BASE 348 #define NRF_TWIS2_S_BASE NULL 349 #undef NRF_UARTE2_S_BASE 350 #define NRF_UARTE2_S_BASE (&NRF_UARTE_regs[NHW_UARTE_APP2]) 351 #undef NRF_SPIM3_NS_BASE 352 #define NRF_SPIM3_NS_BASE NULL 353 #undef NRF_SPIS3_NS_BASE 354 #define NRF_SPIS3_NS_BASE NULL 355 #undef NRF_TWIM3_NS_BASE 356 #define NRF_TWIM3_NS_BASE NULL 357 #undef NRF_TWIS3_NS_BASE 358 #define NRF_TWIS3_NS_BASE NULL 359 #undef NRF_UARTE3_NS_BASE 360 #define NRF_UARTE3_NS_BASE (&NRF_UARTE_regs[NHW_UARTE_APP3]) 361 #undef NRF_SPIM3_S_BASE 362 #define NRF_SPIM3_S_BASE NULL 363 #undef NRF_SPIS3_S_BASE 364 #define NRF_SPIS3_S_BASE NULL 365 #undef NRF_TWIM3_S_BASE 366 #define NRF_TWIM3_S_BASE NULL 367 #undef NRF_TWIS3_S_BASE 368 #define NRF_TWIS3_S_BASE NULL 369 #undef NRF_UARTE3_S_BASE 370 #define NRF_UARTE3_S_BASE (&NRF_UARTE_regs[NHW_UARTE_APP3]) 371 extern NRF_GPIOTE_Type NRF_GPIOTE_regs[]; 372 #undef NRF_GPIOTE0_S_BASE 373 #define NRF_GPIOTE0_S_BASE (&NRF_GPIOTE_regs[NHW_GPIOTE_APP0]) 374 #undef NRF_SAADC_NS_BASE 375 #define NRF_SAADC_NS_BASE NULL 376 #undef NRF_SAADC_S_BASE 377 #define NRF_SAADC_S_BASE NULL 378 extern NRF_TIMER_Type NRF_TIMER_regs[]; 379 #undef NRF_TIMER0_NS_BASE 380 #define NRF_TIMER0_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_APP0]) 381 #undef NRF_TIMER0_S_BASE 382 #define NRF_TIMER0_S_BASE (&NRF_TIMER_regs[NHW_TIMER_APP0]) 383 #undef NRF_TIMER1_NS_BASE 384 #define NRF_TIMER1_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_APP1]) 385 #undef NRF_TIMER1_S_BASE 386 #define NRF_TIMER1_S_BASE (&NRF_TIMER_regs[NHW_TIMER_APP1]) 387 #undef NRF_TIMER2_NS_BASE 388 #define NRF_TIMER2_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_APP2]) 389 #undef NRF_TIMER2_S_BASE 390 #define NRF_TIMER2_S_BASE (&NRF_TIMER_regs[NHW_TIMER_APP2]) 391 extern NRF_RTC_Type NRF_RTC_regs[]; 392 #undef NRF_RTC0_NS_BASE 393 #define NRF_RTC0_NS_BASE (&NRF_RTC_regs[NHW_RTC_APP0]) 394 #undef NRF_RTC0_S_BASE 395 #define NRF_RTC0_S_BASE (&NRF_RTC_regs[NHW_RTC_APP0]) 396 #undef NRF_RTC1_NS_BASE 397 #define NRF_RTC1_NS_BASE (&NRF_RTC_regs[NHW_RTC_APP1]) 398 #undef NRF_RTC1_S_BASE 399 #define NRF_RTC1_S_BASE (&NRF_RTC_regs[NHW_RTC_APP1]) 400 extern NRF_DPPIC_Type NRF_DPPIC_regs[]; 401 #undef NRF_DPPIC_NS_BASE 402 #define NRF_DPPIC_NS_BASE (&NRF_DPPIC_regs[NHW_DPPI_APP_0]) 403 #undef NRF_DPPIC_S_BASE 404 #define NRF_DPPIC_S_BASE (&NRF_DPPIC_regs[NHW_DPPI_APP_0]) 405 #undef NRF_WDT0_NS_BASE 406 #define NRF_WDT0_NS_BASE NULL 407 #undef NRF_WDT0_S_BASE 408 #define NRF_WDT0_S_BASE NULL 409 #undef NRF_WDT1_NS_BASE 410 #define NRF_WDT1_NS_BASE NULL 411 #undef NRF_WDT1_S_BASE 412 #define NRF_WDT1_S_BASE NULL 413 #undef NRF_COMP_NS_BASE 414 #define NRF_COMP_NS_BASE NULL 415 #undef NRF_LPCOMP_NS_BASE 416 #define NRF_LPCOMP_NS_BASE NULL 417 #undef NRF_COMP_S_BASE 418 #define NRF_COMP_S_BASE NULL 419 #undef NRF_LPCOMP_S_BASE 420 #define NRF_LPCOMP_S_BASE NULL 421 extern NRF_EGU_Type NRF_EGU_regs[]; 422 #undef NRF_EGU0_NS_BASE 423 #define NRF_EGU0_NS_BASE (&NRF_EGU_regs[NHW_EGU_APP0]) 424 #undef NRF_EGU0_S_BASE 425 #define NRF_EGU0_S_BASE (&NRF_EGU_regs[NHW_EGU_APP0]) 426 #undef NRF_EGU1_NS_BASE 427 #define NRF_EGU1_NS_BASE (&NRF_EGU_regs[NHW_EGU_APP1]) 428 #undef NRF_EGU1_S_BASE 429 #define NRF_EGU1_S_BASE (&NRF_EGU_regs[NHW_EGU_APP1]) 430 #undef NRF_EGU2_NS_BASE 431 #define NRF_EGU2_NS_BASE (&NRF_EGU_regs[NHW_EGU_APP2]) 432 #undef NRF_EGU2_S_BASE 433 #define NRF_EGU2_S_BASE (&NRF_EGU_regs[NHW_EGU_APP2]) 434 #undef NRF_EGU3_NS_BASE 435 #define NRF_EGU3_NS_BASE (&NRF_EGU_regs[NHW_EGU_APP3]) 436 #undef NRF_EGU3_S_BASE 437 #define NRF_EGU3_S_BASE (&NRF_EGU_regs[NHW_EGU_APP3]) 438 #undef NRF_EGU4_NS_BASE 439 #define NRF_EGU4_NS_BASE (&NRF_EGU_regs[NHW_EGU_APP4]) 440 #undef NRF_EGU4_S_BASE 441 #define NRF_EGU4_S_BASE (&NRF_EGU_regs[NHW_EGU_APP4]) 442 #undef NRF_EGU5_NS_BASE 443 #define NRF_EGU5_NS_BASE (&NRF_EGU_regs[NHW_EGU_APP5]) 444 #undef NRF_EGU5_S_BASE 445 #define NRF_EGU5_S_BASE (&NRF_EGU_regs[NHW_EGU_APP5]) 446 #undef NRF_PWM0_NS_BASE 447 #define NRF_PWM0_NS_BASE NULL 448 #undef NRF_PWM0_S_BASE 449 #define NRF_PWM0_S_BASE NULL 450 #undef NRF_PWM1_NS_BASE 451 #define NRF_PWM1_NS_BASE NULL 452 #undef NRF_PWM1_S_BASE 453 #define NRF_PWM1_S_BASE NULL 454 #undef NRF_PWM2_NS_BASE 455 #define NRF_PWM2_NS_BASE NULL 456 #undef NRF_PWM2_S_BASE 457 #define NRF_PWM2_S_BASE NULL 458 #undef NRF_PWM3_NS_BASE 459 #define NRF_PWM3_NS_BASE NULL 460 #undef NRF_PWM3_S_BASE 461 #define NRF_PWM3_S_BASE NULL 462 #undef NRF_PDM0_NS_BASE 463 #define NRF_PDM0_NS_BASE NULL 464 #undef NRF_PDM0_S_BASE 465 #define NRF_PDM0_S_BASE NULL 466 #undef NRF_I2S0_NS_BASE 467 #define NRF_I2S0_NS_BASE NULL 468 #undef NRF_I2S0_S_BASE 469 #define NRF_I2S0_S_BASE NULL 470 extern NRF_IPC_Type NRF_IPC_regs[NHW_IPC_TOTAL_INST]; 471 #undef NRF_IPC_NS_BASE 472 #define NRF_IPC_NS_BASE (&NRF_IPC_regs[NHW_IPC_APP0]) 473 #undef NRF_IPC_S_BASE 474 #define NRF_IPC_S_BASE (&NRF_IPC_regs[NHW_IPC_APP0]) 475 #undef NRF_QSPI_NS_BASE 476 #define NRF_QSPI_NS_BASE NULL 477 #undef NRF_QSPI_S_BASE 478 #define NRF_QSPI_S_BASE NULL 479 extern NRF_NFCT_Type NRF_NFCT_regs; 480 #undef NRF_NFCT_NS_BASE 481 #define NRF_NFCT_NS_BASE (&NRF_NFCT_regs) 482 #undef NRF_NFCT_S_BASE 483 #define NRF_NFCT_S_BASE (&NRF_NFCT_regs) 484 #undef NRF_GPIOTE1_NS_BASE 485 #define NRF_GPIOTE1_NS_BASE (&NRF_GPIOTE_regs[NHW_GPIOTE_APP1]) 486 extern NRF_MUTEX_Type NRF_MUTEX_regs; 487 #undef NRF_MUTEX_NS_BASE 488 #define NRF_MUTEX_NS_BASE (&NRF_MUTEX_regs) 489 #undef NRF_MUTEX_S_BASE 490 #define NRF_MUTEX_S_BASE (&NRF_MUTEX_regs) 491 #undef NRF_QDEC0_NS_BASE 492 #define NRF_QDEC0_NS_BASE NULL 493 #undef NRF_QDEC0_S_BASE 494 #define NRF_QDEC0_S_BASE NULL 495 #undef NRF_QDEC1_NS_BASE 496 #define NRF_QDEC1_NS_BASE NULL 497 #undef NRF_QDEC1_S_BASE 498 #define NRF_QDEC1_S_BASE NULL 499 #undef NRF_USBD_NS_BASE 500 #define NRF_USBD_NS_BASE NULL 501 #undef NRF_USBD_S_BASE 502 #define NRF_USBD_S_BASE NULL 503 #undef NRF_USBREGULATOR_NS_BASE 504 #define NRF_USBREGULATOR_NS_BASE NULL 505 #undef NRF_USBREGULATOR_S_BASE 506 #define NRF_USBREGULATOR_S_BASE NULL 507 #undef NRF_KMU_NS_BASE 508 #define NRF_KMU_NS_BASE NULL 509 extern NRF_NVMC_Type *NRF_NVMC_regs_p[]; 510 #undef NRF_NVMC_NS_BASE 511 #define NRF_NVMC_NS_BASE (NRF_NVMC_regs_p[NHW_NVMC_APP0]) 512 #undef NRF_KMU_S_BASE 513 #define NRF_KMU_S_BASE NULL 514 #undef NRF_NVMC_S_BASE 515 #define NRF_NVMC_S_BASE (NRF_NVMC_regs_p[NHW_NVMC_APP0]) 516 extern NRF_GPIO_Type NRF_GPIO_regs[]; 517 #undef NRF_P0_NS_BASE 518 #define NRF_P0_NS_BASE (&NRF_GPIO_regs[NHW_GPIO_APP_P0]) 519 #undef NRF_P1_NS_BASE 520 #define NRF_P1_NS_BASE (&NRF_GPIO_regs[NHW_GPIO_APP_P1]) 521 #undef NRF_P0_S_BASE 522 #define NRF_P0_S_BASE (&NRF_GPIO_regs[NHW_GPIO_APP_P0]) 523 #undef NRF_P1_S_BASE 524 #define NRF_P1_S_BASE (&NRF_GPIO_regs[NHW_GPIO_APP_P1]) 525 #undef NRF_CRYPTOCELL_S_BASE 526 #define NRF_CRYPTOCELL_S_BASE NULL 527 #undef NRF_VMC_NS_BASE 528 #define NRF_VMC_NS_BASE NULL 529 #undef NRF_VMC_S_BASE 530 #define NRF_VMC_S_BASE NULL 531 532 /********************************************************************/ 533 /********************************************************************/ 534 /********************************************************************/ 535 #elif defined(NRF54L15_XXAA) 536 537 extern NRF_FICR_Type NRF_FICR_regs; 538 #undef NRF_FICR_NS_BASE 539 #define NRF_FICR_NS_BASE (&NRF_FICR_regs) 540 extern NRF_UICR_Type *NRF_UICR_regs_p[]; 541 #undef NRF_UICR_S_BASE 542 #define NRF_UICR_S_BASE (NRF_UICR_regs_p[0]) 543 #undef NRF_SICR_S_BASE 544 #define NRF_SICR_S_BASE NULL 545 extern NRF_CRACENCORE_Type NRF_CRACENCORE_regs; 546 #undef NRF_CRACENCORE_S_BASE 547 #define NRF_CRACENCORE_S_BASE (&NRF_CRACENCORE_regs) 548 extern NRF_SPU_Type NRF_SPU_regs[]; 549 #undef NRF_SPU00_S_BASE 550 #define NRF_SPU00_S_BASE (&NRF_SPU_regs[NHW_SPU_00]) 551 #undef NRF_MPC00_S_BASE 552 #define NRF_MPC00_S_BASE NULL 553 extern NRF_DPPIC_Type NRF_DPPIC_regs[]; 554 #undef NRF_DPPIC00_NS_BASE 555 #define NRF_DPPIC00_NS_BASE (&NRF_DPPIC_regs[NHW_DPPI_00]) 556 #undef NRF_DPPIC00_S_BASE 557 #define NRF_DPPIC00_S_BASE (&NRF_DPPIC_regs[NHW_DPPI_00]) 558 extern NRF_PPIB_Type NRF_PPIB_regs[]; 559 #undef NRF_PPIB00_NS_BASE 560 #define NRF_PPIB00_NS_BASE (&NRF_PPIB_regs[NHW_PPIB_00]) 561 #undef NRF_PPIB00_S_BASE 562 #define NRF_PPIB00_S_BASE (&NRF_PPIB_regs[NHW_PPIB_00]) 563 #undef NRF_PPIB01_NS_BASE 564 #define NRF_PPIB01_NS_BASE (&NRF_PPIB_regs[NHW_PPIB_01]) 565 #undef NRF_PPIB01_S_BASE 566 #define NRF_PPIB01_S_BASE (&NRF_PPIB_regs[NHW_PPIB_01]) 567 #undef NRF_KMU_S_BASE 568 #define NRF_KMU_S_BASE NULL 569 extern NRF_AAR_Type *NRF_AAR_regs[]; 570 extern NRF_CCM_Type *NRF_CCM_regs[]; 571 extern NRF_ECB_Type NRF_ECB_regs[]; 572 #undef NRF_AAR00_NS_BASE 573 #define NRF_AAR00_NS_BASE (NRF_AAR_regs[NHW_AARCCMECB_00]) 574 #undef NRF_CCM00_NS_BASE 575 #define NRF_CCM00_NS_BASE (NRF_CCM_regs[NHW_AARCCMECB_00]) 576 #undef NRF_AAR00_S_BASE 577 #define NRF_AAR00_S_BASE (NRF_AAR_regs[NHW_AARCCMECB_00]) 578 #undef NRF_CCM00_S_BASE 579 #define NRF_CCM00_S_BASE (NRF_CCM_regs[NHW_AARCCMECB_00]) 580 #undef NRF_ECB00_NS_BASE 581 #define NRF_ECB00_NS_BASE (&NRF_ECB_regs[NHW_AARCCMECB_00]) 582 #undef NRF_ECB00_S_BASE 583 #define NRF_ECB00_S_BASE (&NRF_ECB_regs[NHW_AARCCMECB_00]) 584 extern NRF_CRACEN_Type NRF_CRACEN_regs; 585 #undef NRF_CRACEN_S_BASE 586 #define NRF_CRACEN_S_BASE (&NRF_CRACEN_regs) 587 #undef NRF_SPIM00_NS_BASE 588 #define NRF_SPIM00_NS_BASE NULL 589 #undef NRF_SPIS00_NS_BASE 590 #define NRF_SPIS00_NS_BASE NULL 591 extern NRF_UARTE_Type NRF_UARTE_regs[]; 592 #undef NRF_UARTE00_NS_BASE 593 #define NRF_UARTE00_NS_BASE (&NRF_UARTE_regs[NHW_UARTE00]) 594 #undef NRF_SPIM00_S_BASE 595 #define NRF_SPIM00_S_BASE NULL 596 #undef NRF_SPIS00_S_BASE 597 #define NRF_SPIS00_S_BASE NULL 598 #undef NRF_UARTE00_S_BASE 599 #define NRF_UARTE00_S_BASE (&NRF_UARTE_regs[NHW_UARTE00]) 600 #undef NRF_GLITCHDET_S_BASE 601 #define NRF_GLITCHDET_S_BASE NULL 602 extern void* nhw_RRAMC_get_RRAM_base_address(unsigned int inst); 603 #define NRF_RRAM_BASE_ADDR ((uintptr_t)nhw_RRAMC_get_RRAM_base_address(0)) 604 extern NRF_RRAMC_Type *NRF_RRAMC_regs_p[]; 605 #undef NRF_RRAMC_S_BASE 606 #define NRF_RRAMC_S_BASE (NRF_RRAMC_regs_p[0]) 607 #undef NRF_VPR00_NS_BASE 608 #define NRF_VPR00_NS_BASE NULL 609 #undef NRF_VPR00_S_BASE 610 #define NRF_VPR00_S_BASE NULL 611 extern NRF_GPIO_Type NRF_GPIO_regs[]; 612 #undef NRF_P2_NS_BASE 613 #define NRF_P2_NS_BASE (&NRF_GPIO_regs[NHW_GPIO_P2]) 614 #undef NRF_P2_S_BASE 615 #define NRF_P2_S_BASE (&NRF_GPIO_regs[NHW_GPIO_P2]) 616 #undef NRF_CTRLAP_NS_BASE 617 #define NRF_CTRLAP_NS_BASE NULL 618 #undef NRF_CTRLAP_S_BASE 619 #define NRF_CTRLAP_S_BASE NULL 620 #undef NRF_TAD_NS_BASE 621 #define NRF_TAD_NS_BASE NULL 622 #undef NRF_TAD_S_BASE 623 #define NRF_TAD_S_BASE NULL 624 extern NRF_TIMER_Type NRF_TIMER_regs[]; 625 #undef NRF_TIMER00_NS_BASE 626 #define NRF_TIMER00_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_00]) 627 #undef NRF_TIMER00_S_BASE 628 #define NRF_TIMER00_S_BASE (&NRF_TIMER_regs[NHW_TIMER_00]) 629 #undef NRF_SPU10_S_BASE 630 #define NRF_SPU10_S_BASE (&NRF_SPU_regs[NHW_SPU_10]) 631 #undef NRF_DPPIC10_NS_BASE 632 #define NRF_DPPIC10_NS_BASE (&NRF_DPPIC_regs[NHW_DPPI_10]) 633 #undef NRF_DPPIC10_S_BASE 634 #define NRF_DPPIC10_S_BASE (&NRF_DPPIC_regs[NHW_DPPI_10]) 635 #undef NRF_PPIB10_NS_BASE 636 #define NRF_PPIB10_NS_BASE (&NRF_PPIB_regs[NHW_PPIB_10]) 637 #undef NRF_PPIB10_S_BASE 638 #define NRF_PPIB10_S_BASE (&NRF_PPIB_regs[NHW_PPIB_10]) 639 #undef NRF_PPIB11_NS_BASE 640 #define NRF_PPIB11_NS_BASE (&NRF_PPIB_regs[NHW_PPIB_11]) 641 #undef NRF_PPIB11_S_BASE 642 #define NRF_PPIB11_S_BASE (&NRF_PPIB_regs[NHW_PPIB_11]) 643 #undef NRF_TIMER10_NS_BASE 644 #define NRF_TIMER10_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_10]) 645 #undef NRF_TIMER10_S_BASE 646 #define NRF_TIMER10_S_BASE (&NRF_TIMER_regs[NHW_TIMER_10]) 647 extern NRF_EGU_Type NRF_EGU_regs[]; 648 #undef NRF_EGU10_NS_BASE 649 #define NRF_EGU10_NS_BASE (&NRF_EGU_regs[NHW_EGU_10]) 650 #undef NRF_EGU10_S_BASE 651 #define NRF_EGU10_S_BASE (&NRF_EGU_regs[NHW_EGU_10]) 652 extern NRF_RADIO_Type NRF_RADIO_regs; 653 #undef NRF_RADIO_NS_BASE 654 #define NRF_RADIO_NS_BASE (&NRF_RADIO_regs) 655 #undef NRF_RADIO_S_BASE 656 #define NRF_RADIO_S_BASE (&NRF_RADIO_regs) 657 #undef NRF_SPU20_S_BASE 658 #define NRF_SPU20_S_BASE (&NRF_SPU_regs[NHW_SPU_20]) 659 #undef NRF_DPPIC20_NS_BASE 660 #define NRF_DPPIC20_NS_BASE (&NRF_DPPIC_regs[NHW_DPPI_20]) 661 #undef NRF_DPPIC20_S_BASE 662 #define NRF_DPPIC20_S_BASE (&NRF_DPPIC_regs[NHW_DPPI_20]) 663 #undef NRF_PPIB20_NS_BASE 664 #define NRF_PPIB20_NS_BASE (&NRF_PPIB_regs[NHW_PPIB_20]) 665 #undef NRF_PPIB20_S_BASE 666 #define NRF_PPIB20_S_BASE (&NRF_PPIB_regs[NHW_PPIB_20]) 667 #undef NRF_PPIB21_NS_BASE 668 #define NRF_PPIB21_NS_BASE (&NRF_PPIB_regs[NHW_PPIB_21]) 669 #undef NRF_PPIB21_S_BASE 670 #define NRF_PPIB21_S_BASE (&NRF_PPIB_regs[NHW_PPIB_21]) 671 #undef NRF_PPIB22_NS_BASE 672 #define NRF_PPIB22_NS_BASE (&NRF_PPIB_regs[NHW_PPIB_22]) 673 #undef NRF_PPIB22_S_BASE 674 #define NRF_PPIB22_S_BASE (&NRF_PPIB_regs[NHW_PPIB_22]) 675 #undef NRF_SPIM20_NS_BASE 676 #define NRF_SPIM20_NS_BASE NULL 677 #undef NRF_SPIS20_NS_BASE 678 #define NRF_SPIS20_NS_BASE NULL 679 #undef NRF_TWIM20_NS_BASE 680 #define NRF_TWIM20_NS_BASE NULL 681 #undef NRF_TWIS20_NS_BASE 682 #define NRF_TWIS20_NS_BASE NULL 683 #undef NRF_UARTE20_NS_BASE 684 #define NRF_UARTE20_NS_BASE (&NRF_UARTE_regs[NHW_UARTE20]) 685 #undef NRF_SPIM20_S_BASE 686 #define NRF_SPIM20_S_BASE NULL 687 #undef NRF_SPIS20_S_BASE 688 #define NRF_SPIS20_S_BASE NULL 689 #undef NRF_TWIM20_S_BASE 690 #define NRF_TWIM20_S_BASE NULL 691 #undef NRF_TWIS20_S_BASE 692 #define NRF_TWIS20_S_BASE NULL 693 #undef NRF_UARTE20_S_BASE 694 #define NRF_UARTE20_S_BASE (&NRF_UARTE_regs[NHW_UARTE20]) 695 #undef NRF_SPIM21_NS_BASE 696 #define NRF_SPIM21_NS_BASE NULL 697 #undef NRF_SPIS21_NS_BASE 698 #define NRF_SPIS21_NS_BASE NULL 699 #undef NRF_TWIM21_NS_BASE 700 #define NRF_TWIM21_NS_BASE NULL 701 #undef NRF_TWIS21_NS_BASE 702 #define NRF_TWIS21_NS_BASE NULL 703 #undef NRF_UARTE21_NS_BASE 704 #define NRF_UARTE21_NS_BASE (&NRF_UARTE_regs[NHW_UARTE21]) 705 #undef NRF_SPIM21_S_BASE 706 #define NRF_SPIM21_S_BASE NULL 707 #undef NRF_SPIS21_S_BASE 708 #define NRF_SPIS21_S_BASE NULL 709 #undef NRF_TWIM21_S_BASE 710 #define NRF_TWIM21_S_BASE NULL 711 #undef NRF_TWIS21_S_BASE 712 #define NRF_TWIS21_S_BASE NULL 713 #undef NRF_UARTE21_S_BASE 714 #define NRF_UARTE21_S_BASE (&NRF_UARTE_regs[NHW_UARTE21]) 715 #undef NRF_SPIM22_NS_BASE 716 #define NRF_SPIM22_NS_BASE NULL 717 #undef NRF_SPIS22_NS_BASE 718 #define NRF_SPIS22_NS_BASE NULL 719 #undef NRF_TWIM22_NS_BASE 720 #define NRF_TWIM22_NS_BASE NULL 721 #undef NRF_TWIS22_NS_BASE 722 #define NRF_TWIS22_NS_BASE NULL 723 #undef NRF_UARTE22_NS_BASE 724 #define NRF_UARTE22_NS_BASE (&NRF_UARTE_regs[NHW_UARTE22]) 725 #undef NRF_SPIM22_S_BASE 726 #define NRF_SPIM22_S_BASE NULL 727 #undef NRF_SPIS22_S_BASE 728 #define NRF_SPIS22_S_BASE NULL 729 #undef NRF_TWIM22_S_BASE 730 #define NRF_TWIM22_S_BASE NULL 731 #undef NRF_TWIS22_S_BASE 732 #define NRF_TWIS22_S_BASE NULL 733 #undef NRF_UARTE22_S_BASE 734 #define NRF_UARTE22_S_BASE (&NRF_UARTE_regs[NHW_UARTE22]) 735 #undef NRF_EGU20_NS_BASE 736 #define NRF_EGU20_NS_BASE (&NRF_EGU_regs[NHW_EGU_20]) 737 #undef NRF_EGU20_S_BASE 738 #define NRF_EGU20_S_BASE (&NRF_EGU_regs[NHW_EGU_20]) 739 #undef NRF_TIMER20_NS_BASE 740 #define NRF_TIMER20_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_20]) 741 #undef NRF_TIMER20_S_BASE 742 #define NRF_TIMER20_S_BASE (&NRF_TIMER_regs[NHW_TIMER_20]) 743 #undef NRF_TIMER21_NS_BASE 744 #define NRF_TIMER21_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_21]) 745 #undef NRF_TIMER21_S_BASE 746 #define NRF_TIMER21_S_BASE (&NRF_TIMER_regs[NHW_TIMER_21]) 747 #undef NRF_TIMER22_NS_BASE 748 #define NRF_TIMER22_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_22]) 749 #undef NRF_TIMER22_S_BASE 750 #define NRF_TIMER22_S_BASE (&NRF_TIMER_regs[NHW_TIMER_22]) 751 #undef NRF_TIMER23_NS_BASE 752 #define NRF_TIMER23_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_23]) 753 #undef NRF_TIMER23_S_BASE 754 #define NRF_TIMER23_S_BASE (&NRF_TIMER_regs[NHW_TIMER_23]) 755 #undef NRF_TIMER24_NS_BASE 756 #define NRF_TIMER24_NS_BASE (&NRF_TIMER_regs[NHW_TIMER_24]) 757 #undef NRF_TIMER24_S_BASE 758 #define NRF_TIMER24_S_BASE (&NRF_TIMER_regs[NHW_TIMER_24]) 759 #undef NRF_MEMCONF_NS_BASE 760 #define NRF_MEMCONF_NS_BASE NULL 761 #undef NRF_MEMCONF_S_BASE 762 #define NRF_MEMCONF_S_BASE NULL 763 #undef NRF_PDM20_NS_BASE 764 #define NRF_PDM20_NS_BASE NULL 765 #undef NRF_PDM20_S_BASE 766 #define NRF_PDM20_S_BASE NULL 767 #undef NRF_PDM21_NS_BASE 768 #define NRF_PDM21_NS_BASE NULL 769 #undef NRF_PDM21_S_BASE 770 #define NRF_PDM21_S_BASE NULL 771 #undef NRF_PWM20_NS_BASE 772 #define NRF_PWM20_NS_BASE NULL 773 #undef NRF_PWM20_S_BASE 774 #define NRF_PWM20_S_BASE NULL 775 #undef NRF_PWM21_NS_BASE 776 #define NRF_PWM21_NS_BASE NULL 777 #undef NRF_PWM21_S_BASE 778 #define NRF_PWM21_S_BASE NULL 779 #undef NRF_PWM22_NS_BASE 780 #define NRF_PWM22_NS_BASE NULL 781 #undef NRF_PWM22_S_BASE 782 #define NRF_PWM22_S_BASE NULL 783 #undef NRF_SAADC_NS_BASE 784 #define NRF_SAADC_NS_BASE NULL 785 #undef NRF_SAADC_S_BASE 786 #define NRF_SAADC_S_BASE NULL 787 extern NRF_NFCT_Type NRF_NFCT_regs; 788 #undef NRF_NFCT_NS_BASE 789 #define NRF_NFCT_NS_BASE (&NRF_NFCT_regs) 790 #undef NRF_NFCT_S_BASE 791 #define NRF_NFCT_S_BASE (&NRF_NFCT_regs) 792 extern NRF_TEMP_Type NRF_TEMP_regs; 793 #undef NRF_TEMP_NS_BASE 794 #define NRF_TEMP_NS_BASE (&NRF_TEMP_regs) 795 #undef NRF_TEMP_S_BASE 796 #define NRF_TEMP_S_BASE (&NRF_TEMP_regs) 797 #undef NRF_P1_NS_BASE 798 #define NRF_P1_NS_BASE (&NRF_GPIO_regs[NHW_GPIO_P1]) 799 #undef NRF_P1_S_BASE 800 #define NRF_P1_S_BASE (&NRF_GPIO_regs[NHW_GPIO_P1]) 801 extern NRF_GPIOTE_Type NRF_GPIOTE_regs[]; 802 #undef NRF_GPIOTE20_NS_BASE 803 #define NRF_GPIOTE20_NS_BASE (&NRF_GPIOTE_regs[NHW_GPIOTE_20]) 804 #undef NRF_GPIOTE20_S_BASE 805 #define NRF_GPIOTE20_S_BASE (&NRF_GPIOTE_regs[NHW_GPIOTE_20]) 806 #undef NRF_TAMPC_S_BASE 807 #define NRF_TAMPC_S_BASE NULL 808 #undef NRF_I2S20_NS_BASE 809 #define NRF_I2S20_NS_BASE NULL 810 #undef NRF_I2S20_S_BASE 811 #define NRF_I2S20_S_BASE NULL 812 #undef NRF_QDEC20_NS_BASE 813 #define NRF_QDEC20_NS_BASE NULL 814 #undef NRF_QDEC20_S_BASE 815 #define NRF_QDEC20_S_BASE NULL 816 #undef NRF_QDEC21_NS_BASE 817 #define NRF_QDEC21_NS_BASE NULL 818 #undef NRF_QDEC21_S_BASE 819 #define NRF_QDEC21_S_BASE NULL 820 extern NRF_GRTC_Type NRF_GRTC_regs; 821 #undef NRF_GRTC_NS_BASE 822 #define NRF_GRTC_NS_BASE (&NRF_GRTC_regs) 823 #undef NRF_GRTC_S_BASE 824 #define NRF_GRTC_S_BASE (&NRF_GRTC_regs) 825 #undef NRF_SPU30_S_BASE 826 #define NRF_SPU30_S_BASE (&NRF_SPU_regs[NHW_SPU_30]) 827 #undef NRF_DPPIC30_NS_BASE 828 #define NRF_DPPIC30_NS_BASE (&NRF_DPPIC_regs[NHW_DPPI_30]) 829 #undef NRF_DPPIC30_S_BASE 830 #define NRF_DPPIC30_S_BASE (&NRF_DPPIC_regs[NHW_DPPI_30]) 831 #undef NRF_PPIB30_NS_BASE 832 #define NRF_PPIB30_NS_BASE (&NRF_PPIB_regs[NHW_PPIB_30]) 833 #undef NRF_PPIB30_S_BASE 834 #define NRF_PPIB30_S_BASE (&NRF_PPIB_regs[NHW_PPIB_30]) 835 #undef NRF_SPIM30_NS_BASE 836 #define NRF_SPIM30_NS_BASE NULL 837 #undef NRF_SPIS30_NS_BASE 838 #define NRF_SPIS30_NS_BASE NULL 839 #undef NRF_TWIM30_NS_BASE 840 #define NRF_TWIM30_NS_BASE NULL 841 #undef NRF_TWIS30_NS_BASE 842 #define NRF_TWIS30_NS_BASE NULL 843 #undef NRF_UARTE30_NS_BASE 844 #define NRF_UARTE30_NS_BASE (&NRF_UARTE_regs[NHW_UARTE20]) 845 #undef NRF_SPIM30_S_BASE 846 #define NRF_SPIM30_S_BASE NULL 847 #undef NRF_SPIS30_S_BASE 848 #define NRF_SPIS30_S_BASE NULL 849 #undef NRF_TWIM30_S_BASE 850 #define NRF_TWIM30_S_BASE NULL 851 #undef NRF_TWIS30_S_BASE 852 #define NRF_TWIS30_S_BASE NULL 853 #undef NRF_UARTE30_S_BASE 854 #define NRF_UARTE30_S_BASE (&NRF_UARTE_regs[NHW_UARTE30]) 855 #undef NRF_COMP_NS_BASE 856 #define NRF_COMP_NS_BASE NULL 857 #undef NRF_LPCOMP_NS_BASE 858 #define NRF_LPCOMP_NS_BASE NULL 859 #undef NRF_COMP_S_BASE 860 #define NRF_COMP_S_BASE NULL 861 #undef NRF_LPCOMP_S_BASE 862 #define NRF_LPCOMP_S_BASE NULL 863 #undef NRF_WDT30_S_BASE 864 #define NRF_WDT30_S_BASE NULL 865 #undef NRF_WDT31_NS_BASE 866 #define NRF_WDT31_NS_BASE NULL 867 #undef NRF_WDT31_S_BASE 868 #define NRF_WDT31_S_BASE NULL 869 #undef NRF_P0_NS_BASE 870 #define NRF_P0_NS_BASE (&NRF_GPIO_regs[NHW_GPIO_P0]) 871 #undef NRF_P0_S_BASE 872 #define NRF_P0_S_BASE (&NRF_GPIO_regs[NHW_GPIO_P0]) 873 #undef NRF_GPIOTE30_NS_BASE 874 #define NRF_GPIOTE30_NS_BASE (&NRF_GPIOTE_regs[NHW_GPIOTE_30]) 875 #undef NRF_GPIOTE30_S_BASE 876 #define NRF_GPIOTE30_S_BASE (&NRF_GPIOTE_regs[NHW_GPIOTE_30]) 877 extern NRF_CLOCK_Type *NRF_CLOCK_regs[]; 878 #undef NRF_CLOCK_NS_BASE 879 #define NRF_CLOCK_NS_BASE (NRF_CLOCK_regs[NHW_CLKPWR_0]) 880 extern NRF_POWER_Type *NRF_POWER_regs[]; 881 #undef NRF_POWER_NS_BASE 882 #define NRF_POWER_NS_BASE (NRF_POWER_regs[NHW_CLKPWR_0]) 883 extern NRF_RESET_Type *NRF_RESET_regs[]; 884 #undef NRF_RESET_NS_BASE 885 #define NRF_RESET_NS_BASE (NRF_RESET_regs[NHW_CLKPWR_0]) 886 #undef NRF_CLOCK_S_BASE 887 #define NRF_CLOCK_S_BASE (NRF_CLOCK_regs[NHW_CLKPWR_0]) 888 #undef NRF_POWER_S_BASE 889 #define NRF_POWER_S_BASE (NRF_POWER_regs[NHW_CLKPWR_0]) 890 #undef NRF_RESET_S_BASE 891 #define NRF_RESET_S_BASE (NRF_RESET_regs[NHW_CLKPWR_0]) 892 #undef NRF_OSCILLATORS_NS_BASE 893 #define NRF_OSCILLATORS_NS_BASE NULL 894 #undef NRF_REGULATORS_NS_BASE 895 #define NRF_REGULATORS_NS_BASE NULL 896 #undef NRF_OSCILLATORS_S_BASE 897 #define NRF_OSCILLATORS_S_BASE NULL 898 #undef NRF_REGULATORS_S_BASE 899 #define NRF_REGULATORS_S_BASE NULL 900 901 #else 902 #error "Platform not supported" 903 # endif 904 905 #ifdef __cplusplus 906 } 907 #endif 908 909 #endif /* NRF_BSIM_REDEF_H */ 910
