1 /*
2  * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef NRFX_CONFIG_H__
8 #define NRFX_CONFIG_H__
9 
10 #include <zephyr/devicetree.h>
11 
12 /*
13  * NRFX API version 2.10 flag.
14  * When the flag is set NRFX API is compatible with the newest NRFX release.
15  */
16 #define NRFX_CONFIG_API_VER_2_10 1
17 
18 /*
19  * These are mappings of Kconfig options enabling nrfx drivers and particular
20  * peripheral instances to the corresponding symbols used inside of nrfx.
21  * Please note that only subsets of these entries are used for particular SoCs
22  * supported by nrfx (see the corresponding nrfx_config_*.h files).
23  */
24 
25 #ifdef CONFIG_NRFX_ADC
26 #define NRFX_ADC_ENABLED 1
27 #endif
28 #ifdef CONFIG_NRFX_ADC_LOG
29 #define NRFX_ADC_CONFIG_LOG_ENABLED 1
30 #endif
31 
32 #ifdef CONFIG_NRFX_CLOCK
33 #define NRFX_CLOCK_ENABLED 1
34 #endif
35 #ifdef CONFIG_NRFX_CLOCK_LOG
36 #define NRFX_CLOCK_CONFIG_LOG_ENABLED 1
37 #endif
38 
39 #ifdef CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC
40 #if defined(CONFIG_SOC_SERIES_NRF91X) || defined(CONFIG_SOC_SERIES_NRF53X)
41 #define NRFX_CLOCK_CONFIG_LF_SRC 1
42 #else
43 #define NRFX_CLOCK_CONFIG_LF_SRC 0
44 #endif
45 #endif // CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC
46 
47 #ifdef CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL
48 #if defined(CONFIG_SOC_SERIES_NRF91X) || defined(CONFIG_SOC_SERIES_NRF53X)
49 #define NRFX_CLOCK_CONFIG_LF_SRC 2
50 #else
51 #define NRFX_CLOCK_CONFIG_LF_SRC 1
52 #endif
53 #endif // CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL
54 
55 #ifdef CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH
56 #ifdef CONFIG_SOC_SERIES_NRF53X
57 #define NRFX_CLOCK_CONFIG_LF_SRC 3
58 #else
59 #define NRFX_CLOCK_CONFIG_LF_SRC 2
60 #endif
61 #endif // CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH
62 
63 #ifdef CONFIG_CLOCK_CONTROL_NRF_K32SRC_EXT_LOW_SWING
64 #define NRFX_CLOCK_CONFIG_LF_SRC 131073
65 #endif
66 
67 #ifdef CONFIG_CLOCK_CONTROL_NRF_K32SRC_EXT_FULL_SWING
68 #define NRFX_CLOCK_CONFIG_LF_SRC 196609
69 #endif
70 
71 #ifdef CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION
72 #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 1
73 #endif
74 
75 #ifdef CONFIG_NRFX_CLOCK_LFXO_TWO_STAGE_ENABLED
76 #define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 1
77 #endif
78 
79 #ifdef CONFIG_NRFX_COMP
80 #define NRFX_COMP_ENABLED 1
81 #endif
82 #ifdef CONFIG_NRFX_COMP_LOG
83 #define NRFX_COMP_CONFIG_LOG_ENABLED 1
84 #endif
85 
86 #ifdef CONFIG_NRFX_DPPI
87 #define NRFX_DPPI_ENABLED 1
88 #endif
89 #ifdef CONFIG_NRFX_DPPI_LOG
90 #define NRFX_DPPI_CONFIG_LOG_ENABLED 1
91 #endif
92 
93 #ifdef CONFIG_NRFX_EGU
94 #define NRFX_EGU_ENABLED 1
95 #endif
96 #ifdef CONFIG_NRFX_EGU_LOG
97 #define NRFX_EGU_CONFIG_LOG_ENABLED 1
98 #endif
99 #ifdef CONFIG_NRFX_EGU0
100 #define NRFX_EGU0_ENABLED 1
101 #endif
102 #ifdef CONFIG_NRFX_EGU1
103 #define NRFX_EGU1_ENABLED 1
104 #endif
105 #ifdef CONFIG_NRFX_EGU2
106 #define NRFX_EGU2_ENABLED 1
107 #endif
108 #ifdef CONFIG_NRFX_EGU3
109 #define NRFX_EGU3_ENABLED 1
110 #endif
111 #ifdef CONFIG_NRFX_EGU4
112 #define NRFX_EGU4_ENABLED 1
113 #endif
114 #ifdef CONFIG_NRFX_EGU5
115 #define NRFX_EGU5_ENABLED 1
116 #endif
117 
118 #ifdef CONFIG_NRFX_GPIOTE
119 #define NRFX_GPIOTE_ENABLED 1
120 #endif
121 #ifdef CONFIG_NRFX_GPIOTE_LOG
122 #define NRFX_GPIOTE_CONFIG_LOG_ENABLED 1
123 #endif
124 
125 #ifdef CONFIG_NRFX_GPIOTE_NUM_OF_EVT_HANDLERS
126 #define NRFX_GPIOTE_CONFIG_NUM_OF_EVT_HANDLERS CONFIG_NRFX_GPIOTE_NUM_OF_EVT_HANDLERS
127 #endif
128 
129 #ifdef CONFIG_NRFX_I2S
130 #define NRFX_I2S_ENABLED 1
131 #endif
132 #ifdef CONFIG_NRFX_I2S_LOG
133 #define NRFX_I2S_CONFIG_LOG_ENABLED 1
134 #endif
135 #ifdef CONFIG_NRFX_I2S0
136 #define NRFX_I2S0_ENABLED 1
137 #endif
138 
139 #ifdef CONFIG_NRFX_IPC
140 #define NRFX_IPC_ENABLED 1
141 #endif
142 #ifdef CONFIG_NRFX_IPC_LOG
143 #define NRFX_IPC_CONFIG_LOG_ENABLED 1
144 #endif
145 
146 #ifdef CONFIG_NRFX_LPCOMP
147 #define NRFX_LPCOMP_ENABLED 1
148 #endif
149 #ifdef CONFIG_NRFX_LPCOMP_LOG
150 #define NRFX_LPCOMP_CONFIG_LOG_ENABLED 1
151 #endif
152 
153 #ifdef CONFIG_NRFX_NFCT
154 #define NRFX_NFCT_ENABLED 1
155 #endif
156 #ifdef CONFIG_NRFX_NFCT_LOG
157 #define NRFX_NFCT_CONFIG_LOG_ENABLED 1
158 #endif
159 
160 #ifdef CONFIG_NRFX_NVMC
161 #define NRFX_NVMC_ENABLED 1
162 #endif
163 #ifdef CONFIG_NRFX_NVMC_LOG
164 #define NRFX_NVMC_CONFIG_LOG_ENABLED 1
165 #endif
166 
167 #ifdef CONFIG_NRFX_PDM
168 #define NRFX_PDM_ENABLED 1
169 #endif
170 #ifdef CONFIG_NRFX_PDM_LOG
171 #define NRFX_PDM_CONFIG_LOG_ENABLED 1
172 #endif
173 
174 #ifdef CONFIG_NRFX_POWER
175 #define NRFX_POWER_ENABLED 1
176 #endif
177 #ifdef CONFIG_NRFX_POWER_LOG
178 #define NRFX_POWER_CONFIG_LOG_ENABLED 1
179 #endif
180 
181 #ifdef CONFIG_NRFX_PPI
182 #define NRFX_PPI_ENABLED 1
183 #endif
184 #ifdef CONFIG_NRFX_PPI_LOG
185 #define NRFX_PPI_CONFIG_LOG_ENABLED 1
186 #endif
187 
188 #ifdef CONFIG_NRFX_PRS
189 #define NRFX_PRS_ENABLED 1
190 #endif
191 #ifdef CONFIG_NRFX_PRS_LOG
192 #define NRFX_PRS_CONFIG_LOG_ENABLED 1
193 #endif
194 #ifdef CONFIG_NRFX_PRS_BOX_0
195 #define NRFX_PRS_BOX_0_ENABLED 1
196 #endif
197 #ifdef CONFIG_NRFX_PRS_BOX_1
198 #define NRFX_PRS_BOX_1_ENABLED 1
199 #endif
200 #ifdef CONFIG_NRFX_PRS_BOX_2
201 #define NRFX_PRS_BOX_2_ENABLED 1
202 #endif
203 #ifdef CONFIG_NRFX_PRS_BOX_3
204 #define NRFX_PRS_BOX_3_ENABLED 1
205 #endif
206 #ifdef CONFIG_NRFX_PRS_BOX_4
207 #define NRFX_PRS_BOX_4_ENABLED 1
208 #endif
209 
210 #ifdef CONFIG_NRFX_PWM
211 #define NRFX_PWM_ENABLED 1
212 #endif
213 #ifdef CONFIG_NRFX_PWM_LOG
214 #define NRFX_PWM_CONFIG_LOG_ENABLED 1
215 #endif
216 #ifdef CONFIG_NRFX_PWM0
217 #define NRFX_PWM0_ENABLED 1
218 #endif
219 #ifdef CONFIG_NRFX_PWM1
220 #define NRFX_PWM1_ENABLED 1
221 #endif
222 #ifdef CONFIG_NRFX_PWM2
223 #define NRFX_PWM2_ENABLED 1
224 #endif
225 #ifdef CONFIG_NRFX_PWM3
226 #define NRFX_PWM3_ENABLED 1
227 #endif
228 
229 #ifdef CONFIG_NRFX_QDEC
230 #define NRFX_QDEC_ENABLED 1
231 #endif
232 #ifdef CONFIG_NRFX_QDEC_LOG
233 #define NRFX_QDEC_CONFIG_LOG_ENABLED 1
234 #endif
235 #ifdef CONFIG_NRFX_QDEC0
236 #define NRFX_QDEC0_ENABLED 1
237 #endif
238 #ifdef CONFIG_NRFX_QDEC1
239 #define NRFX_QDEC1_ENABLED 1
240 #endif
241 
242 #ifdef CONFIG_NRFX_QSPI
243 #define NRFX_QSPI_ENABLED 1
244 #endif
245 #ifdef CONFIG_NRFX_QSPI_LOG
246 #define NRFX_QSPI_CONFIG_LOG_ENABLED 1
247 #endif
248 
249 #ifdef CONFIG_NRFX_RNG
250 #define NRFX_RNG_ENABLED 1
251 #endif
252 #ifdef CONFIG_NRFX_RNG_LOG
253 #define NRFX_RNG_CONFIG_LOG_ENABLED 1
254 #endif
255 
256 #ifdef CONFIG_NRFX_RTC
257 #define NRFX_RTC_ENABLED 1
258 #endif
259 #ifdef CONFIG_NRFX_RTC_LOG
260 #define NRFX_RTC_CONFIG_LOG_ENABLED 1
261 #endif
262 #ifdef CONFIG_NRFX_RTC0
263 #define NRFX_RTC0_ENABLED 1
264 #endif
265 #ifdef CONFIG_NRFX_RTC1
266 #define NRFX_RTC1_ENABLED 1
267 #endif
268 #ifdef CONFIG_NRFX_RTC2
269 #define NRFX_RTC2_ENABLED 1
270 #endif
271 
272 #ifdef CONFIG_NRFX_SAADC
273 #define NRFX_SAADC_ENABLED 1
274 #endif
275 #ifdef CONFIG_NRFX_SAADC_LOG
276 #define NRFX_SAADC_CONFIG_LOG_ENABLED 1
277 #endif
278 
279 #ifdef CONFIG_NRFX_SPI
280 #define NRFX_SPI_ENABLED 1
281 #endif
282 #ifdef CONFIG_NRFX_SPI_LOG
283 #define NRFX_SPI_CONFIG_LOG_ENABLED 1
284 #endif
285 #ifdef CONFIG_NRFX_SPI0
286 #define NRFX_SPI0_ENABLED 1
287 #endif
288 #ifdef CONFIG_NRFX_SPI1
289 #define NRFX_SPI1_ENABLED 1
290 #endif
291 #ifdef CONFIG_NRFX_SPI2
292 #define NRFX_SPI2_ENABLED 1
293 #endif
294 
295 #ifdef CONFIG_NRFX_SPIM
296 #define NRFX_SPIM_ENABLED 1
297 #endif
298 #ifdef CONFIG_NRFX_SPIM_LOG
299 #define NRFX_SPIM_CONFIG_LOG_ENABLED 1
300 #endif
301 #ifdef CONFIG_NRFX_SPIM0
302 #define NRFX_SPIM0_ENABLED 1
303 #endif
304 #ifdef CONFIG_NRFX_SPIM1
305 #define NRFX_SPIM1_ENABLED 1
306 #endif
307 #ifdef CONFIG_NRFX_SPIM2
308 #define NRFX_SPIM2_ENABLED 1
309 #endif
310 #ifdef CONFIG_NRFX_SPIM3
311 #define NRFX_SPIM3_ENABLED 1
312 #ifdef CONFIG_NRF52_ANOMALY_198_WORKAROUND
313 #define NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED 1
314 #endif
315 #endif
316 #ifdef CONFIG_NRFX_SPIM4
317 #define NRFX_SPIM4_ENABLED 1
318 #endif
319 #if (DT_PROP(DT_NODELABEL(spi3), rx_delay_supported) || \
320 	DT_PROP(DT_NODELABEL(spi4), rx_delay_supported))
321 #define NRFX_SPIM_EXTENDED_ENABLED 1
322 #endif
323 
324 #ifdef CONFIG_NRFX_SPIS
325 #define NRFX_SPIS_ENABLED 1
326 #endif
327 #ifdef CONFIG_NRFX_SPIS_LOG
328 #define NRFX_SPIS_CONFIG_LOG_ENABLED 1
329 #endif
330 #ifdef CONFIG_NRFX_SPIS0
331 #define NRFX_SPIS0_ENABLED 1
332 #endif
333 #ifdef CONFIG_NRFX_SPIS1
334 #define NRFX_SPIS1_ENABLED 1
335 #endif
336 #ifdef CONFIG_NRFX_SPIS2
337 #define NRFX_SPIS2_ENABLED 1
338 #endif
339 #ifdef CONFIG_NRFX_SPIS3
340 #define NRFX_SPIS3_ENABLED 1
341 #endif
342 
343 #ifdef CONFIG_NRFX_SYSTICK
344 #define NRFX_SYSTICK_ENABLED 1
345 #endif
346 #ifdef CONFIG_NRFX_SYSTICK_LOG
347 #define NRFX_SYSTICK_CONFIG_LOG_ENABLED 1
348 #endif
349 
350 #ifdef CONFIG_NRFX_TEMP
351 #define NRFX_TEMP_ENABLED 1
352 #endif
353 #ifdef CONFIG_NRFX_TEMP_LOG
354 #define NRFX_TEMP_CONFIG_LOG_ENABLED 1
355 #endif
356 
357 #ifdef CONFIG_NRFX_TIMER
358 #define NRFX_TIMER_ENABLED 1
359 #endif
360 #ifdef CONFIG_NRFX_TIMER_LOG
361 #define NRFX_TIMER_CONFIG_LOG_ENABLED 1
362 #endif
363 #ifdef CONFIG_NRFX_TIMER0
364 #define NRFX_TIMER0_ENABLED 1
365 #endif
366 #ifdef CONFIG_NRFX_TIMER1
367 #define NRFX_TIMER1_ENABLED 1
368 #endif
369 #ifdef CONFIG_NRFX_TIMER2
370 #define NRFX_TIMER2_ENABLED 1
371 #endif
372 #ifdef CONFIG_NRFX_TIMER3
373 #define NRFX_TIMER3_ENABLED 1
374 #endif
375 #ifdef CONFIG_NRFX_TIMER4
376 #define NRFX_TIMER4_ENABLED 1
377 #endif
378 
379 #ifdef CONFIG_NRFX_TWI
380 #define NRFX_TWI_ENABLED 1
381 #endif
382 #ifdef CONFIG_NRFX_TWI_LOG
383 #define NRFX_TWI_CONFIG_LOG_ENABLED 1
384 #endif
385 #ifdef CONFIG_NRFX_TWI0
386 #define NRFX_TWI0_ENABLED 1
387 #endif
388 #ifdef CONFIG_NRFX_TWI1
389 #define NRFX_TWI1_ENABLED 1
390 #endif
391 
392 #ifdef CONFIG_NRFX_TWIM
393 #define NRFX_TWIM_ENABLED 1
394 #endif
395 #ifdef CONFIG_NRFX_TWIM_LOG
396 #define NRFX_TWIM_CONFIG_LOG_ENABLED 1
397 #endif
398 #ifdef CONFIG_NRFX_TWIM0
399 #define NRFX_TWIM0_ENABLED 1
400 #endif
401 #ifdef CONFIG_NRFX_TWIM1
402 #define NRFX_TWIM1_ENABLED 1
403 #endif
404 #ifdef CONFIG_NRFX_TWIM2
405 #define NRFX_TWIM2_ENABLED 1
406 #endif
407 #ifdef CONFIG_NRFX_TWIM3
408 #define NRFX_TWIM3_ENABLED 1
409 #endif
410 
411 #ifdef CONFIG_NRFX_TWIS
412 #define NRFX_TWIS_ENABLED 1
413 #endif
414 #ifdef CONFIG_NRFX_TWIS_LOG
415 #define NRFX_TWIS_CONFIG_LOG_ENABLED 1
416 #endif
417 #ifdef CONFIG_NRFX_TWIS0
418 #define NRFX_TWIS0_ENABLED 1
419 #endif
420 #ifdef CONFIG_NRFX_TWIS1
421 #define NRFX_TWIS1_ENABLED 1
422 #endif
423 #ifdef CONFIG_NRFX_TWIS2
424 #define NRFX_TWIS2_ENABLED 1
425 #endif
426 #ifdef CONFIG_NRFX_TWIS3
427 #define NRFX_TWIS3_ENABLED 1
428 #endif
429 
430 #ifdef CONFIG_NRFX_UART
431 #define NRFX_UART_ENABLED 1
432 #endif
433 #ifdef CONFIG_NRFX_UART_LOG
434 #define NRFX_UART_CONFIG_LOG_ENABLED 1
435 #endif
436 #ifdef CONFIG_NRFX_UART0
437 #define NRFX_UART0_ENABLED 1
438 #endif
439 
440 #ifdef CONFIG_NRFX_UARTE
441 #define NRFX_UARTE_ENABLED 1
442 #endif
443 #ifdef CONFIG_NRFX_UARTE_LOG
444 #define NRFX_UARTE_CONFIG_LOG_ENABLED 1
445 #endif
446 #ifdef CONFIG_NRFX_UARTE0
447 #define NRFX_UARTE0_ENABLED 1
448 #endif
449 #ifdef CONFIG_NRFX_UARTE1
450 #define NRFX_UARTE1_ENABLED 1
451 #endif
452 #ifdef CONFIG_NRFX_UARTE2
453 #define NRFX_UARTE2_ENABLED 1
454 #endif
455 #ifdef CONFIG_NRFX_UARTE3
456 #define NRFX_UARTE3_ENABLED 1
457 #endif
458 
459 #ifdef CONFIG_NRFX_USBD
460 #define NRFX_USBD_ENABLED 1
461 #endif
462 #ifdef CONFIG_NRFX_USBD_LOG
463 #define NRFX_USBD_CONFIG_LOG_ENABLED 1
464 #endif
465 
466 #ifdef CONFIG_NRFX_USBD_ISO_IN_ZLP
467 #define NRFX_USBD_CONFIG_ISO_IN_ZLP 1
468 #endif
469 
470 #ifdef CONFIG_NRFX_USBREG
471 #define NRFX_USBREG_ENABLED 1
472 #endif
473 #ifdef CONFIG_NRFX_USBREG_LOG
474 #define NRFX_USBREG_CONFIG_LOG_ENABLED 1
475 #endif
476 
477 #ifdef CONFIG_NRFX_WDT
478 #define NRFX_WDT_ENABLED 1
479 #endif
480 #ifdef CONFIG_NRFX_WDT_LOG
481 #define NRFX_WDT_CONFIG_LOG_ENABLED 1
482 #endif
483 #ifdef CONFIG_NRFX_WDT0
484 #define NRFX_WDT0_ENABLED 1
485 #endif
486 #ifdef CONFIG_NRFX_WDT1
487 #define NRFX_WDT1_ENABLED 1
488 #endif
489 
490 #ifdef CONFIG_NRF52_ANOMALY_109_WORKAROUND
491 #define NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 1
492 #define NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED 1
493 #define NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 1
494 #define NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 1
495 #endif
496 
497 #if defined(CONFIG_SOC_SERIES_BSIM_NRFXX)
498 #include "nrfx_config_bsim.h"
499 #endif
500 
501 /*
502  * For chips with TrustZone support, MDK provides CMSIS-Core peripheral
503  * accessing symbols in two flavors, with secure and non-secure base address
504  * mappings. Their names contain the suffix _S or _NS, respectively.
505  * Because nrfx HALs and drivers require these peripheral accessing symbols
506  * without any suffixes, the following macro is provided that will translate
507  * their names according to the kind of the target that is built.
508  */
509 #if defined(NRF_TRUSTZONE_NONSECURE)
510 #define NRF_PERIPH(P) P##_NS
511 #else
512 #define NRF_PERIPH(P) P##_S
513 #endif
514 
515 #include <nrfx_config_common.h>
516 #if defined(NRF51)
517     #include <nrfx_config_nrf51.h>
518 #elif defined(NRF52805_XXAA)
519     #include <nrfx_config_nrf52805.h>
520 #elif defined(NRF52810_XXAA)
521     #include <nrfx_config_nrf52810.h>
522 #elif defined(NRF52811_XXAA)
523     #include <nrfx_config_nrf52811.h>
524 #elif defined(NRF52820_XXAA)
525     #include <nrfx_config_nrf52820.h>
526 #elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB)
527     #include <nrfx_config_nrf52832.h>
528 #elif defined(NRF52833_XXAA)
529     #include <nrfx_config_nrf52833.h>
530 #elif defined(NRF52840_XXAA)
531     #include <nrfx_config_nrf52840.h>
532 #elif defined(NRF5340_XXAA_APPLICATION)
533     #include <nrfx_config_nrf5340_application.h>
534 #elif defined(NRF5340_XXAA_NETWORK)
535     #include <nrfx_config_nrf5340_network.h>
536 #elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA)
537     #include <nrfx_config_nrf91.h>
538 #else
539     #error "Unknown device."
540 #endif
541 
542 #endif // NRFX_CONFIG_H__
543