1 /*******************************************************************************
2 * @file rsi_retention.h
3 *******************************************************************************
4 * # License
5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6 *******************************************************************************
7 *
8 * SPDX-License-Identifier: Zlib
9 *
10 * The licensor of this software is Silicon Laboratories Inc.
11 *
12 * This software is provided 'as-is', without any express or implied
13 * warranty. In no event will the authors be held liable for any damages
14 * arising from the use of this software.
15 *
16 * Permission is granted to anyone to use this software for any purpose,
17 * including commercial applications, and to alter it and redistribute it
18 * freely, subject to the following restrictions:
19 *
20 * 1. The origin of this software must not be misrepresented; you must not
21 * claim that you wrote the original software. If you use this software
22 * in a product, an acknowledgment in the product documentation would be
23 * appreciated but is not required.
24 * 2. Altered source versions must be plainly marked as such, and must not be
25 * misrepresented as being the original software.
26 * 3. This notice may not be removed or altered from any source distribution.
27 *
28 ******************************************************************************/
29
30 /**
31 * Includes
32 */
33
34 #ifndef __RSI_RETENTION_H__
35 #define __RSI_RETENTION_H__
36 #include "rsi_ccp_common.h"
37 #include "rsi_power_save.h"
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /*NPSS GPIO PIN MUX VALEUS*/
44 #define NPSS_GPIO_STATUS (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x14))
45 #define NPSS_GPIO_CONFIG_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x10))
46 #define NPSS_GPIO_CONFIG_CLR_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x8))
47
48 /*NPSS GPIO PIN MUX VALEUS*/
49 #define NPSSGPIO_PIN_MUX_MODE0 0
50 #define NPSSGPIO_PIN_MUX_MODE1 1
51 #define NPSSGPIO_PIN_MUX_MODE2 2
52 #define NPSSGPIO_PIN_MUX_MODE3 3
53 #define NPSSGPIO_PIN_MUX_MODE4 4
54 #define NPSSGPIO_PIN_MUX_MODE5 5
55 #define NPSSGPIO_PIN_MUX_MODE6 6
56 #define NPSSGPIO_PIN_MUX_MODE7 7
57 /*@note : Please refer to pin MUX excel to configure in desired mode
58 * */
59 /*EDGE INTERRUPT MODE */
60 #define RISING_EDGE 0
61 #define FALLING_EDGE 1
62 #define BOTH_FALL_RISE_EDGE 3
63
64 /*NPSS GPIO pin interrupt edge configuration */
65 #define NPSS_INTR_RISING_EDGE 1
66 #define NPSS_INTR_FALLING_EDGE 0
67
68 /*NPSS GPIO pin direction */
69 #define NPSS_GPIO_DIR_INPUT 1
70 #define NPSS_GPIO_DIR_OUTPUT 0
71
72 /*NPSS GPIO pin interrupt levels*/
73 #define NPSS_GPIO_INTR_HIGH 1
74 #define NPSS_GPIO_INTR_LOW 0
75
76 /*NPSS GPIO pin defines */
77 #define NPSS_GPIO_0 0
78 #define NPSS_GPIO_1 1
79 #define NPSS_GPIO_2 2
80 #define NPSS_GPIO_3 3
81 #define NPSS_GPIO_4 4
82
83 /*NPSS GPIO Interrupt defines */
84 #define NPSS_GPIO_0_INTR BIT(0)
85 #define NPSS_GPIO_1_INTR BIT(1)
86 #define NPSS_GPIO_2_INTR BIT(2)
87 #define NPSS_GPIO_3_INTR BIT(3)
88 #define NPSS_GPIO_4_INTR BIT(4)
89
90 /**
91 * \ingroup RSI_SPECIFIC_DRIVERS
92 * \defgroup RSI_NPSSGPIO RSI:RS1xxxx NPSSGPIO
93 * @{
94 *
95 */
96
97 /**
98 * @brief This API is used to set the NPSS GPIO pin MUX (mode)
99 *@param[in] pin: is NPSS GPIO pin number (0...4)
100 *@param[in] mux : is NPSS GPIO MUX value
101 *@return : none
102 * */
RSI_NPSSGPIO_SetPinMux(uint8_t pin,uint8_t mux)103 STATIC INLINE void RSI_NPSSGPIO_SetPinMux(uint8_t pin, uint8_t mux)
104 {
105 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = (unsigned int)(mux & 0x07);
106 }
107
108 /**
109 * @fn void RSI_NPSSGPIO_InputBufferEn(uint8_t pin , boolean_t enable)
110 * @brief This API is used to enable/disable NPSS GPIO input buffer
111 *@param[in] pin: is NPSS GPIO pin number (0...4)
112 *@param[in] enable: is enable / disable NPSS GPIO input buffer
113 * 1- Enable
114 * 0- Disable
115 *@return : none
116 * */
RSI_NPSSGPIO_InputBufferEn(uint8_t pin,boolean_t enable)117 STATIC INLINE void RSI_NPSSGPIO_InputBufferEn(uint8_t pin, boolean_t enable)
118 {
119 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = (unsigned int)(enable & 0x01);
120 }
121
122 /**
123 * @brief This API is used to set the direction of the NPSS GPIO
124 *@param[in] pin: is NPSS GPIO pin number (0...4)
125 *@param[in] dir: is direction value (Input / Output)
126 * 1- Input Direction
127 * 0- Output Direction
128 *@return : none
129 * */
RSI_NPSSGPIO_SetDir(uint8_t pin,boolean_t dir)130 STATIC INLINE void RSI_NPSSGPIO_SetDir(uint8_t pin, boolean_t dir)
131 {
132 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN = (unsigned int)(dir & 0x01);
133 }
134
135 /**
136 * @brief This API is used to Get the direction of the NPSS GPIO
137 *@param[in] pin: is NPSS GPIO pin number (0...4)
138 * @return : returns the GPIO pin direction
139 * */
RSI_NPSSGPIO_GetDir(uint8_t pin)140 STATIC INLINE boolean_t RSI_NPSSGPIO_GetDir(uint8_t pin)
141 {
142 return MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN;
143 }
144
145 /**
146 * @brief This API is used to set the NPSS GPIO pin value
147 *@param[in] pin: is NPSS GPIO pin number (0...4)
148 *@param[in] val: is NPSS GPIO pin value 0 or 1
149 * @return none
150 */
RSI_NPSSGPIO_SetPin(uint8_t pin,boolean_t val)151 STATIC INLINE void RSI_NPSSGPIO_SetPin(uint8_t pin, boolean_t val)
152 {
153 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = (unsigned int)(val & 0x01);
154 }
155
156 /**
157 * @brief This API is used to Get the NPSS GPIO pin value
158 *@param[in] pin: is NPSS GPIO pin number (0...4)
159 * @return returns the pin logical state of pin
160 */
RSI_NPSSGPIO_GetPin(uint8_t pin)161 STATIC INLINE boolean_t RSI_NPSSGPIO_GetPin(uint8_t pin)
162 {
163 return (NPSS_GPIO_STATUS >> pin) & 0x01;
164 }
165
166 /**
167 * @brief This API is used to select NPSS GPIO wake up detection when in sleep
168 *@param[in] pin: is NPSS GPIO pin number (0...4)
169 *@param[in] level :Gpio polarity to wake up from sleep
170 * 1 - When signal is High
171 * 0 - When signal is Low
172 *@return : none
173 * */
RSI_NPSSGPIO_SetPolarity(uint8_t pin,boolean_t level)174 STATIC INLINE void RSI_NPSSGPIO_SetPolarity(uint8_t pin, boolean_t level)
175 {
176 MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_POLARITY = (unsigned int)(level & 0x01);
177 }
178
179 /**
180 * @brief This API is used to set the GPIO to wake from deep sleep
181 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
182 * @return none
183 */
RSI_NPSSGPIO_SetWkpGpio(uint8_t npssGpioPinIntr)184 STATIC INLINE void RSI_NPSSGPIO_SetWkpGpio(uint8_t npssGpioPinIntr)
185 {
186 MCU_FSM->GPIO_WAKEUP_REGISTER |= npssGpioPinIntr;
187 }
188
189 /**
190 * @brief This API is used to clear the GPIO to wake from deep sleep
191 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
192 * @return none
193 */
RSI_NPSSGPIO_ClrWkpGpio(uint8_t npssGpioPinIntr)194 STATIC INLINE void RSI_NPSSGPIO_ClrWkpGpio(uint8_t npssGpioPinIntr)
195 {
196 MCU_FSM->GPIO_WAKEUP_REGISTER &= ~npssGpioPinIntr;
197 }
198
199 /**
200 * @brief This API is used to mask the NPSS GPIO interrupt
201 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
202 * @return none
203 */
RSI_NPSSGPIO_IntrMask(uint8_t npssGpioPinIntr)204 STATIC INLINE void RSI_NPSSGPIO_IntrMask(uint8_t npssGpioPinIntr)
205 {
206 NPSS_INTR_MASK_SET_REG = (npssGpioPinIntr << 1);
207 }
208
209 /**
210 * @brief This API is used to un mask the NPSS GPIO interrupt
211 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
212 * @return none
213 */
RSI_NPSSGPIO_IntrUnMask(uint8_t npssGpioPinIntr)214 STATIC INLINE void RSI_NPSSGPIO_IntrUnMask(uint8_t npssGpioPinIntr)
215 {
216 NPSS_INTR_MASK_CLR_REG = (npssGpioPinIntr << 1);
217 }
218
219 /**
220 * @brief This API is used to un mask the NPSS GPIO interrupt
221 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
222 * @return none
223 */
RSI_NPSSGPIO_SetIntFallEdgeEnable(uint8_t npssGpioPinIntr)224 STATIC INLINE void RSI_NPSSGPIO_SetIntFallEdgeEnable(uint8_t npssGpioPinIntr)
225 {
226 NPSS_GPIO_CONFIG_REG |= (npssGpioPinIntr << 8);
227 }
228
229 /**
230 * @brief This API is used to un mask the NPSS GPIO interrupt
231 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
232 * @return none
233 */
RSI_NPSSGPIO_ClrIntFallEdgeEnable(uint8_t npssGpioPinIntr)234 STATIC INLINE void RSI_NPSSGPIO_ClrIntFallEdgeEnable(uint8_t npssGpioPinIntr)
235 {
236 NPSS_GPIO_CONFIG_REG &= (uint32_t)(~(npssGpioPinIntr << 8));
237 }
238
239 /**
240 * @brief This API is used to Set the rise edge interrupt detection for NPSS GPIO
241 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
242 * @return none
243 */
RSI_NPSSGPIO_SetIntRiseEdgeEnable(uint8_t npssGpioPinIntr)244 STATIC INLINE void RSI_NPSSGPIO_SetIntRiseEdgeEnable(uint8_t npssGpioPinIntr)
245 {
246 NPSS_GPIO_CONFIG_REG |= (npssGpioPinIntr << 0);
247 }
248
249 /**
250 * @brief This API is used to Enable rise edge interrupt detection for NPSS GPIO
251 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
252 * @return none
253 */
RSI_NPSSGPIO_ClrIntRiseEdgeEnable(uint8_t npssGpioPinIntr)254 STATIC INLINE void RSI_NPSSGPIO_ClrIntRiseEdgeEnable(uint8_t npssGpioPinIntr)
255 {
256 NPSS_GPIO_CONFIG_REG &= (uint32_t)(~(npssGpioPinIntr << 0));
257 }
258
259 /**
260 * @brief This API is used to un mask the NPSS GPIO interrupt
261 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
262 * @return none
263 */
RSI_NPSSGPIO_SetIntLevelHighEnable(uint8_t npssGpioPinIntr)264 STATIC INLINE void RSI_NPSSGPIO_SetIntLevelHighEnable(uint8_t npssGpioPinIntr)
265 {
266 NPSS_GPIO_CONFIG_REG |= (npssGpioPinIntr << 24);
267 }
268
269 /**
270 * @brief This API is used to un mask the NPSS GPIO interrupt
271 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
272 * @return none
273 */
RSI_NPSSGPIO_ClrIntLevelHighEnable(uint8_t npssGpioPinIntr)274 STATIC INLINE void RSI_NPSSGPIO_ClrIntLevelHighEnable(uint8_t npssGpioPinIntr)
275 {
276 NPSS_GPIO_CONFIG_REG &= (uint32_t)(~(npssGpioPinIntr << 24));
277 }
278
279 /**
280 * @brief This API is used to un mask the NPSS GPIO interrupt
281 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
282 * @return none
283 */
RSI_NPSSGPIO_SetIntLevelLowEnable(uint8_t npssGpioPinIntr)284 STATIC INLINE void RSI_NPSSGPIO_SetIntLevelLowEnable(uint8_t npssGpioPinIntr)
285 {
286 NPSS_GPIO_CONFIG_REG |= (npssGpioPinIntr << 16);
287 }
288
289 /**
290 * @brief This API is used clear the interrupt low level enable
291 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
292 * @return none
293 */
RSI_NPSSGPIO_ClrIntLevelLowEnable(uint8_t npssGpioPinIntr)294 STATIC INLINE void RSI_NPSSGPIO_ClrIntLevelLowEnable(uint8_t npssGpioPinIntr)
295 {
296 NPSS_GPIO_CONFIG_REG &= (uint32_t)(~(npssGpioPinIntr << 16));
297 }
298
299 /**
300 * @brief This API is used to clear NPSS GPIO interrupt
301 * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts
302 * @return none
303 */
RSI_NPSSGPIO_ClrIntr(uint8_t npssGpioPinIntr)304 STATIC INLINE void RSI_NPSSGPIO_ClrIntr(uint8_t npssGpioPinIntr)
305 {
306 NPSS_INTR_CLEAR_REG = (npssGpioPinIntr << 1);
307 }
308
309 /**
310 * @brief This API is used to get the NPSS GPIO interrupt status
311 * @return returns the GPIO status
312 */
RSI_NPSSGPIO_GetIntrStatus(void)313 STATIC INLINE uint8_t RSI_NPSSGPIO_GetIntrStatus(void)
314 {
315 return (NPSS_INTR_STATUS_REG >> 1) & 0x1F;
316 }
317 /*
318 *@}
319 */
320
321 #ifdef __cplusplus
322 }
323 #endif
324
325 /*End of file not truncated*/
326 #endif /*__RSI_RETENTION_H__*/
327
