1 /*
2  * Copyright (c) 2022 Nordic Semiconductor ASA
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM6001_GPIO_H_
7 #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM6001_GPIO_H_
8 
9 /**
10  * @brief nPM6001-specific GPIO Flags
11  * @defgroup gpio_interface_npm6001 nPM6001-specific GPIO Flags
12  *
13  * The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
14  * follows:
15  *
16  * - Bit 8: Drive strength (0=NORMAL, 1=HIGH)
17  * - Bit 9: Input type (0=SCHMITT, 1=CMOS)
18  *
19  * @ingroup gpio_interface
20  * @{
21  */
22 
23 /**
24  * @name nPM6001 GPIO drive strength flags
25  * @brief nPM6001 GPIO drive strength flags
26  * @{
27  */
28 
29 /** @cond INTERNAL_HIDDEN */
30 /** Drive mode field mask */
31 #define NPM6001_GPIO_DRIVE_MSK	0x0100U
32 /** @endcond */
33 
34 /** Normal drive */
35 #define NPM6001_GPIO_DRIVE_NORMAL	(0U << 8U)
36 /** High drive */
37 #define NPM6001_GPIO_DRIVE_HIGH		(1U << 8U)
38 
39 /** @} */
40 
41 /**
42  * @name nPM6001 GPIO drive strength flags
43  * @brief nPM6001 GPIO drive strength flags
44  * @{
45  */
46 
47 /** @cond INTERNAL_HIDDEN */
48 /** Input type field mask */
49 #define NPM6001_GPIO_SENSE_MSK	0x0200U
50 /** @endcond */
51 
52 /** Schmitt trigger input type */
53 #define NPM6001_GPIO_SENSE_SCHMITT	(0U << 9U)
54 /** CMOS input type */
55 #define NPM6001_GPIO_SENSE_CMOS		(1U << 9U)
56 
57 /** @} */
58 
59 /** @} */
60 
61 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_ */
62