1 /* 2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * Copyright (C) 2017-2023 Nuvoton Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef NPCM845x_ARM_DEF_H 10 #define NPCM845x_ARM_DEF_H 11 12 #include <arch.h> 13 #include <common/interrupt_props.h> 14 #include <common/tbbr/tbbr_img_def.h> 15 #include <drivers/arm/gic_common.h> 16 #include <lib/utils_def.h> 17 #include <lib/xlat_tables/xlat_tables_defs.h> 18 #include <plat/arm/common/smccc_def.h> 19 #include <plat/common/common_def.h> 20 21 /* This flag will add zones to the MMU so that it will be possible to debug */ 22 #ifdef NPCM845X_DEBUG 23 #define ALLOW_DEBUG_MMU 24 #undef ALLOW_DEBUG_MMU 25 #endif /* NPCM845X_DEBUG */ 26 27 #undef CONFIG_TARGET_ARBEL_PALLADIUM 28 /****************************************************************************** 29 * Definitions common to all ARM standard platforms 30 *****************************************************************************/ 31 32 /* 33 * Root of trust key hash lengths 34 */ 35 #define ARM_ROTPK_HEADER_LEN 19 36 #define ARM_ROTPK_HASH_LEN 32 37 38 /* Special value used to verify platform parameters from BL2 to BL31 */ 39 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 40 41 /* No need for system because we have only one cluster */ 42 #define ARM_SYSTEM_COUNT U(0) 43 44 #define ARM_CACHE_WRITEBACK_SHIFT 6 45 46 /* 47 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. 48 * The power levels have a 1:1 mapping with the MPIDR affinity levels. 49 */ 50 /* In NPCM845x - refers to cores */ 51 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 52 53 /* In NPCM845x - refers to cluster */ 54 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 55 56 /* No need for additional settings because the platform doesn't have system */ 57 58 /* 59 * Macros for local power states in ARM platforms encoded by State-ID field 60 * within the power-state parameter. 61 */ 62 #define NPCM845x_PLAT_PRIMARY_CPU U(0x0) 63 #define NPCM845x_CLUSTER_COUNT U(1) 64 65 #ifdef SECONDARY_BRINGUP 66 #define NPCM845x_MAX_CPU_PER_CLUSTER U(2) 67 #define NPCM845x_PLATFORM_CORE_COUNT U(2) 68 #define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(2) 69 #else 70 #define NPCM845x_MAX_CPU_PER_CLUSTER U(4) 71 #define NPCM845x_PLATFORM_CORE_COUNT U(4) 72 #define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(4) 73 #endif /* SECONDARY_BRINGUP */ 74 75 #define NPCM845x_SYSTEM_COUNT U(0) 76 77 /* Memory mapping for NPCM845x */ 78 #define NPCM845x_REG_BASE 0xf0000000 79 #define NPCM845x_REG_SIZE 0x0ff16000 80 81 /* 82 * DRAM 83 * 0x3fffffff +-------------+ 84 * | BL33 | (non-secure) 85 * 0x06200000 +-------------+ 86 * | BL32 SHARED | (non-secure) 87 * 0x06000000 +-------------+ 88 * | BL32 | (secure) 89 * 0x02100000 +-------------+ 90 * | BL31 | (secure) 91 * 0x02000000 +-------------+ 92 * | | (non-secure) 93 * 0x00000000 +-------------+ 94 * 95 * Trusted ROM 96 * 0xfff50000 +-------------+ 97 * | BL1 (ro) | 98 * 0xfff40000 +-------------+ 99 */ 100 101 #define ARM_DRAM1_BASE ULL(0x00000000) 102 #ifndef CONFIG_TARGET_ARBEL_PALLADIUM 103 /* 104 * Although npcm845x is 4G, 105 * consider only 2G Trusted Firmware memory allocation 106 */ 107 #define ARM_DRAM1_SIZE ULL(0x37000000) 108 #else 109 #define ARM_DRAM1_SIZE ULL(0x10000000) 110 #define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1U) 111 #endif /* CONFIG_TARGET_ARBEL_PALLADIUM */ 112 113 /* 114 * The top 16MB of DRAM1 is configured as secure access only using the TZC 115 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 116 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 117 */ 118 119 /* Check for redundancy */ 120 #ifdef NPCM845X_DEBUG 121 #define PLAT_ARM_NS_IMAGE_BASE 0x0 122 #endif /* NPCM845X_DEBUG */ 123 124 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) 125 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 126 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 127 ARM_SCP_TZC_DRAM1_SIZE - 1U) 128 129 /* 130 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime 131 * firmware. This region is meant to be NOLOAD and will not be zero 132 * initialized. Data sections with the attribute `arm_el3_tzc_dram` 133 * will be placed here. 134 * 135 * NPCM845x - Currently the platform doesn't have EL3 implementation 136 * on secured DRAM. 137 */ 138 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 139 ARM_EL3_TZC_DRAM1_SIZE) 140 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ 141 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 142 ARM_EL3_TZC_DRAM1_SIZE - 1U) 143 144 #define ARM_AP_TZC_DRAM1_BASE 0x02100000 145 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 146 (ARM_SCP_TZC_DRAM1_SIZE + \ 147 ARM_EL3_TZC_DRAM1_SIZE)) 148 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 149 ARM_AP_TZC_DRAM1_SIZE - 1U) 150 151 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 152 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 153 154 #ifdef SPD_opteed 155 /* 156 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 157 * load/authenticate the trusted os extra image. The first 512KB of 158 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 159 * for OPTEE is paged image which only include the paging part using 160 * virtual memory but without "init" data. OPTEE will copy the "init" data 161 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 162 * extra image behind the "init" data. 163 */ 164 #define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 165 #define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 166 #define BL32_BASE ARM_AP_TZC_DRAM1_BASE 167 #define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 168 ARM_AP_TZC_DRAM1_SIZE) 169 170 #define ARM_OPTEE_PAGEABLE_LOAD_BASE ( \ 171 ARM_AP_TZC_DRAM1_BASE + ARM_AP_TZC_DRAM1_SIZE - \ 172 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 173 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 174 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 175 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 176 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 177 MT_MEMORY | MT_RW | MT_SECURE) 178 179 /* 180 * Map the memory for the OP-TEE core (also known as OP-TEE pager 181 * when paging support is enabled). 182 */ 183 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 184 BL32_BASE, BL32_LIMIT - BL32_BASE, \ 185 MT_MEMORY | MT_RW | MT_SECURE) 186 #endif /* SPD_opteed */ 187 188 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 189 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 190 ARM_TZC_DRAM1_SIZE) 191 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 192 ARM_NS_DRAM1_SIZE - 1U) 193 194 /* The platform doesn't use DRAM2 but it has to have a value for calculation */ 195 #define ARM_DRAM2_BASE 0 /* PLAT_ARM_DRAM_BASE */ 196 #define ARM_DRAM2_SIZE 1 /* PLAT_ARM_DRAM_SIZE */ 197 #define ARM_DRAM2_END (ARM_DRAM2_BASE + ARM_DRAM2_SIZE - 1U) 198 199 #define FIRST_EXT_INTERRUPT_NUM U(32) 200 #define ARM_IRQ_SEC_PHY_TIMER (U(29) + FIRST_EXT_INTERRUPT_NUM) 201 202 #define ARM_IRQ_SEC_SGI_0 8 203 #define ARM_IRQ_SEC_SGI_1 9 204 #define ARM_IRQ_SEC_SGI_2 10 205 #define ARM_IRQ_SEC_SGI_3 11 206 #define ARM_IRQ_SEC_SGI_4 12 207 #define ARM_IRQ_SEC_SGI_5 13 208 #define ARM_IRQ_SEC_SGI_6 14 209 #define ARM_IRQ_SEC_SGI_7 15 210 211 /* 212 * Define a list of Group 1 Secure and Group 0 interrupt properties 213 * as per GICv3 terminology. On a GICv2 system or mode, 214 * the lists will be merged and treated as Group 0 interrupts. 215 */ 216 #define ARM_G1S_IRQ_PROPS(grp) \ 217 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 218 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \ 219 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 220 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ 221 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 222 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ 223 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 224 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ 225 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 226 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ 227 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 228 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ 229 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 230 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE) 231 232 #define ARM_G0_IRQ_PROPS(grp) \ 233 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 234 PLAT_SDEI_NORMAL_PRI, (grp), GIC_INTR_CFG_EDGE), \ 235 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 236 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE) 237 238 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 239 ARM_SHARED_RAM_BASE, ARM_SHARED_RAM_SIZE, \ 240 MT_DEVICE | MT_RW | MT_SECURE) 241 242 #ifdef ALLOW_DEBUG_MMU 243 /* In order to be able to debug, 244 * the platform needs to add BL33 and BL32 to MMU as well. 245 */ 246 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 247 ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_SIZE, \ 248 MT_MEMORY | MT_RW | MT_NS) 249 250 #ifdef BL32_BASE 251 #define ARM_MAP_BL32_CORE_MEM MAP_REGION_FLAT( \ 252 BL32_BASE, BL32_LIMIT - BL32_BASE, \ 253 MT_MEMORY | MT_RW | MT_SECURE) 254 #endif /* BL32_BASE */ 255 256 #ifdef NPCM845X_DEBUG 257 #define ARM_MAP_SEC_BB_MEM MAP_REGION_FLAT( \ 258 0xFFFB0000, 0x20000, \ 259 MT_MEMORY | MT_RW | MT_NS) 260 #endif /* NPCM845X_DEBUG */ 261 #endif /* BL32_BASE */ 262 263 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 264 ARM_DRAM2_BASE, ARM_DRAM2_SIZE, \ 265 MT_MEMORY | MT_RW | MT_NS) 266 267 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 268 TSP_SEC_MEM_BASE, TSP_SEC_MEM_SIZE, \ 269 MT_MEMORY | MT_RW | MT_SECURE) 270 271 #if ARM_BL31_IN_DRAM 272 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 273 BL31_BASE, PLAT_ARM_MAX_BL31_SIZE, \ 274 MT_MEMORY | MT_RW | MT_SECURE) 275 #endif /* ARM_BL31_IN_DRAM */ 276 277 /* Currently the platform doesn't have EL3 implementation on secured DRAM. */ 278 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 279 ARM_EL3_TZC_DRAM1_BASE, \ 280 ARM_EL3_TZC_DRAM1_SIZE, \ 281 MT_MEMORY | MT_RW | MT_SECURE) 282 283 #if defined(SPD_spmd) 284 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 285 PLAT_ARM_TRUSTED_DRAM_BASE, \ 286 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 287 MT_MEMORY | MT_RW | MT_SECURE) 288 #endif /* SPD_spmd */ 289 290 /* 291 * Mapping for the BL1 RW region. This mapping is needed by BL2 292 * in order to share the Mbed TLS heap. Since the heap is allocated 293 * inside BL1, it resides in the BL1 RW region. Hence, BL2 needs access 294 * to the BL1 RW region in order to be able to access the heap. 295 */ 296 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 297 BL1_RW_BASE, BL1_RW_LIMIT - BL1_RW_BASE, \ 298 MT_MEMORY | MT_RW | EL3_PAS) 299 300 /* 301 * If SEPARATE_CODE_AND_RODATA=1 the platform will define a region 302 * for each section, otherwise one region containing both sections 303 * is defined. 304 */ 305 #if SEPARATE_CODE_AND_RODATA 306 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 307 BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \ 308 MT_CODE | EL3_PAS), \ 309 MAP_REGION_FLAT(BL_RO_DATA_BASE, \ 310 BL_RO_DATA_END - BL_RO_DATA_BASE, \ 311 MT_RO_DATA | EL3_PAS) 312 #else 313 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 314 BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \ 315 MT_CODE | EL3_PAS) 316 #endif /* SEPARATE_CODE_AND_RODATA */ 317 318 #if USE_COHERENT_MEM 319 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 320 BL_COHERENT_RAM_BASE, \ 321 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 322 MT_DEVICE | MT_RW | EL3_PAS) 323 #endif /* USE_COHERENT_MEM */ 324 325 #if USE_ROMLIB 326 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 327 ROMLIB_RO_BASE, \ 328 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE, \ 329 MT_CODE | MT_SECURE) 330 331 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 332 ROMLIB_RW_BASE, \ 333 ROMLIB_RW_END - ROMLIB_RW_BASE, \ 334 MT_MEMORY | MT_RW | MT_SECURE) 335 #endif /* USE_ROMLIB */ 336 337 /* 338 * Map mem_protect flash region with read and write permissions 339 */ 340 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT( \ 341 PLAT_ARM_MEM_PROT_ADDR, \ 342 V2M_FLASH_BLOCK_SIZE, \ 343 MT_DEVICE | MT_RW | MT_SECURE) 344 /* 345 * Map the region for device tree configuration with read and write permissions 346 */ 347 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ 348 ARM_BL_RAM_BASE, \ 349 (ARM_FW_CONFIGS_LIMIT - ARM_BL_RAM_BASE), \ 350 MT_MEMORY | MT_RW | MT_SECURE) 351 352 /* 353 * The max number of regions like RO(code), coherent and data required by 354 * different BL stages which need to be mapped in the MMU. 355 */ 356 #define ARM_BL_REGIONS 10 357 358 #define MAX_MMAP_REGIONS ( \ 359 PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) 360 361 /* Memory mapped Generic timer interfaces */ 362 #define ARM_SYS_CNTCTL_BASE UL(0XF07FC000) 363 364 #define ARM_CONSOLE_BAUDRATE 115200 365 366 /* 367 * The TBBR document specifies a watchdog timeout of 256 seconds. SP805 368 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) 369 */ 370 #define ARM_TWDG_TIMEOUT_SEC 128 371 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 372 ARM_TWDG_TIMEOUT_SEC) 373 374 /****************************************************************************** 375 * Required platform porting definitions common to all ARM standard platforms 376 *****************************************************************************/ 377 378 /* 379 * Some data must be aligned on the biggest cache line size in the platform. 380 * This is known only to the platform as it might have a combination of 381 * integrated and external caches (64 on Arbel). 382 */ 383 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 384 385 /* 386 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 387 * and limit. Leave enough space of BL2 meminfo. 388 */ 389 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 390 #define ARM_FW_CONFIG_LIMIT ( \ 391 (ARM_BL_RAM_BASE + PAGE_SIZE) + (PAGE_SIZE / 2U)) 392 393 /* 394 * Boot parameters passed from BL2 to BL31/BL32 are stored here 395 */ 396 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 397 #define ARM_BL2_MEM_DESC_LIMIT ( \ 398 ARM_BL2_MEM_DESC_BASE + (PAGE_SIZE / 2U)) 399 400 /* 401 * Define limit of firmware configuration memory: 402 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 403 */ 404 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) 405 406 /******************************************************************************* 407 * BL1 specific defines. 408 * BL1 RW data is relocated from ROM to RAM at runtime so we need 409 * two sets of addresses. 410 ******************************************************************************/ 411 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 412 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + \ 413 (PLAT_ARM_TRUSTED_ROM_SIZE - PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 414 /* 415 * Put BL1 RW at the top of the Trusted SRAM. 416 */ 417 #define BL1_RW_BASE (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE - \ 418 (PLAT_ARM_MAX_BL1_RW_SIZE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 419 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 420 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 421 422 #define ROMLIB_RO_BASE BL1_RO_LIMIT 423 #define ROMLIB_RO_LIMIT ( \ 424 PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 425 426 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 427 #define ROMLIB_RW_END ( \ 428 ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 429 430 /****************************************************************************** 431 * BL2 specific defines. 432 *****************************************************************************/ 433 #if BL2_AT_EL3 434 /* Put BL2 towards the middle of the Trusted SRAM */ 435 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 436 PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) 437 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 438 #else 439 /* 440 * Put BL2 just below BL1. 441 */ 442 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 443 #define BL2_LIMIT BL1_RW_BASE 444 #endif /* BL2_AT_EL3 */ 445 446 /******************************************************************************* 447 * BL31 specific defines. 448 ******************************************************************************/ 449 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 450 /* 451 * Put BL31 at the bottom of TZC secured DRAM 452 */ 453 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 454 #define BL31_LIMIT ( \ 455 ARM_AP_TZC_DRAM1_BASE + PLAT_ARM_MAX_BL31_SIZE) 456 457 /* 458 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 459 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 460 */ 461 #if SEPARATE_NOBITS_REGION 462 #define BL31_NOBITS_BASE BL2_BASE 463 #define BL31_NOBITS_LIMIT BL2_LIMIT 464 #endif /* SEPARATE_NOBITS_REGION */ 465 #elif (RESET_TO_BL31) 466 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 467 #if !ENABLE_PIE 468 #error "BL31 must be a PIE if RESET_TO_BL31=1." 469 #endif /* !ENABLE_PIE */ 470 /* 471 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 472 * used for building BL31 and not used for loading BL31. 473 */ 474 #define NEW_SRAM_ALLOCATION 475 476 #ifdef NEW_SRAM_ALLOCATION 477 #define BL31_BASE 0x20001000 478 #else 479 #define BL31_BASE 0x20001000 480 #endif /* NEW_SRAM_ALLOCATION */ 481 482 #define BL31_LIMIT BL2_BASE /* PLAT_ARM_MAX_BL31_SIZE */ 483 #else 484 /* Put BL31 below BL2 in the Trusted SRAM.*/ 485 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) - \ 486 PLAT_ARM_MAX_BL31_SIZE) 487 #define BL31_PROGBITS_LIMIT BL2_BASE 488 489 /* 490 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. 491 * This is because in the BL2_AT_EL3 configuration, BL2 is always resident. 492 */ 493 #if BL2_AT_EL3 494 #define BL31_LIMIT BL2_BASE 495 #else 496 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 497 #endif /* BL2_AT_EL3 */ 498 #endif /* ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION */ 499 500 /* 501 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is 502 * no SPD and no SPM-MM, as they are the only ones that can be used as BL32. 503 */ 504 #if defined(SPD_none) && !SPM_MM 505 #undef BL32_BASE 506 #endif /* SPD_none && !SPM_MM */ 507 508 /****************************************************************************** 509 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 510 *****************************************************************************/ 511 #define BL2U_BASE BL2_BASE 512 #define BL2U_LIMIT BL2_LIMIT 513 514 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 515 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 516 517 /* 518 * ID of the secure physical generic timer interrupt used by the TSP. 519 */ 520 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 521 522 /* 523 * One cache line needed for bakery locks on ARM platforms 524 */ 525 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 526 527 /* Priority levels for ARM platforms */ 528 #define PLAT_RAS_PRI 0x10 529 #define PLAT_SDEI_CRITICAL_PRI 0x60 530 #define PLAT_SDEI_NORMAL_PRI 0x70 531 532 /* ARM platforms use 3 upper bits of secure interrupt priority */ 533 #define ARM_PRI_BITS 3 534 535 /* SGI used for SDEI signalling */ 536 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 537 538 #if SDEI_IN_FCONF 539 /* ARM SDEI dynamic private event max count */ 540 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 541 542 /* ARM SDEI dynamic shared event max count */ 543 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 544 #else 545 /* ARM SDEI dynamic private event numbers */ 546 #define ARM_SDEI_DP_EVENT_0 1000 547 #define ARM_SDEI_DP_EVENT_1 1001 548 #define ARM_SDEI_DP_EVENT_2 1002 549 550 /* ARM SDEI dynamic shared event numbers */ 551 #define ARM_SDEI_DS_EVENT_0 2000 552 #define ARM_SDEI_DS_EVENT_1 2001 553 #define ARM_SDEI_DS_EVENT_2 2002 554 555 #define ARM_SDEI_PRIVATE_EVENTS \ 556 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 557 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 558 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 559 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 560 561 #define ARM_SDEI_SHARED_EVENTS \ 562 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 563 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 564 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 565 #endif /* SDEI_IN_FCONF */ 566 567 #endif /* ARM_DEF_H */ 568
