1 /** 2 * 3 * \file 4 * 5 * \brief This module contains NMC1000 bus wrapper APIs declarations. 6 * 7 * Copyright (c) 2016-2017 Atmel Corporation. All rights reserved. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions are met: 15 * 16 * 1. Redistributions of source code must retain the above copyright notice, 17 * this list of conditions and the following disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above copyright notice, 20 * this list of conditions and the following disclaimer in the documentation 21 * and/or other materials provided with the distribution. 22 * 23 * 3. The name of Atmel may not be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 42 #ifndef _NM_BUS_WRAPPER_H_ 43 #define _NM_BUS_WRAPPER_H_ 44 45 #include "common/include/nm_common.h" 46 47 /** 48 BUS Type 49 **/ 50 #define NM_BUS_TYPE_I2C ((uint8)0) 51 #define NM_BUS_TYPE_SPI ((uint8)1) 52 #define NM_BUS_TYPE_UART ((uint8)2) 53 /** 54 IOCTL commands 55 **/ 56 #define NM_BUS_IOCTL_R ((uint8)0) /*!< Read only ==> I2C/UART. Parameter:tstrNmI2cDefault/tstrNmUartDefault */ 57 #define NM_BUS_IOCTL_W ((uint8)1) /*!< Write only ==> I2C/UART. Parameter type tstrNmI2cDefault/tstrNmUartDefault*/ 58 #define NM_BUS_IOCTL_W_SPECIAL ((uint8)2) /*!< Write two buffers within the same transaction 59 (same start/stop conditions) ==> I2C only. Parameter:tstrNmI2cSpecial */ 60 #define NM_BUS_IOCTL_RW ((uint8)3) /*!< Read/Write at the same time ==> SPI only. Parameter:tstrNmSpiRw */ 61 62 #define NM_BUS_IOCTL_WR_RESTART ((uint8)4) /*!< Write buffer then made restart condition then read ==> I2C only. parameter:tstrNmI2cSpecial */ 63 /** 64 * @struct tstrNmBusCapabilities 65 * @brief Structure holding bus capabilities information 66 * @sa NM_BUS_TYPE_I2C, NM_BUS_TYPE_SPI 67 */ 68 typedef struct 69 { 70 uint16 u16MaxTrxSz; /*!< Maximum transfer size. Must be >= 16 bytes*/ 71 } tstrNmBusCapabilities; 72 73 /** 74 * @struct tstrNmI2cDefault 75 * @brief Structure holding I2C default operation parameters 76 * @sa NM_BUS_IOCTL_R, NM_BUS_IOCTL_W 77 */ 78 typedef struct 79 { 80 uint8 u8SlaveAdr; 81 uint8 *pu8Buf; /*!< Operation buffer */ 82 uint16 u16Sz; /*!< Operation size */ 83 } tstrNmI2cDefault; 84 85 /** 86 * @struct tstrNmI2cSpecial 87 * @brief Structure holding I2C special operation parameters 88 * @sa NM_BUS_IOCTL_W_SPECIAL 89 */ 90 typedef struct 91 { 92 uint8 u8SlaveAdr; 93 uint8 *pu8Buf1; /*!< pointer to the 1st buffer */ 94 uint8 *pu8Buf2; /*!< pointer to the 2nd buffer */ 95 uint16 u16Sz1; /*!< 1st buffer size */ 96 uint16 u16Sz2; /*!< 2nd buffer size */ 97 } tstrNmI2cSpecial; 98 99 /** 100 * @struct tstrNmSpiRw 101 * @brief Structure holding SPI R/W parameters 102 * @sa NM_BUS_IOCTL_RW 103 */ 104 typedef struct 105 { 106 uint8 *pu8InBuf; /*!< pointer to input buffer. 107 Can be set to null and in this case zeros should be sent at MOSI */ 108 uint8 *pu8OutBuf; /*!< pointer to output buffer. 109 Can be set to null and in this case data from MISO can be ignored */ 110 uint16 u16Sz; /*!< Transfere size */ 111 } tstrNmSpiRw; 112 113 114 /** 115 * @struct tstrNmUartDefault 116 * @brief Structure holding UART default operation parameters 117 * @sa NM_BUS_IOCTL_R, NM_BUS_IOCTL_W 118 */ 119 typedef struct 120 { 121 uint8 *pu8Buf; /*!< Operation buffer */ 122 uint16 u16Sz; /*!< Operation size */ 123 } tstrNmUartDefault; 124 /*!< Bus capabilities. This structure must be declared at platform specific bus wrapper */ 125 extern tstrNmBusCapabilities egstrNmBusCapabilities; 126 127 128 #ifdef __cplusplus 129 extern "C" { 130 #endif 131 /** 132 * @fn nm_bus_init 133 * @brief Initialize the bus wrapper 134 * @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure 135 */ 136 sint8 nm_bus_init(void *); 137 138 /** 139 * @fn nm_bus_ioctl 140 * @brief send/receive from the bus 141 * @param [in] u8Cmd 142 * IOCTL command for the operation 143 * @param [in] pvParameter 144 * Arbitrary parameter depending on IOCTL 145 * @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure 146 * @note For SPI only, it's important to be able to send/receive at the same time 147 */ 148 sint8 nm_bus_ioctl(uint8 u8Cmd, void* pvParameter); 149 150 /** 151 * @fn nm_bus_deinit 152 * @brief De-initialize the bus wrapper 153 * @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure 154 */ 155 sint8 nm_bus_deinit(void); 156 157 /* 158 * @fn nm_bus_reinit 159 * @brief re-initialize the bus wrapper 160 * @param [in] void *config 161 * re-init configuration data 162 * @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure 163 */ 164 sint8 nm_bus_reinit(void *); 165 /* 166 * @fn nm_bus_get_chip_type 167 * @brief get chip type 168 * @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure 169 */ 170 #ifdef CONF_WINC_USE_UART 171 uint8 nm_bus_get_chip_type(void); 172 sint8 nm_bus_break(void); 173 #endif 174 #ifdef __cplusplus 175 } 176 #endif 177 178 #endif /*_NM_BUS_WRAPPER_H_*/ 179
