1 /* 2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef __NI_TOWER_APU_REG_H__ 9 #define __NI_TOWER_APU_REG_H__ 10 11 #include "tfm_hal_device_header.h" 12 13 #include <stdint.h> 14 15 #define NI_TOWER_MAX_APU_REGIONS 32 16 17 /** 18 * \brief NI-Tower APU register map 19 */ 20 __PACKED_STRUCT ni_tower_apu_reg_map { 21 __PACKED_STRUCT { 22 __IOM uint32_t prbar_low; 23 __IOM uint32_t prbar_high; 24 __IOM uint32_t prlar_low; 25 __IOM uint32_t prlar_high; 26 __IOM uint32_t prid_low; 27 __IOM uint32_t prid_high; 28 const uint32_t reserved_2[2]; 29 } region[NI_TOWER_MAX_APU_REGIONS]; 30 const uint32_t reserved_3[766]; 31 __IOM uint32_t apu_ctlr; 32 __IM uint32_t apu_iidr; 33 }; 34 35 /* Field definitions for prbar_low register */ 36 #define NI_TOWER_APU_REGION_ENABLE_POS (0U) 37 #define NI_TOWER_APU_REGION_ENABLE_MSK (0x1UL << NI_TOWER_APU_REGION_ENABLE_POS) 38 #define NI_TOWER_APU_REGION_ENABLE NI_TOWER_APU_REGION_ENABLE_MSK 39 #define NI_TOWER_APU_BR_POS (1U) 40 #define NI_TOWER_APU_BR_MSK (0x1UL << NI_TOWER_APU_BR_POS) 41 #define NI_TOWER_APU_BR NI_TOWER_APU_BR_MSK 42 #define NI_TOWER_APU_LOCK_POS (2U) 43 #define NI_TOWER_APU_LOCK_MSK (0x1UL << NI_TOWER_APU_LOCK_POS) 44 #define NI_TOWER_APU_LOCK NI_TOWER_APU_LOCK_MSK 45 46 /* Field definitions for prlar_low register */ 47 #define NI_TOWER_APU_ID_VALID_POS (0U) 48 #define NI_TOWER_APU_ID_VALID_MSK (0xFUL << NI_TOWER_APU_ID_VALID_POS) 49 #define NI_TOWER_APU_ID_VALID NI_TOWER_APU_ID_VALID_MSK 50 51 /* Field definitions for prid_low register */ 52 #define NI_TOWER_APU_ID_0_POS (0U) 53 #define NI_TOWER_APU_ID_0_MSK (0xFFUL << NI_TOWER_APU_ID_0_POS) 54 #define NI_TOWER_APU_ID_0 NI_TOWER_APU_ID_0_MSK 55 #define NI_TOWER_APU_PERM_0_POS (8U) 56 #define NI_TOWER_APU_PERM_0_MSK (0xFFUL << NI_TOWER_APU_PERM_0_POS) 57 #define NI_TOWER_APU_PERM_0 NI_TOWER_APU_PERM_0_MSK 58 #define NI_TOWER_APU_ID_1_POS (16U) 59 #define NI_TOWER_APU_ID_1_MSK (0xFFUL << NI_TOWER_APU_ID_1_POS) 60 #define NI_TOWER_APU_ID_1 NI_TOWER_APU_ID_1_MSK 61 #define NI_TOWER_APU_PERM_1_POS (24U) 62 #define NI_TOWER_APU_PERM_1_MSK (0xFFUL << NI_TOWER_APU_PERM_1_POS) 63 #define NI_TOWER_APU_PERM_1 NI_TOWER_APU_PERM_1_MSK 64 65 /* Field definitions for prid_high register */ 66 #define NI_TOWER_APU_ID_2_POS (0U) 67 #define NI_TOWER_APU_ID_2_MSK (0xFFUL << NI_TOWER_APU_ID_2_POS) 68 #define NI_TOWER_APU_ID_2 NI_TOWER_APU_ID_2_MSK 69 #define NI_TOWER_APU_PERM_2_POS (8U) 70 #define NI_TOWER_APU_PERM_2_MSK (0xFFUL << NI_TOWER_APU_PERM_2_POS) 71 #define NI_TOWER_APU_PERM_2 NI_TOWER_APU_PERM_2_MSK 72 #define NI_TOWER_APU_ID_3_POS (16U) 73 #define NI_TOWER_APU_ID_3_MSK (0xFFUL << NI_TOWER_APU_ID_3_POS) 74 #define NI_TOWER_APU_ID_3 NI_TOWER_APU_ID_3_MSK 75 #define NI_TOWER_APU_PERM_3_POS (24U) 76 #define NI_TOWER_APU_PERM_3_MSK (0xFFUL << NI_TOWER_APU_PERM_3_POS) 77 #define NI_TOWER_APU_PERM_3 NI_TOWER_APU_PERM_3_MSK 78 79 /* Field definitions for apu_ctlr register */ 80 #define NI_TOWER_APU_CTLR_APU_ENABLE_POS (0U) 81 #define NI_TOWER_APU_CTLR_APU_ENABLE_MSK (0x1UL << NI_TOWER_APU_CTLR_APU_ENABLE_POS) 82 #define NI_TOWER_APU_CTLR_APU_ENABLE NI_TOWER_APU_CTLR_APU_ENABLE_MSK 83 #define NI_TOWER_APU_CTLR_FMU_ERROR_EN_POS (1U) 84 #define NI_TOWER_APU_CTLR_FMU_ERROR_EN_MSK (0x1UL << NI_TOWER_APU_CTLR_FMU_ERROR_EN_POS) 85 #define NI_TOWER_APU_CTLR_FMU_ERROR_EN NI_TOWER_APU_CTLR_FMU_ERROR_EN_MSK 86 #define NI_TOWER_APU_CTLR_SYNC_ERROR_EN_POS (2U) 87 #define NI_TOWER_APU_CTLR_SYNC_ERROR_EN_MSK (0x1UL << NI_TOWER_APU_CTLR_SYNC_ERROR_EN_POS) 88 #define NI_TOWER_APU_CTLR_SYNC_ERROR_EN NI_TOWER_APU_CTLR_SYNC_ERROR_EN_MSK 89 #define NI_TOWER_APU_CTLR_APU_REGION_4K_POS (3U) 90 #define NI_TOWER_APU_CTLR_APU_REGION_4K_MSK (0x1UL << NI_TOWER_APU_CTLR_APU_REGION_4K_POS) 91 #define NI_TOWER_APU_CTLR_APU_REGION_4K NI_TOWER_APU_CTLR_APU_REGION_4K_MSK 92 93 #endif /* __NI_TOWER_APU_REG_H__ */ 94
