1 /*
2 * Copyright (c) 2016 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file
9 * @brief Nios II specific kernel interface header
10 * This header contains the Nios II specific kernel interface. It is
11 * included by the generic kernel interface header (include/arch/cpu.h)
12 */
13
14 #ifndef ZEPHYR_INCLUDE_ARCH_NIOS2_ARCH_H_
15 #define ZEPHYR_INCLUDE_ARCH_NIOS2_ARCH_H_
16
17 #include <system.h>
18
19 #include <arch/nios2/thread.h>
20 #include <arch/nios2/asm_inline.h>
21 #include <arch/common/addr_types.h>
22 #include <devicetree.h>
23 #include <arch/nios2/nios2.h>
24 #include <arch/common/sys_bitops.h>
25 #include <sys/sys_io.h>
26 #include <arch/common/ffs.h>
27
28 #define ARCH_STACK_PTR_ALIGN 4
29
30 #ifndef _ASMLANGUAGE
31 #include <zephyr/types.h>
32 #include <irq.h>
33 #include <sw_isr_table.h>
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* There is no notion of priority with the Nios II internal interrupt
40 * controller and no flags are currently supported.
41 */
42 #define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
43 { \
44 Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
45 }
46
47 extern void z_irq_spurious(const void *unused);
48
arch_irq_lock(void)49 static ALWAYS_INLINE unsigned int arch_irq_lock(void)
50 {
51 unsigned int key, tmp;
52
53 __asm__ volatile (
54 "rdctl %[key], status\n\t"
55 "movi %[tmp], -2\n\t"
56 "and %[tmp], %[key], %[tmp]\n\t"
57 "wrctl status, %[tmp]\n\t"
58 : [key] "=r" (key), [tmp] "=r" (tmp)
59 : : "memory");
60
61 return key;
62 }
63
arch_irq_unlock(unsigned int key)64 static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
65 {
66 /* If the CPU is built without certain features, then
67 * the only writable bit in the status register is PIE
68 * in which case we can just write the value stored in key,
69 * all the other writable bits will be the same.
70 *
71 * If not, other stuff could have changed and we need to
72 * specifically flip just that bit.
73 */
74
75 #if (ALT_CPU_NUM_OF_SHADOW_REG_SETS > 0) || \
76 (defined ALT_CPU_EIC_PRESENT) || \
77 (defined ALT_CPU_MMU_PRESENT) || \
78 (defined ALT_CPU_MPU_PRESENT)
79 __asm__ volatile (
80 "andi %[key], %[key], 1\n\t"
81 "beq %[key], zero, 1f\n\t"
82 "rdctl %[key], status\n\t"
83 "ori %[key], %[key], 1\n\t"
84 "wrctl status, %[key]\n\t"
85 "1:\n\t"
86 : [key] "+r" (key)
87 : : "memory");
88 #else
89 __asm__ volatile (
90 "wrctl status, %[key]"
91 : : [key] "r" (key)
92 : "memory");
93 #endif
94 }
95
arch_irq_unlocked(unsigned int key)96 static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
97 {
98 return key & 1;
99 }
100
101 void arch_irq_enable(unsigned int irq);
102 void arch_irq_disable(unsigned int irq);
103
104 struct __esf {
105 uint32_t ra; /* return address r31 */
106 uint32_t r1; /* at */
107 uint32_t r2; /* return value */
108 uint32_t r3; /* return value */
109 uint32_t r4; /* register args */
110 uint32_t r5; /* register args */
111 uint32_t r6; /* register args */
112 uint32_t r7; /* register args */
113 uint32_t r8; /* Caller-saved general purpose */
114 uint32_t r9; /* Caller-saved general purpose */
115 uint32_t r10; /* Caller-saved general purpose */
116 uint32_t r11; /* Caller-saved general purpose */
117 uint32_t r12; /* Caller-saved general purpose */
118 uint32_t r13; /* Caller-saved general purpose */
119 uint32_t r14; /* Caller-saved general purpose */
120 uint32_t r15; /* Caller-saved general purpose */
121 uint32_t estatus;
122 uint32_t instr; /* Instruction being executed when exc occurred */
123 };
124
125 typedef struct __esf z_arch_esf_t;
126
127 FUNC_NORETURN void z_SysFatalErrorHandler(unsigned int reason,
128 const z_arch_esf_t *esf);
129
130 FUNC_NORETURN void z_NanoFatalErrorHandler(unsigned int reason,
131 const z_arch_esf_t *esf);
132
133 enum nios2_exception_cause {
134 NIOS2_EXCEPTION_UNKNOWN = -1,
135 NIOS2_EXCEPTION_RESET = 0,
136 NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST = 1,
137 NIOS2_EXCEPTION_INTERRUPT = 2,
138 NIOS2_EXCEPTION_TRAP_INST = 3,
139 NIOS2_EXCEPTION_UNIMPLEMENTED_INST = 4,
140 NIOS2_EXCEPTION_ILLEGAL_INST = 5,
141 NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR = 6,
142 NIOS2_EXCEPTION_MISALIGNED_TARGET_PC = 7,
143 NIOS2_EXCEPTION_DIVISION_ERROR = 8,
144 NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR = 9,
145 NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST = 10,
146 NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR = 11,
147 NIOS2_EXCEPTION_TLB_MISS = 12,
148 NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION = 13,
149 NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION = 14,
150 NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION = 15,
151 NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION = 16,
152 NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION = 17,
153 NIOS2_EXCEPTION_ECC_TLB_ERR = 18,
154 NIOS2_EXCEPTION_ECC_FETCH_ERR = 19,
155 NIOS2_EXCEPTION_ECC_REGISTER_FILE_ERR = 20,
156 NIOS2_EXCEPTION_ECC_DATA_ERR = 21,
157 NIOS2_EXCEPTION_ECC_DATA_CACHE_WRITEBACK_ERR = 22
158 };
159
160 /* Bitfield indicating which exception cause codes report a valid
161 * badaddr register. NIOS2_EXCEPTION_TLB_MISS and NIOS2_EXCEPTION_ECC_TLB_ERR
162 * are deliberately not included here, you need to check if TLBMISC.D=1
163 */
164 #define NIOS2_BADADDR_CAUSE_MASK \
165 (BIT(NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR) | \
166 BIT(NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR) | \
167 BIT(NIOS2_EXCEPTION_MISALIGNED_TARGET_PC) | \
168 BIT(NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION) | \
169 BIT(NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION) | \
170 BIT(NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION) | \
171 BIT(NIOS2_EXCEPTION_ECC_DATA_ERR))
172
173
174 extern uint32_t sys_clock_cycle_get_32(void);
175
arch_k_cycle_get_32(void)176 static inline uint32_t arch_k_cycle_get_32(void)
177 {
178 return sys_clock_cycle_get_32();
179 }
180
arch_nop(void)181 static ALWAYS_INLINE void arch_nop(void)
182 {
183 __asm__ volatile("nop");
184 }
185
186 #ifdef __cplusplus
187 }
188 #endif
189
190 #endif /* _ASMLANGUAGE */
191
192 #endif /* ZEPHYR_INCLUDE_ARCH_NIOS2_ARCH_H_ */
193
