1 /*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include "fsl_netc_phy_wrapper.h"
8
NETC_PHYWriteRegBits(netc_mdio_handle_t * handle,bool pcs,volatile uint16_t * reg,uint16_t mask,uint16_t val)9 static void NETC_PHYWriteRegBits(
10 netc_mdio_handle_t *handle, bool pcs, volatile uint16_t *reg, uint16_t mask, uint16_t val)
11 {
12 uint8_t portAddr = pcs ? 0x0U : 0x10U;
13 uint8_t devAddr = getPhyDev(reg);
14 uint16_t regAddr = getPhyReg(reg);
15 uint16_t regValue;
16 status_t status;
17
18 status = NETC_MDIOC45Read(handle, portAddr, devAddr, regAddr, ®Value);
19 assert(status == kStatus_Success);
20
21 regValue &= ~mask;
22 if (val != 0U)
23 {
24 regValue |= val;
25 }
26
27 status = NETC_MDIOC45Write(handle, portAddr, devAddr, regAddr, regValue);
28 if (status != kStatus_Success)
29 {
30 assert(false);
31 }
32 }
33
NETC_PHYReadReg(netc_mdio_handle_t * handle,bool pcs,const volatile uint16_t * reg,uint16_t * val)34 static void NETC_PHYReadReg(netc_mdio_handle_t *handle, bool pcs, const volatile uint16_t *reg, uint16_t *val)
35 {
36 uint8_t portAddr = pcs ? 0x0U : 0x10U;
37 uint8_t devAddr = getPhyDev(reg);
38 uint16_t regAddr = getPhyReg(reg);
39 status_t status;
40
41 status = NETC_MDIOC45Read(handle, portAddr, devAddr, regAddr, val);
42 if (status != kStatus_Success)
43 {
44 assert(false);
45 }
46 }
47
NETC_PHYInit(netc_mdio_handle_t * handle,phy_mode_t mode)48 status_t NETC_PHYInit(netc_mdio_handle_t *handle, phy_mode_t mode)
49 {
50 uint16_t regValue;
51
52 #if !(defined(FSL_FEATURE_NETC_HAS_NO_XGMII) && FSL_FEATURE_NETC_HAS_NO_XGMII)
53 if ((mode == kNETC_XGMII10G) || (mode == kNETC_XGMII10GAuto))
54 {
55 NETC_PHYWriteRegBits(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_PHY,
56 ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK_MASK,
57 ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK(0x1U));
58 NETC_PHYWriteRegBits(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_MPLLA,
59 ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK_MASK,
60 ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK(0x1U));
61 NETC_PHYWriteRegBits(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_MPLLB,
62 ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK_MASK,
63 ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK(0x1U));
64 NETC_PHYWriteRegBits(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_RAM,
65 ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK_MASK,
66 ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK(0x1U));
67 NETC_PHYWriteRegBits(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_ROM,
68 ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK_MASK,
69 ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK(0x1U));
70 do
71 {
72 NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_SRAM, ®Value);
73 regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_INIT_DN_MASK;
74 } while (regValue == 0x0U);
75 NETC_PHYWriteRegBits(handle, false, &ENET_PHY_CTRL_EX->GLOBAL_CTRL_EX_0,
76 ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS_MASK,
77 ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS(0x1U));
78 do
79 {
80 NETC_PHYReadReg(handle, true, &ENET_PHY_XS_PCS_MMD->SR_XS_PCS_CTRL1, ®Value);
81 regValue &= ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_RST_MASK;
82 } while (regValue != 0x0U);
83 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL,
84 ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE_MASK,
85 ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE(0x0U));
86 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0,
87 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_MASK,
88 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0(0x1U));
89 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1,
90 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK,
91 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(0x1U));
92 SDK_DelayAtLeastUs(1, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
93 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0,
94 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_MASK,
95 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0(0x0U));
96 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1,
97 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK,
98 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(0x0U));
99 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_TX_POWER_STATE_CTRL,
100 ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_MASK,
101 ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE(0x3U));
102 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL,
103 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_MASK,
104 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0(0x0U));
105 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0,
106 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0_MASK,
107 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0(0x0U));
108 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0,
109 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_MASK,
110 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0(0x0U));
111 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL,
112 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK,
113 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(0x1U));
114 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL,
115 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK,
116 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(0x3U));
117 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2,
118 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK,
119 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0(0x1U));
120 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2,
121 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK,
122 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(0x1U));
123 do
124 {
125 NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, ®Value);
126 regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK;
127 } while (regValue != 0x0U);
128 do
129 {
130 NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, ®Value);
131 regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK;
132 } while (regValue != 0x0U);
133 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL,
134 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RANGE_MASK,
135 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RANGE(0x6U));
136 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL,
137 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_DIV2_MASK,
138 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_DIV2(0x0U));
139 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL,
140 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV2_MASK,
141 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV2(0x1U));
142 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2,
143 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN_MASK,
144 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN(0x0U));
145 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2,
146 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN_MASK,
147 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN(0x1U));
148 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2,
149 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN_MASK,
150 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN(0x1U));
151 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2,
152 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_MASK,
153 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_TX_CLK_DIV(0x0U));
154 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2,
155 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_CLK_EN_MASK,
156 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_CLK_EN(0x1U));
157 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2,
158 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_MULT_MASK,
159 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_MULT(0x5U));
160 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL1,
161 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_EN_MASK,
162 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_EN(0x0U));
163 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL1,
164 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL_MASK,
165 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL(0x0U));
166 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL5,
167 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_MASK,
168 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK(0x0U));
169 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL4,
170 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT_MASK,
171 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT(0x0U));
172 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL5,
173 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_SPD_EN_MASK,
174 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_SPD_EN(0x0U));
175 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL1,
176 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_FRACN_CTRL_MASK,
177 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_FRACN_CTRL(0x0U));
178 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0,
179 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK,
180 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER(0x21U));
181 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1,
182 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_LVL_MASK,
183 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_LVL(0x5U));
184 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL3,
185 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH_MASK,
186 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH(0xA016U));
187 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0,
188 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX_VREF_CTRL_MASK,
189 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX_VREF_CTRL(0x11U));
190 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_MISC_CTRL2,
191 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_SUP_MISC_MASK,
192 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_SUP_MISC(0x1U));
193 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0,
194 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0_MASK,
195 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0(0x29U));
196 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0,
197 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0_MASK,
198 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0(0x549U));
199 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0,
200 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0_RX0_CDR_PPM_MAX_MASK,
201 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0_RX0_CDR_PPM_MAX(0x12U));
202 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0,
203 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0_TX0_MISC_MASK,
204 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0_TX0_MISC(0x0U));
205 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL,
206 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE_MASK,
207 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE(0x0U));
208 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL,
209 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLLB_SEL_0_MASK,
210 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLLB_SEL_0(0x0U));
211 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2,
212 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH_MASK,
213 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH(0x3U));
214 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1,
215 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0_MASK,
216 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0(0x1U));
217 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL,
218 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL_TX0_IBOOST_MASK,
219 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL_TX0_IBOOST(0xFU));
220 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0,
221 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_PRE_MASK,
222 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_PRE(0x0U));
223 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1,
224 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1_TX_EQ_POST_MASK,
225 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1_TX_EQ_POST(0x20U));
226 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0,
227 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_MAIN_MASK,
228 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_MAIN(0x20U));
229 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL,
230 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE_MASK,
231 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE(0x0U));
232 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0,
233 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_POLE_0_MASK,
234 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_POLE_0(0x2U));
235 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0,
236 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0_MASK,
237 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0(0x10U));
238 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL3,
239 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_TRSHLD_0_MASK,
240 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_TRSHLD_0(0x7U));
241 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1,
242 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0_MASK,
243 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0(0x1U));
244 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1,
245 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0_MASK,
246 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0(0x1U));
247 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0,
248 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC_MASK,
249 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC(0x12U));
250 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2,
251 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH_MASK,
252 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH(0x3U));
253 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1,
254 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0_MASK,
255 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0(0x1U));
256 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL,
257 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL_CDR_SSC_EN_0_MASK,
258 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL_CDR_SSC_EN_0(0x0U));
259 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL3,
260 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_LFPS_EN_0_MASK,
261 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_LFPS_EN_0(0x0U));
262 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_GENCTRL4,
263 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0_MASK,
264 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0(0x0U));
265 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL,
266 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL_RX0_EQ_ATT_LVL_MASK,
267 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL_RX0_EQ_ATT_LVL(0x0U));
268 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0,
269 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA1_GAIN_0_MASK,
270 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA1_GAIN_0(0x5U));
271 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0,
272 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA2_GAIN_0_MASK,
273 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA2_GAIN_0(0x5U));
274 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0,
275 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0_DFE_TAP1_0_MASK,
276 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0_DFE_TAP1_0(0x0U));
277 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1,
278 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK,
279 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0(0x1U));
280 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1,
281 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_TERM_ACDC_0_MASK,
282 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_TERM_ACDC_0(0x1U));
283 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0,
284 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK,
285 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ(0x0U));
286 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5,
287 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_SEL_0_MASK,
288 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_SEL_0(0x0U));
289 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5,
290 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK,
291 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE(0x3U));
292 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->SR_XS_PCS_CTRL2,
293 ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL_MASK,
294 ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL(0x0U));
295 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1,
296 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USXG_EN_MASK,
297 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USXG_EN(0x1U));
298 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_KR_CTRL,
299 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_MODE_MASK,
300 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_MODE(0x0U));
301 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->SR_XS_PCS_CTRL2,
302 ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL_MASK,
303 ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL(0x0U));
304 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0,
305 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK,
306 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER(0x21U));
307 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL3,
308 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH_MASK,
309 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH(0xA016U));
310 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0,
311 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0_MASK,
312 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0(0x549U));
313 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0,
314 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0_MASK,
315 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0(0x29U));
316 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4,
317 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_ADAPT_0_MASK,
318 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_ADAPT_0(0x1U));
319 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL,
320 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE_MASK,
321 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE(0x0U));
322 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL,
323 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE_MASK,
324 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE(0x0U));
325 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2,
326 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH_MASK,
327 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH(0x3U));
328 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2,
329 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH_MASK,
330 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH(0x3U));
331 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2,
332 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN_MASK,
333 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN(0x1U));
334 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2,
335 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN_MASK,
336 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN(0x1U));
337 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2,
338 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN_MASK,
339 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN(0x0U));
340 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1,
341 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0_MASK,
342 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0(0x1U));
343 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0,
344 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0_MASK,
345 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0(0x10U));
346 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1,
347 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0_MASK,
348 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0(0x1U));
349 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1,
350 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0_MASK,
351 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0(0x1U));
352 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0,
353 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC_MASK,
354 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC(0x12U));
355 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_GENCTRL4,
356 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0_MASK,
357 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0(0x0U));
358 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1,
359 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK,
360 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0(0x1U));
361 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0,
362 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK,
363 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ(0x0U));
364 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5,
365 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK,
366 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE(0x3U));
367 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1,
368 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0_MASK,
369 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0(0x0U));
370 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1,
371 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST_MASK,
372 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST(0x1U));
373 do
374 {
375 NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_SRAM, ®Value);
376 regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_INIT_DN_MASK;
377 } while (regValue == 0x0U);
378 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_SRAM,
379 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_EXT_LD_DN_MASK,
380 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_EXT_LD_DN(0x1U));
381 do
382 {
383 NETC_PHYReadReg(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1, ®Value);
384 regValue &= ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST_MASK;
385 } while (regValue != 0x0U);
386 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1,
387 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK,
388 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(0x0U));
389 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL,
390 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0_MASK,
391 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0(0x0U));
392 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL,
393 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK,
394 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(0x0U));
395 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0,
396 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_MASK,
397 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0(0x1U));
398 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2,
399 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK,
400 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(0x1U));
401 do
402 {
403 NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, ®Value);
404 regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK;
405 } while (regValue != 0x0U);
406 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1,
407 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0_MASK,
408 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0(0x1U));
409 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DEBUG_CTRL,
410 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_LOS_DET_MASK,
411 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_LOS_DET(0x1U));
412 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DEBUG_CTRL,
413 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_DT_EN_CTL_MASK,
414 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_DT_EN_CTL(0x1U));
415 do
416 {
417 NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_RX_LSTS, ®Value);
418 regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_0_MASK;
419 } while (regValue == 0x0U);
420 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4,
421 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ_MASK,
422 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ(0x1U));
423 do
424 {
425 NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MISC_STS, ®Value);
426 regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RX_ADPT_ACK_MASK;
427 } while (regValue == 0x0U);
428 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4,
429 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ_MASK,
430 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ(0x0U));
431
432 if (mode == kNETC_XGMII10GAuto)
433 {
434 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_CTRL,
435 ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_AN_INTR_EN_MASK,
436 ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_AN_INTR_EN(0x1U));
437 }
438
439 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_CTRL,
440 ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_TX_CONFIG_MASK,
441 ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_TX_CONFIG(0x0U));
442
443 if (mode == kNETC_XGMII10GAuto)
444 {
445 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_LINK_TIMER_CTRL,
446 ENET_PHY_VS_MII_MMD_VR_MII_LINK_TIMER_CTRL_CL37_LINK_TIME_MASK,
447 ENET_PHY_VS_MII_MMD_VR_MII_LINK_TIMER_CTRL_CL37_LINK_TIME(0x1U));
448 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_DIG_CTRL1,
449 ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_MASK,
450 ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE(0x1U));
451 }
452
453 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS6_MASK,
454 ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS6(0x1U));
455 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS13_MASK,
456 ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS13(0x1U));
457 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS5_MASK,
458 ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS5(0x0U));
459
460 NETC_PHYWriteRegBits(handle, true, &ENET_PHY->LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0,
461 ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE_MASK,
462 ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE(0x169U));
463 NETC_PHYWriteRegBits(handle, true, &ENET_PHY->LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0,
464 ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_CDR_FREQ_TUNE_OVRD_EN_MASK,
465 ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_CDR_FREQ_TUNE_OVRD_EN(0x1U));
466 NETC_PHYWriteRegBits(handle, true, &ENET_PHY->LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2,
467 ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2_RX_ANA_CDR_FREQ_TUNE_CLK_MASK,
468 ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2_RX_ANA_CDR_FREQ_TUNE_CLK(0x1U));
469
470 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DEBUG_CTRL,
471 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_TX_PMBL_CTL_MASK,
472 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_TX_PMBL_CTL(0x1U));
473 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_TX_POWER_STATE_CTRL,
474 ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_MASK,
475 ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE(0x2U));
476 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL,
477 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_MASK,
478 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0(0x1U));
479 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2,
480 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK,
481 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0(0x1U));
482 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2,
483 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK,
484 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(0x1U));
485 do
486 {
487 NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, ®Value);
488 regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK;
489 } while (regValue != 0x0U);
490 do
491 {
492 NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, ®Value);
493 regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK;
494 } while (regValue != 0x0U);
495 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_TX_POWER_STATE_CTRL,
496 ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_MASK,
497 ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE(0x0U));
498 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0,
499 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_MASK,
500 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0(0x0U));
501 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_TX_POWER_STATE_CTRL,
502 ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX_DISABLE_0_MASK,
503 ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX_DISABLE_0(0x0U));
504 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL,
505 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_MASK,
506 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0(0x1U));
507 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1,
508 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK,
509 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(0x0U));
510 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL,
511 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0_MASK,
512 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0(0x0U));
513 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL,
514 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK,
515 ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(0x0U));
516 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0,
517 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0_MASK,
518 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0(0x1U));
519 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0,
520 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_MASK,
521 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0(0x1U));
522 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2,
523 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK,
524 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0(0x1U));
525 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2,
526 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK,
527 ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(0x1U));
528 do
529 {
530 NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, ®Value);
531 regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK;
532 } while (regValue != 0x0U);
533 do
534 {
535 NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, ®Value);
536 regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK;
537 } while (regValue != 0x0U);
538
539 if (mode == kNETC_XGMII10GAuto)
540 {
541 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL,
542 ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE_MASK,
543 ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE(0x1U));
544 do
545 {
546 NETC_PHYReadReg(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_INTR_STS, ®Value);
547 regValue &= ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_MASK;
548 } while (regValue == 0x0U);
549 do
550 {
551 NETC_PHYReadReg(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_INTR_STS, ®Value);
552 regValue &= ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_USXG_AN_STS_MASK;
553 } while (regValue != ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_USXG_AN_STS(0x2FU));
554
555 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_INTR_STS,
556 ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_MASK,
557 ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR(0x0U));
558
559 NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1,
560 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST_MASK,
561 ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST(0x1U));
562 do
563 {
564 NETC_PHYReadReg(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1, ®Value);
565 regValue &= ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST_MASK;
566 } while (regValue != 0U);
567 }
568 }
569 else
570 {
571 return kStatus_NETC_Unsupported;
572 }
573
574 #endif
575 return kStatus_Success;
576 }
577
