1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_NETC_F3_SI0.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_NETC_F3_SI0 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_NETC_F3_SI0_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_NETC_F3_SI0_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- NETC_F3_SI0 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup NETC_F3_SI0_Peripheral_Access_Layer NETC_F3_SI0 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** NETC_F3_SI0 - Size of Registers Arrays */ 72 #define NETC_F3_SI0_MSGSR_PSI_A_VSI_NUM_COUNT 7u 73 #define NETC_F3_SI0_TX_MSI_COUNT 18u 74 #define NETC_F3_SI0_RX_GRP_COUNT 18u 75 #define NETC_F3_SI0_BDR_NUM_COUNT 18u 76 77 /** NETC_F3_SI0 - Register Layout Typedef */ 78 typedef struct { 79 __IO uint32_t SIMR; /**< Station interface mode register, offset: 0x0 */ 80 __I uint32_t SISR; /**< Station interface status register, offset: 0x4 */ 81 uint8_t RESERVED_0[16]; 82 __I uint32_t SICTR0; /**< Station interface current time register 0, offset: 0x18 */ 83 __I uint32_t SICTR1; /**< Station interface current time register 1, offset: 0x1C */ 84 __I uint32_t SIPCAPR0; /**< Station interface port capability register 0, offset: 0x20 */ 85 __I uint32_t SIPCAPR1; /**< Station interface port capability register 1, offset: 0x24 */ 86 uint8_t RESERVED_1[8]; 87 __I uint32_t SITSR; /**< Station interface timer status register, offset: 0x30 */ 88 uint8_t RESERVED_2[4]; 89 __IO uint32_t SIRBGCR; /**< Station interface receive BDR group control register, offset: 0x38 */ 90 uint8_t RESERVED_3[4]; 91 __IO uint32_t SIBCAR; /**< Station interface buffer cache attribute register, offset: 0x40 */ 92 __IO uint32_t SIMCAR; /**< Station interface message cache attribute register, offset: 0x44 */ 93 __IO uint32_t SICCAR; /**< Station interface command cache attribute register, offset: 0x48 */ 94 uint8_t RESERVED_4[52]; 95 __I uint32_t SIPMAR0; /**< Station interface primary MAC address register 0, offset: 0x80 */ 96 __I uint32_t SIPMAR1; /**< Station interface primary MAC address register 1, offset: 0x84 */ 97 uint8_t RESERVED_5[8]; 98 __I uint32_t SICVLANR1; /**< Station interface custom VLAN register 1, offset: 0x90 */ 99 __I uint32_t SICVLANR2; /**< Station interface custom VLAN register 2, offset: 0x94 */ 100 uint8_t RESERVED_6[104]; 101 __IO uint32_t SIVLANIPVMR0; /**< Station interface VLAN to IPV mapping register 0, offset: 0x100 */ 102 __IO uint32_t SIVLANIPVMR1; /**< Station interface VLAN to IPV mapping register 1, offset: 0x104 */ 103 uint8_t RESERVED_7[72]; 104 __IO uint32_t SIIPVBDRMR0; /**< Station interface IPV to ring mapping register, offset: 0x150 */ 105 uint8_t RESERVED_8[176]; 106 union { /* offset: 0x204 */ 107 struct { /* offset: 0x204 */ 108 __IO uint32_t PSIMSGRR; /**< Physical station interface message receive register, offset: 0x204 */ 109 __IO uint32_t PSIMSGSR; /**< Physical station interface message send register, offset: 0x208 */ 110 uint8_t RESERVED_0[4]; 111 struct { /* offset: 0x210, array step: 0x8 */ 112 __IO uint32_t PSIVMSGRCVAR0; /**< PSI VSI 1 message receive address register 0..PSI VSI 7 message receive address register 0, array offset: 0x210, array step: 0x8 */ 113 __IO uint32_t PSIVMSGRCVAR1; /**< PSI VSI 1 message receive address register 1..PSI VSI 7 message receive address register 1, array offset: 0x214, array step: 0x8 */ 114 } VSI_NUM[NETC_F3_SI0_MSGSR_PSI_A_VSI_NUM_COUNT]; 115 } PSI_A; 116 } MSGSR; 117 uint8_t RESERVED_9[184]; 118 __I uint32_t SIROCT0; /**< Station interface receive octets counter (ifInOctets) 0, offset: 0x300 */ 119 __I uint32_t SIROCT1; /**< Station interface receive octets counter (ifInOctets) 1, offset: 0x304 */ 120 __I uint32_t SIRFRM0; /**< Station interface receive frame counter (aFrameReceivedOK) 0, offset: 0x308 */ 121 __I uint32_t SIRFRM1; /**< Station interface receive frame counter (aFrameReceivedOK) 1, offset: 0x30C */ 122 __I uint32_t SIRUCA0; /**< Station interface receive unicast frame counter (ifInUcastPkts) 0, offset: 0x310 */ 123 __I uint32_t SIRUCA1; /**< Station interface receive unicast frame counter (ifInUcastPkts) 1, offset: 0x314 */ 124 __I uint32_t SIRMCA0; /**< Station interface receive multicast frame counter (ifInMulticastPkts) 0, offset: 0x318 */ 125 __I uint32_t SIRMCA1; /**< Station interface receive multicast frame counter (ifInMulticastPkts) 1, offset: 0x31C */ 126 __I uint32_t SITOCT0; /**< Station interface transmit octets counter (ifOutOctets) 0, offset: 0x320 */ 127 __I uint32_t SITOCT1; /**< Station interface transmit octets counter (ifOutOctets) 1, offset: 0x324 */ 128 __I uint32_t SITFRM0; /**< Station interface transmit frame counter (aFrameTransmittedOK) 0, offset: 0x328 */ 129 __I uint32_t SITFRM1; /**< Station interface transmit frame counter (aFrameTransmittedOK) 1, offset: 0x32C */ 130 __I uint32_t SITUCA0; /**< Station interface transmit unicast frame counter (ifOutUcastPkts) 0, offset: 0x330 */ 131 __I uint32_t SITUCA1; /**< Station interface transmit unicast frame counter (ifOutUcastPkts) 1, offset: 0x334 */ 132 __I uint32_t SITMCA0; /**< Station interface transmit multicast frame counter (ifOutMulticastPkts) 0, offset: 0x338 */ 133 __I uint32_t SITMCA1; /**< Station interface transmit multicast frame counter (ifOutMulticastPkts) 1, offset: 0x33C */ 134 uint8_t RESERVED_10[1216]; 135 __IO uint32_t SICBDRMR; /**< Station interface command BDR mode register, offset: 0x800 */ 136 __I uint32_t SICBDRSR; /**< Station interface command BDR status register, offset: 0x804 */ 137 uint8_t RESERVED_11[8]; 138 __IO uint32_t SICBDRBAR0; /**< Station interface command BDR base address register 0, offset: 0x810 */ 139 __IO uint32_t SICBDRBAR1; /**< Station interface command BDR base address register 1, offset: 0x814 */ 140 __IO uint32_t SICBDRPIR; /**< Station interface command BDR producer index register, offset: 0x818 */ 141 __IO uint32_t SICBDRCIR; /**< Station interface command BDR consumer index register, offset: 0x81C */ 142 __IO uint32_t SICBDRLENR; /**< Station interface command BDR length register, offset: 0x820 */ 143 uint8_t RESERVED_12[124]; 144 __IO uint32_t SICBDRIER; /**< Station interface command BDR interrupt enable register, offset: 0x8A0 */ 145 __IO uint32_t SICBDRIDR; /**< Station interface command BDR interrupt detect register, offset: 0x8A4 */ 146 uint8_t RESERVED_13[88]; 147 __I uint32_t SICAPR0; /**< Station interface capability register 0, offset: 0x900 */ 148 __I uint32_t SICAPR1; /**< Station interface capability register 1, offset: 0x904 */ 149 __I uint32_t SICAPR2; /**< Station interface capability register 2, offset: 0x908 */ 150 uint8_t RESERVED_14[244]; 151 union { /* offset: 0xA00 */ 152 struct { /* offset: 0xA00 */ 153 __IO uint32_t PSIIER; /**< Physical station interface interrupt enable register, offset: 0xA00 */ 154 uint8_t RESERVED_0[4]; 155 __IO uint32_t PSIIDR; /**< Physical station interface interrupt detect register, offset: 0xA08 */ 156 } PSI; 157 } INTERRUPT; 158 uint8_t RESERVED_15[12]; 159 __IO uint32_t SITXIDR0; /**< Station interface transmit interrupt detect register 0, offset: 0xA18 */ 160 __IO uint32_t SITXIDR1; /**< Station interface transmit interrupt detect register 1, offset: 0xA1C */ 161 uint8_t RESERVED_16[8]; 162 __IO uint32_t SIRXIDR0; /**< Station interface receive interrupt detect register 0, offset: 0xA28 */ 163 __IO uint32_t SIRXIDR1; /**< Station interface receive interrupt detect register 1, offset: 0xA2C */ 164 __IO uint32_t SIMSIVR; /**< Station interface MSI-X vector register, offset: 0xA30 */ 165 __IO uint32_t SICMSIVR; /**< Station interface command MSI-X vector register, offset: 0xA34 */ 166 uint8_t RESERVED_17[8]; 167 __IO uint32_t SITMRIER; /**< Station interface timer interrupt enable register, offset: 0xA40 */ 168 __IO uint32_t SITMRIDR; /**< Station interface timer interrupt detect register, offset: 0xA44 */ 169 uint8_t RESERVED_18[4]; 170 __IO uint32_t SITMRMSIVR; /**< Station interface timer MSI-X vector register, offset: 0xA4C */ 171 uint8_t RESERVED_19[176]; 172 __IO uint32_t SIMSITRVR[NETC_F3_SI0_TX_MSI_COUNT]; /**< Station interface MSI-X transmit ring 0 vector register..Station interface MSI-X transmit ring 17 vector register, array offset: 0xB00, array step: 0x4 */ 173 uint8_t RESERVED_20[56]; 174 __IO uint32_t SIMSIRRVR[NETC_F3_SI0_RX_GRP_COUNT]; /**< Station interface MSI-X receive ring 0 vector register..Station interface MSI-X receive ring 17 vector register, array offset: 0xB80, array step: 0x4 */ 175 uint8_t RESERVED_21[568]; 176 __IO uint32_t SICMECR; /**< Station interface correctable memory error configuration register, offset: 0xE00 */ 177 __IO uint32_t SICMESR; /**< Station interface correctable memory error status register, offset: 0xE04 */ 178 uint8_t RESERVED_22[4]; 179 __I uint32_t SICMECTR; /**< Station interface correctable memory error count register, offset: 0xE0C */ 180 __IO uint32_t SIUPECR; /**< Station interface uncorrectable programming error configuration register, offset: 0xE10 */ 181 __IO uint32_t SIUPESR; /**< Station interface uncorrectable programming error status register, offset: 0xE14 */ 182 uint8_t RESERVED_23[4]; 183 __I uint32_t SIUPECTR; /**< Station interface uncorrectable programming error count register, offset: 0xE1C */ 184 __IO uint32_t SIUNSBECR; /**< Station interface uncorrectable non-fatal system bus error configuration register, offset: 0xE20 */ 185 __IO uint32_t SIUNSBESR; /**< Station interface uncorrectable non-fatal system bus error status register, offset: 0xE24 */ 186 uint8_t RESERVED_24[4]; 187 __I uint32_t SIUNSBECTR; /**< Station interface uncorrectable non-fatal system bus error count register, offset: 0xE2C */ 188 __IO uint32_t SIUFSBECR; /**< Station interface uncorrectable fatal system bus error configuration register, offset: 0xE30 */ 189 __IO uint32_t SIUFSBESR; /**< Station interface uncorrectable fatal system bus error status register, offset: 0xE34 */ 190 uint8_t RESERVED_25[8]; 191 __IO uint32_t SIUNMECR; /**< Station interface uncorrectable non-fatal memory error configuration register, offset: 0xE40 */ 192 __IO uint32_t SIUNMESR0; /**< Station interface uncorrectable non-fatal memory error status register 0, offset: 0xE44 */ 193 __I uint32_t SIUNMESR1; /**< Station interface uncorrectable non-fatal memory error status register 1, offset: 0xE48 */ 194 __I uint32_t SIUNMECTR; /**< Station interface uncorrectable non-fatal memory error count register, offset: 0xE4C */ 195 __IO uint32_t SIUFMECR; /**< Station interface uncorrectable fatal memory error configuration register, offset: 0xE50 */ 196 __IO uint32_t SIUFMESR0; /**< Station interface uncorrectable fatal memory error status register 0, offset: 0xE54 */ 197 __I uint32_t SIUFMESR1; /**< Station interface uncorrectable fatal memory error status register 1, offset: 0xE58 */ 198 uint8_t RESERVED_26[4]; 199 __IO uint32_t SIUNIECR; /**< Station interface uncorrectable non-fatal integrity error configuration register, offset: 0xE60 */ 200 __IO uint32_t SIUNIESR; /**< Station interface uncorrectable non-fatal integrity error status register, offset: 0xE64 */ 201 uint8_t RESERVED_27[4]; 202 __I uint32_t SIUNIECTR; /**< Station interface uncorrectable non-fatal integrity error count register, offset: 0xE6C */ 203 __IO uint32_t SIUFIECR; /**< Station interface uncorrectable fatal integrity error configuration register, offset: 0xE70 */ 204 __IO uint32_t SIUFIESR; /**< Station interface uncorrectable fatal integrity error status register, offset: 0xE74 */ 205 uint8_t RESERVED_28[392]; 206 __I uint32_t SIMAFTCAPR; /**< Station interface MAC address filter table capability register, offset: 0x1000 */ 207 uint8_t RESERVED_29[252]; 208 __I uint32_t SIVFTCAPR; /**< Station interface VLAN filter table capability register, offset: 0x1100 */ 209 uint8_t RESERVED_30[252]; 210 __I uint32_t SIRFSCAPR; /**< Station interface RFS capability register, offset: 0x1200 */ 211 uint8_t RESERVED_31[28156]; 212 struct { /* offset: 0x8000, array step: 0x200 */ 213 __IO uint32_t TBMR; /**< Tx BDR 0 mode register..Tx BDR 17 mode register, array offset: 0x8000, array step: 0x200 */ 214 __IO uint32_t TBSR; /**< Tx BDR 0 status register..Tx BDR 17 status register, array offset: 0x8004, array step: 0x200 */ 215 uint8_t RESERVED_0[8]; 216 __IO uint32_t TBBAR0; /**< Tx BDR 0 base address register 0..Tx BDR 17 base address register 0, array offset: 0x8010, array step: 0x200 */ 217 __IO uint32_t TBBAR1; /**< Tx BDR 0 base address register 1..Tx BDR 17 base address register 1, array offset: 0x8014, array step: 0x200 */ 218 __IO uint32_t TBPIR; /**< Tx BDR 0 producer index register..Tx BDR 17 producer index register, array offset: 0x8018, array step: 0x200 */ 219 __IO uint32_t TBCIR; /**< Tx BDR 0 consumer index register..Tx BDR 17 consumer index register, array offset: 0x801C, array step: 0x200 */ 220 __IO uint32_t TBLENR; /**< Tx BDR 0 length register..Tx BDR 17 length register, array offset: 0x8020, array step: 0x200 */ 221 uint8_t RESERVED_1[124]; 222 __IO uint32_t TBIER; /**< Tx BDR 0 interrupt enable register..Tx BDR 17 interrupt enable register, array offset: 0x80A0, array step: 0x200 */ 223 __I uint32_t TBIDR; /**< Tx BDR 0 interrupt detect register..Tx BDR 17 interrupt detect register, array offset: 0x80A4, array step: 0x200 */ 224 __IO uint32_t TBICR0; /**< Tx BDR 0 interrupt coalescing register 0..Tx BDR 17 interrupt coalescing register 0, array offset: 0x80A8, array step: 0x200 */ 225 __IO uint32_t TBICR1; /**< Tx BDR 0 interrupt coalescing register 1..Tx BDR 17 interrupt coalescing register 1, array offset: 0x80AC, array step: 0x200 */ 226 uint8_t RESERVED_2[80]; 227 __IO uint32_t RBMR; /**< Rx BDR 0 mode register..Rx BDR 17 mode register, array offset: 0x8100, array step: 0x200 */ 228 __IO uint32_t RBSR; /**< Rx BDR 0 status register..Rx BDR 17 status register, array offset: 0x8104, array step: 0x200 */ 229 __IO uint32_t RBBSR; /**< Rx BDR 0 buffer size register..Rx BDR 17 buffer size register, array offset: 0x8108, array step: 0x200 */ 230 __IO uint32_t RBCIR; /**< Rx BDR 0 consumer index register..Rx BDR 17 consumer index register, array offset: 0x810C, array step: 0x200 */ 231 __IO uint32_t RBBAR0; /**< Rx BDR 0 base address register 0..Rx BDR 17 base address register 0, array offset: 0x8110, array step: 0x200 */ 232 __IO uint32_t RBBAR1; /**< Rx BDR 0 base address register 1..Rx BDR 17 base address register 1, array offset: 0x8114, array step: 0x200 */ 233 __IO uint32_t RBPIR; /**< Rx BDR 0 producer index register..Rx BDR 17 producer index register, array offset: 0x8118, array step: 0x200 */ 234 uint8_t RESERVED_3[4]; 235 __IO uint32_t RBLENR; /**< Rx BDR 0 length register..Rx BDR 17 length register, array offset: 0x8120, array step: 0x200 */ 236 uint8_t RESERVED_4[92]; 237 __I uint32_t RBDCR; /**< Rx BDR 0 drop count register..Rx BDR 17 drop count register, array offset: 0x8180, array step: 0x200 */ 238 uint8_t RESERVED_5[28]; 239 __IO uint32_t RBIER; /**< Rx BDR 0 interrupt enable register..Rx BDR 17 interrupt enable register, array offset: 0x81A0, array step: 0x200 */ 240 __I uint32_t RBIDR; /**< Rx BDR 0 interrupt detect register..Rx BDR 17 interrupt detect register, array offset: 0x81A4, array step: 0x200 */ 241 __IO uint32_t RBICR0; /**< Rx BDR 0 interrupt coalescing register 0..Rx BDR 17 interrupt coalescing register 0, array offset: 0x81A8, array step: 0x200 */ 242 __IO uint32_t RBICR1; /**< Rx BDR 0 interrupt coalescing register 1..Rx BDR 17 interrupt coalescing register 1, array offset: 0x81AC, array step: 0x200 */ 243 uint8_t RESERVED_6[80]; 244 } BDR_NUM[NETC_F3_SI0_BDR_NUM_COUNT]; 245 } NETC_F3_SI0_Type, *NETC_F3_SI0_MemMapPtr; 246 247 /** Number of instances of the NETC_F3_SI0 module. */ 248 #define NETC_F3_SI0_INSTANCE_COUNT (1u) 249 250 /* NETC_F3_SI0 - Peripheral instance base addresses */ 251 /** Peripheral NETC__ENETC0_SI0 base address */ 252 #define IP_NETC__ENETC0_SI0_BASE (0x74B00000u) 253 /** Peripheral NETC__ENETC0_SI0 base pointer */ 254 #define IP_NETC__ENETC0_SI0 ((NETC_F3_SI0_Type *)IP_NETC__ENETC0_SI0_BASE) 255 /** Array initializer of NETC_F3_SI0 peripheral base addresses */ 256 #define IP_NETC_F3_SI0_BASE_ADDRS { IP_NETC__ENETC0_SI0_BASE } 257 /** Array initializer of NETC_F3_SI0 peripheral base pointers */ 258 #define IP_NETC_F3_SI0_BASE_PTRS { IP_NETC__ENETC0_SI0 } 259 260 /* ---------------------------------------------------------------------------- 261 -- NETC_F3_SI0 Register Masks 262 ---------------------------------------------------------------------------- */ 263 264 /*! 265 * @addtogroup NETC_F3_SI0_Register_Masks NETC_F3_SI0 Register Masks 266 * @{ 267 */ 268 269 /*! @name SIMR - Station interface mode register */ 270 /*! @{ */ 271 272 #define NETC_F3_SI0_SIMR_RSSE_MASK (0x1U) 273 #define NETC_F3_SI0_SIMR_RSSE_SHIFT (0U) 274 #define NETC_F3_SI0_SIMR_RSSE_WIDTH (1U) 275 #define NETC_F3_SI0_SIMR_RSSE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMR_RSSE_SHIFT)) & NETC_F3_SI0_SIMR_RSSE_MASK) 276 277 #define NETC_F3_SI0_SIMR_RNUM_MASK (0x2U) 278 #define NETC_F3_SI0_SIMR_RNUM_SHIFT (1U) 279 #define NETC_F3_SI0_SIMR_RNUM_WIDTH (1U) 280 #define NETC_F3_SI0_SIMR_RNUM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMR_RNUM_SHIFT)) & NETC_F3_SI0_SIMR_RNUM_MASK) 281 282 #define NETC_F3_SI0_SIMR_RNMM_MASK (0x4U) 283 #define NETC_F3_SI0_SIMR_RNMM_SHIFT (2U) 284 #define NETC_F3_SI0_SIMR_RNMM_WIDTH (1U) 285 #define NETC_F3_SI0_SIMR_RNMM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMR_RNMM_SHIFT)) & NETC_F3_SI0_SIMR_RNMM_MASK) 286 287 #define NETC_F3_SI0_SIMR_RNBM_MASK (0x8U) 288 #define NETC_F3_SI0_SIMR_RNBM_SHIFT (3U) 289 #define NETC_F3_SI0_SIMR_RNBM_WIDTH (1U) 290 #define NETC_F3_SI0_SIMR_RNBM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMR_RNBM_SHIFT)) & NETC_F3_SI0_SIMR_RNBM_MASK) 291 292 #define NETC_F3_SI0_SIMR_V2IPVE_MASK (0x10U) 293 #define NETC_F3_SI0_SIMR_V2IPVE_SHIFT (4U) 294 #define NETC_F3_SI0_SIMR_V2IPVE_WIDTH (1U) 295 #define NETC_F3_SI0_SIMR_V2IPVE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMR_V2IPVE_SHIFT)) & NETC_F3_SI0_SIMR_V2IPVE_MASK) 296 297 #define NETC_F3_SI0_SIMR_DEFAULT_RX_GROUP_MASK (0x10000U) 298 #define NETC_F3_SI0_SIMR_DEFAULT_RX_GROUP_SHIFT (16U) 299 #define NETC_F3_SI0_SIMR_DEFAULT_RX_GROUP_WIDTH (1U) 300 #define NETC_F3_SI0_SIMR_DEFAULT_RX_GROUP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMR_DEFAULT_RX_GROUP_SHIFT)) & NETC_F3_SI0_SIMR_DEFAULT_RX_GROUP_MASK) 301 302 #define NETC_F3_SI0_SIMR_EN_MASK (0x80000000U) 303 #define NETC_F3_SI0_SIMR_EN_SHIFT (31U) 304 #define NETC_F3_SI0_SIMR_EN_WIDTH (1U) 305 #define NETC_F3_SI0_SIMR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMR_EN_SHIFT)) & NETC_F3_SI0_SIMR_EN_MASK) 306 /*! @} */ 307 308 /*! @name SISR - Station interface status register */ 309 /*! @{ */ 310 311 #define NETC_F3_SI0_SISR_TX_BUSY_MASK (0x1U) 312 #define NETC_F3_SI0_SISR_TX_BUSY_SHIFT (0U) 313 #define NETC_F3_SI0_SISR_TX_BUSY_WIDTH (1U) 314 #define NETC_F3_SI0_SISR_TX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SISR_TX_BUSY_SHIFT)) & NETC_F3_SI0_SISR_TX_BUSY_MASK) 315 316 #define NETC_F3_SI0_SISR_MAC_UP_MASK (0x2U) 317 #define NETC_F3_SI0_SISR_MAC_UP_SHIFT (1U) 318 #define NETC_F3_SI0_SISR_MAC_UP_WIDTH (1U) 319 #define NETC_F3_SI0_SISR_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SISR_MAC_UP_SHIFT)) & NETC_F3_SI0_SISR_MAC_UP_MASK) 320 321 #define NETC_F3_SI0_SISR_MAC_MP_MASK (0x4U) 322 #define NETC_F3_SI0_SISR_MAC_MP_SHIFT (2U) 323 #define NETC_F3_SI0_SISR_MAC_MP_WIDTH (1U) 324 #define NETC_F3_SI0_SISR_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SISR_MAC_MP_SHIFT)) & NETC_F3_SI0_SISR_MAC_MP_MASK) 325 326 #define NETC_F3_SI0_SISR_VLAN_P_MASK (0x8U) 327 #define NETC_F3_SI0_SISR_VLAN_P_SHIFT (3U) 328 #define NETC_F3_SI0_SISR_VLAN_P_WIDTH (1U) 329 #define NETC_F3_SI0_SISR_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SISR_VLAN_P_SHIFT)) & NETC_F3_SI0_SISR_VLAN_P_MASK) 330 331 #define NETC_F3_SI0_SISR_VLAN_UTA_MASK (0x10U) 332 #define NETC_F3_SI0_SISR_VLAN_UTA_SHIFT (4U) 333 #define NETC_F3_SI0_SISR_VLAN_UTA_WIDTH (1U) 334 #define NETC_F3_SI0_SISR_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SISR_VLAN_UTA_SHIFT)) & NETC_F3_SI0_SISR_VLAN_UTA_MASK) 335 /*! @} */ 336 337 /*! @name SICTR0 - Station interface current time register 0 */ 338 /*! @{ */ 339 340 #define NETC_F3_SI0_SICTR0_CURR_TIME_MASK (0xFFFFFFFFU) 341 #define NETC_F3_SI0_SICTR0_CURR_TIME_SHIFT (0U) 342 #define NETC_F3_SI0_SICTR0_CURR_TIME_WIDTH (32U) 343 #define NETC_F3_SI0_SICTR0_CURR_TIME(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICTR0_CURR_TIME_SHIFT)) & NETC_F3_SI0_SICTR0_CURR_TIME_MASK) 344 /*! @} */ 345 346 /*! @name SICTR1 - Station interface current time register 1 */ 347 /*! @{ */ 348 349 #define NETC_F3_SI0_SICTR1_CURR_TIME_MASK (0xFFFFFFFFU) 350 #define NETC_F3_SI0_SICTR1_CURR_TIME_SHIFT (0U) 351 #define NETC_F3_SI0_SICTR1_CURR_TIME_WIDTH (32U) 352 #define NETC_F3_SI0_SICTR1_CURR_TIME(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICTR1_CURR_TIME_SHIFT)) & NETC_F3_SI0_SICTR1_CURR_TIME_MASK) 353 /*! @} */ 354 355 /*! @name SIPCAPR0 - Station interface port capability register 0 */ 356 /*! @{ */ 357 358 #define NETC_F3_SI0_SIPCAPR0_RFS_MASK (0x4U) 359 #define NETC_F3_SI0_SIPCAPR0_RFS_SHIFT (2U) 360 #define NETC_F3_SI0_SIPCAPR0_RFS_WIDTH (1U) 361 #define NETC_F3_SI0_SIPCAPR0_RFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR0_RFS_SHIFT)) & NETC_F3_SI0_SIPCAPR0_RFS_MASK) 362 363 #define NETC_F3_SI0_SIPCAPR0_FP_MASK (0x8U) 364 #define NETC_F3_SI0_SIPCAPR0_FP_SHIFT (3U) 365 #define NETC_F3_SI0_SIPCAPR0_FP_WIDTH (1U) 366 #define NETC_F3_SI0_SIPCAPR0_FP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR0_FP_SHIFT)) & NETC_F3_SI0_SIPCAPR0_FP_MASK) 367 368 #define NETC_F3_SI0_SIPCAPR0_TGS_MASK (0x10U) 369 #define NETC_F3_SI0_SIPCAPR0_TGS_SHIFT (4U) 370 #define NETC_F3_SI0_SIPCAPR0_TGS_WIDTH (1U) 371 #define NETC_F3_SI0_SIPCAPR0_TGS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR0_TGS_SHIFT)) & NETC_F3_SI0_SIPCAPR0_TGS_MASK) 372 373 #define NETC_F3_SI0_SIPCAPR0_TSD_MASK (0x20U) 374 #define NETC_F3_SI0_SIPCAPR0_TSD_SHIFT (5U) 375 #define NETC_F3_SI0_SIPCAPR0_TSD_WIDTH (1U) 376 #define NETC_F3_SI0_SIPCAPR0_TSD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR0_TSD_SHIFT)) & NETC_F3_SI0_SIPCAPR0_TSD_MASK) 377 378 #define NETC_F3_SI0_SIPCAPR0_CBS_MASK (0x40U) 379 #define NETC_F3_SI0_SIPCAPR0_CBS_SHIFT (6U) 380 #define NETC_F3_SI0_SIPCAPR0_CBS_WIDTH (1U) 381 #define NETC_F3_SI0_SIPCAPR0_CBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR0_CBS_SHIFT)) & NETC_F3_SI0_SIPCAPR0_CBS_MASK) 382 383 #define NETC_F3_SI0_SIPCAPR0_RSS_MASK (0x100U) 384 #define NETC_F3_SI0_SIPCAPR0_RSS_SHIFT (8U) 385 #define NETC_F3_SI0_SIPCAPR0_RSS_WIDTH (1U) 386 #define NETC_F3_SI0_SIPCAPR0_RSS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR0_RSS_SHIFT)) & NETC_F3_SI0_SIPCAPR0_RSS_MASK) 387 388 #define NETC_F3_SI0_SIPCAPR0_PSFP_MASK (0x200U) 389 #define NETC_F3_SI0_SIPCAPR0_PSFP_SHIFT (9U) 390 #define NETC_F3_SI0_SIPCAPR0_PSFP_WIDTH (1U) 391 #define NETC_F3_SI0_SIPCAPR0_PSFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR0_PSFP_SHIFT)) & NETC_F3_SI0_SIPCAPR0_PSFP_MASK) 392 393 #define NETC_F3_SI0_SIPCAPR0_IPFLT_MASK (0x400U) 394 #define NETC_F3_SI0_SIPCAPR0_IPFLT_SHIFT (10U) 395 #define NETC_F3_SI0_SIPCAPR0_IPFLT_WIDTH (1U) 396 #define NETC_F3_SI0_SIPCAPR0_IPFLT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR0_IPFLT_SHIFT)) & NETC_F3_SI0_SIPCAPR0_IPFLT_MASK) 397 398 #define NETC_F3_SI0_SIPCAPR0_RP_MASK (0x800U) 399 #define NETC_F3_SI0_SIPCAPR0_RP_SHIFT (11U) 400 #define NETC_F3_SI0_SIPCAPR0_RP_WIDTH (1U) 401 #define NETC_F3_SI0_SIPCAPR0_RP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR0_RP_SHIFT)) & NETC_F3_SI0_SIPCAPR0_RP_MASK) 402 403 #define NETC_F3_SI0_SIPCAPR0_WO_MASK (0x2000U) 404 #define NETC_F3_SI0_SIPCAPR0_WO_SHIFT (13U) 405 #define NETC_F3_SI0_SIPCAPR0_WO_WIDTH (1U) 406 #define NETC_F3_SI0_SIPCAPR0_WO(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR0_WO_SHIFT)) & NETC_F3_SI0_SIPCAPR0_WO_MASK) 407 408 #define NETC_F3_SI0_SIPCAPR0_FS_MASK (0x10000U) 409 #define NETC_F3_SI0_SIPCAPR0_FS_SHIFT (16U) 410 #define NETC_F3_SI0_SIPCAPR0_FS_WIDTH (1U) 411 #define NETC_F3_SI0_SIPCAPR0_FS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR0_FS_SHIFT)) & NETC_F3_SI0_SIPCAPR0_FS_MASK) 412 /*! @} */ 413 414 /*! @name SIPCAPR1 - Station interface port capability register 1 */ 415 /*! @{ */ 416 417 #define NETC_F3_SI0_SIPCAPR1_NUM_TCS_MASK (0x70U) 418 #define NETC_F3_SI0_SIPCAPR1_NUM_TCS_SHIFT (4U) 419 #define NETC_F3_SI0_SIPCAPR1_NUM_TCS_WIDTH (3U) 420 #define NETC_F3_SI0_SIPCAPR1_NUM_TCS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR1_NUM_TCS_SHIFT)) & NETC_F3_SI0_SIPCAPR1_NUM_TCS_MASK) 421 422 #define NETC_F3_SI0_SIPCAPR1_NUM_MCH_MASK (0x300U) 423 #define NETC_F3_SI0_SIPCAPR1_NUM_MCH_SHIFT (8U) 424 #define NETC_F3_SI0_SIPCAPR1_NUM_MCH_WIDTH (2U) 425 #define NETC_F3_SI0_SIPCAPR1_NUM_MCH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR1_NUM_MCH_SHIFT)) & NETC_F3_SI0_SIPCAPR1_NUM_MCH_MASK) 426 427 #define NETC_F3_SI0_SIPCAPR1_NUM_UCH_MASK (0xC00U) 428 #define NETC_F3_SI0_SIPCAPR1_NUM_UCH_SHIFT (10U) 429 #define NETC_F3_SI0_SIPCAPR1_NUM_UCH_WIDTH (2U) 430 #define NETC_F3_SI0_SIPCAPR1_NUM_UCH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR1_NUM_UCH_SHIFT)) & NETC_F3_SI0_SIPCAPR1_NUM_UCH_MASK) 431 432 #define NETC_F3_SI0_SIPCAPR1_NUM_MSIX_MASK (0x3F000U) 433 #define NETC_F3_SI0_SIPCAPR1_NUM_MSIX_SHIFT (12U) 434 #define NETC_F3_SI0_SIPCAPR1_NUM_MSIX_WIDTH (6U) 435 #define NETC_F3_SI0_SIPCAPR1_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR1_NUM_MSIX_SHIFT)) & NETC_F3_SI0_SIPCAPR1_NUM_MSIX_MASK) 436 437 #define NETC_F3_SI0_SIPCAPR1_NUM_IPV_MASK (0x80000000U) 438 #define NETC_F3_SI0_SIPCAPR1_NUM_IPV_SHIFT (31U) 439 #define NETC_F3_SI0_SIPCAPR1_NUM_IPV_WIDTH (1U) 440 #define NETC_F3_SI0_SIPCAPR1_NUM_IPV(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPCAPR1_NUM_IPV_SHIFT)) & NETC_F3_SI0_SIPCAPR1_NUM_IPV_MASK) 441 /*! @} */ 442 443 /*! @name SITSR - Station interface timer status register */ 444 /*! @{ */ 445 446 #define NETC_F3_SI0_SITSR_SYNC_MASK (0x1U) 447 #define NETC_F3_SI0_SITSR_SYNC_SHIFT (0U) 448 #define NETC_F3_SI0_SITSR_SYNC_WIDTH (1U) 449 #define NETC_F3_SI0_SITSR_SYNC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITSR_SYNC_SHIFT)) & NETC_F3_SI0_SITSR_SYNC_MASK) 450 451 #define NETC_F3_SI0_SITSR_PARAM_VAL_MASK (0xFFFFFFFEU) 452 #define NETC_F3_SI0_SITSR_PARAM_VAL_SHIFT (1U) 453 #define NETC_F3_SI0_SITSR_PARAM_VAL_WIDTH (31U) 454 #define NETC_F3_SI0_SITSR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITSR_PARAM_VAL_SHIFT)) & NETC_F3_SI0_SITSR_PARAM_VAL_MASK) 455 /*! @} */ 456 457 /*! @name SIRBGCR - Station interface receive BDR group control register */ 458 /*! @{ */ 459 460 #define NETC_F3_SI0_SIRBGCR_NUM_GROUPS_MASK (0x3U) 461 #define NETC_F3_SI0_SIRBGCR_NUM_GROUPS_SHIFT (0U) 462 #define NETC_F3_SI0_SIRBGCR_NUM_GROUPS_WIDTH (2U) 463 #define NETC_F3_SI0_SIRBGCR_NUM_GROUPS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRBGCR_NUM_GROUPS_SHIFT)) & NETC_F3_SI0_SIRBGCR_NUM_GROUPS_MASK) 464 465 #define NETC_F3_SI0_SIRBGCR_RINGS_PER_GROUP_MASK (0x70000U) 466 #define NETC_F3_SI0_SIRBGCR_RINGS_PER_GROUP_SHIFT (16U) 467 #define NETC_F3_SI0_SIRBGCR_RINGS_PER_GROUP_WIDTH (3U) 468 #define NETC_F3_SI0_SIRBGCR_RINGS_PER_GROUP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRBGCR_RINGS_PER_GROUP_SHIFT)) & NETC_F3_SI0_SIRBGCR_RINGS_PER_GROUP_MASK) 469 /*! @} */ 470 471 /*! @name SIBCAR - Station interface buffer cache attribute register */ 472 /*! @{ */ 473 474 #define NETC_F3_SI0_SIBCAR_BD_WRCACHE_MASK (0xFU) 475 #define NETC_F3_SI0_SIBCAR_BD_WRCACHE_SHIFT (0U) 476 #define NETC_F3_SI0_SIBCAR_BD_WRCACHE_WIDTH (4U) 477 #define NETC_F3_SI0_SIBCAR_BD_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIBCAR_BD_WRCACHE_SHIFT)) & NETC_F3_SI0_SIBCAR_BD_WRCACHE_MASK) 478 479 #define NETC_F3_SI0_SIBCAR_BD_WRDOMAIN_MASK (0x30U) 480 #define NETC_F3_SI0_SIBCAR_BD_WRDOMAIN_SHIFT (4U) 481 #define NETC_F3_SI0_SIBCAR_BD_WRDOMAIN_WIDTH (2U) 482 #define NETC_F3_SI0_SIBCAR_BD_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIBCAR_BD_WRDOMAIN_SHIFT)) & NETC_F3_SI0_SIBCAR_BD_WRDOMAIN_MASK) 483 484 #define NETC_F3_SI0_SIBCAR_BD_WRSNP_MASK (0x40U) 485 #define NETC_F3_SI0_SIBCAR_BD_WRSNP_SHIFT (6U) 486 #define NETC_F3_SI0_SIBCAR_BD_WRSNP_WIDTH (1U) 487 #define NETC_F3_SI0_SIBCAR_BD_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIBCAR_BD_WRSNP_SHIFT)) & NETC_F3_SI0_SIBCAR_BD_WRSNP_MASK) 488 489 #define NETC_F3_SI0_SIBCAR_WRCACHE_MASK (0xF00U) 490 #define NETC_F3_SI0_SIBCAR_WRCACHE_SHIFT (8U) 491 #define NETC_F3_SI0_SIBCAR_WRCACHE_WIDTH (4U) 492 #define NETC_F3_SI0_SIBCAR_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIBCAR_WRCACHE_SHIFT)) & NETC_F3_SI0_SIBCAR_WRCACHE_MASK) 493 494 #define NETC_F3_SI0_SIBCAR_WRDOMAIN_MASK (0x3000U) 495 #define NETC_F3_SI0_SIBCAR_WRDOMAIN_SHIFT (12U) 496 #define NETC_F3_SI0_SIBCAR_WRDOMAIN_WIDTH (2U) 497 #define NETC_F3_SI0_SIBCAR_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIBCAR_WRDOMAIN_SHIFT)) & NETC_F3_SI0_SIBCAR_WRDOMAIN_MASK) 498 499 #define NETC_F3_SI0_SIBCAR_WRSNP_MASK (0x4000U) 500 #define NETC_F3_SI0_SIBCAR_WRSNP_SHIFT (14U) 501 #define NETC_F3_SI0_SIBCAR_WRSNP_WIDTH (1U) 502 #define NETC_F3_SI0_SIBCAR_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIBCAR_WRSNP_SHIFT)) & NETC_F3_SI0_SIBCAR_WRSNP_MASK) 503 504 #define NETC_F3_SI0_SIBCAR_BD_RDCACHE_MASK (0xF0000U) 505 #define NETC_F3_SI0_SIBCAR_BD_RDCACHE_SHIFT (16U) 506 #define NETC_F3_SI0_SIBCAR_BD_RDCACHE_WIDTH (4U) 507 #define NETC_F3_SI0_SIBCAR_BD_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIBCAR_BD_RDCACHE_SHIFT)) & NETC_F3_SI0_SIBCAR_BD_RDCACHE_MASK) 508 509 #define NETC_F3_SI0_SIBCAR_BD_RDDOMAIN_MASK (0x300000U) 510 #define NETC_F3_SI0_SIBCAR_BD_RDDOMAIN_SHIFT (20U) 511 #define NETC_F3_SI0_SIBCAR_BD_RDDOMAIN_WIDTH (2U) 512 #define NETC_F3_SI0_SIBCAR_BD_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIBCAR_BD_RDDOMAIN_SHIFT)) & NETC_F3_SI0_SIBCAR_BD_RDDOMAIN_MASK) 513 514 #define NETC_F3_SI0_SIBCAR_BD_RDSNP_MASK (0x400000U) 515 #define NETC_F3_SI0_SIBCAR_BD_RDSNP_SHIFT (22U) 516 #define NETC_F3_SI0_SIBCAR_BD_RDSNP_WIDTH (1U) 517 #define NETC_F3_SI0_SIBCAR_BD_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIBCAR_BD_RDSNP_SHIFT)) & NETC_F3_SI0_SIBCAR_BD_RDSNP_MASK) 518 519 #define NETC_F3_SI0_SIBCAR_RDCACHE_MASK (0xF000000U) 520 #define NETC_F3_SI0_SIBCAR_RDCACHE_SHIFT (24U) 521 #define NETC_F3_SI0_SIBCAR_RDCACHE_WIDTH (4U) 522 #define NETC_F3_SI0_SIBCAR_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIBCAR_RDCACHE_SHIFT)) & NETC_F3_SI0_SIBCAR_RDCACHE_MASK) 523 524 #define NETC_F3_SI0_SIBCAR_RDDOMAIN_MASK (0x30000000U) 525 #define NETC_F3_SI0_SIBCAR_RDDOMAIN_SHIFT (28U) 526 #define NETC_F3_SI0_SIBCAR_RDDOMAIN_WIDTH (2U) 527 #define NETC_F3_SI0_SIBCAR_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIBCAR_RDDOMAIN_SHIFT)) & NETC_F3_SI0_SIBCAR_RDDOMAIN_MASK) 528 529 #define NETC_F3_SI0_SIBCAR_RDSNP_MASK (0x40000000U) 530 #define NETC_F3_SI0_SIBCAR_RDSNP_SHIFT (30U) 531 #define NETC_F3_SI0_SIBCAR_RDSNP_WIDTH (1U) 532 #define NETC_F3_SI0_SIBCAR_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIBCAR_RDSNP_SHIFT)) & NETC_F3_SI0_SIBCAR_RDSNP_MASK) 533 /*! @} */ 534 535 /*! @name SIMCAR - Station interface message cache attribute register */ 536 /*! @{ */ 537 538 #define NETC_F3_SI0_SIMCAR_MSG_WRCACHE_MASK (0xFU) 539 #define NETC_F3_SI0_SIMCAR_MSG_WRCACHE_SHIFT (0U) 540 #define NETC_F3_SI0_SIMCAR_MSG_WRCACHE_WIDTH (4U) 541 #define NETC_F3_SI0_SIMCAR_MSG_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMCAR_MSG_WRCACHE_SHIFT)) & NETC_F3_SI0_SIMCAR_MSG_WRCACHE_MASK) 542 543 #define NETC_F3_SI0_SIMCAR_MSG_WRDOMAIN_MASK (0x30U) 544 #define NETC_F3_SI0_SIMCAR_MSG_WRDOMAIN_SHIFT (4U) 545 #define NETC_F3_SI0_SIMCAR_MSG_WRDOMAIN_WIDTH (2U) 546 #define NETC_F3_SI0_SIMCAR_MSG_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMCAR_MSG_WRDOMAIN_SHIFT)) & NETC_F3_SI0_SIMCAR_MSG_WRDOMAIN_MASK) 547 548 #define NETC_F3_SI0_SIMCAR_MSG_WRSNP_MASK (0x40U) 549 #define NETC_F3_SI0_SIMCAR_MSG_WRSNP_SHIFT (6U) 550 #define NETC_F3_SI0_SIMCAR_MSG_WRSNP_WIDTH (1U) 551 #define NETC_F3_SI0_SIMCAR_MSG_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMCAR_MSG_WRSNP_SHIFT)) & NETC_F3_SI0_SIMCAR_MSG_WRSNP_MASK) 552 553 #define NETC_F3_SI0_SIMCAR_MSG_RDCACHE_MASK (0xF0000U) 554 #define NETC_F3_SI0_SIMCAR_MSG_RDCACHE_SHIFT (16U) 555 #define NETC_F3_SI0_SIMCAR_MSG_RDCACHE_WIDTH (4U) 556 #define NETC_F3_SI0_SIMCAR_MSG_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMCAR_MSG_RDCACHE_SHIFT)) & NETC_F3_SI0_SIMCAR_MSG_RDCACHE_MASK) 557 558 #define NETC_F3_SI0_SIMCAR_MSG_RDDOMAIN_MASK (0x300000U) 559 #define NETC_F3_SI0_SIMCAR_MSG_RDDOMAIN_SHIFT (20U) 560 #define NETC_F3_SI0_SIMCAR_MSG_RDDOMAIN_WIDTH (2U) 561 #define NETC_F3_SI0_SIMCAR_MSG_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMCAR_MSG_RDDOMAIN_SHIFT)) & NETC_F3_SI0_SIMCAR_MSG_RDDOMAIN_MASK) 562 563 #define NETC_F3_SI0_SIMCAR_MSG_RDSNP_MASK (0x400000U) 564 #define NETC_F3_SI0_SIMCAR_MSG_RDSNP_SHIFT (22U) 565 #define NETC_F3_SI0_SIMCAR_MSG_RDSNP_WIDTH (1U) 566 #define NETC_F3_SI0_SIMCAR_MSG_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMCAR_MSG_RDSNP_SHIFT)) & NETC_F3_SI0_SIMCAR_MSG_RDSNP_MASK) 567 /*! @} */ 568 569 /*! @name SICCAR - Station interface command cache attribute register */ 570 /*! @{ */ 571 572 #define NETC_F3_SI0_SICCAR_CBD_WRCACHE_MASK (0xFU) 573 #define NETC_F3_SI0_SICCAR_CBD_WRCACHE_SHIFT (0U) 574 #define NETC_F3_SI0_SICCAR_CBD_WRCACHE_WIDTH (4U) 575 #define NETC_F3_SI0_SICCAR_CBD_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICCAR_CBD_WRCACHE_SHIFT)) & NETC_F3_SI0_SICCAR_CBD_WRCACHE_MASK) 576 577 #define NETC_F3_SI0_SICCAR_CBD_WRDOMAIN_MASK (0x30U) 578 #define NETC_F3_SI0_SICCAR_CBD_WRDOMAIN_SHIFT (4U) 579 #define NETC_F3_SI0_SICCAR_CBD_WRDOMAIN_WIDTH (2U) 580 #define NETC_F3_SI0_SICCAR_CBD_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICCAR_CBD_WRDOMAIN_SHIFT)) & NETC_F3_SI0_SICCAR_CBD_WRDOMAIN_MASK) 581 582 #define NETC_F3_SI0_SICCAR_CBD_WRSNP_MASK (0x40U) 583 #define NETC_F3_SI0_SICCAR_CBD_WRSNP_SHIFT (6U) 584 #define NETC_F3_SI0_SICCAR_CBD_WRSNP_WIDTH (1U) 585 #define NETC_F3_SI0_SICCAR_CBD_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICCAR_CBD_WRSNP_SHIFT)) & NETC_F3_SI0_SICCAR_CBD_WRSNP_MASK) 586 587 #define NETC_F3_SI0_SICCAR_CWRCACHE_MASK (0xF00U) 588 #define NETC_F3_SI0_SICCAR_CWRCACHE_SHIFT (8U) 589 #define NETC_F3_SI0_SICCAR_CWRCACHE_WIDTH (4U) 590 #define NETC_F3_SI0_SICCAR_CWRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICCAR_CWRCACHE_SHIFT)) & NETC_F3_SI0_SICCAR_CWRCACHE_MASK) 591 592 #define NETC_F3_SI0_SICCAR_CWRDOMAIN_MASK (0x3000U) 593 #define NETC_F3_SI0_SICCAR_CWRDOMAIN_SHIFT (12U) 594 #define NETC_F3_SI0_SICCAR_CWRDOMAIN_WIDTH (2U) 595 #define NETC_F3_SI0_SICCAR_CWRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICCAR_CWRDOMAIN_SHIFT)) & NETC_F3_SI0_SICCAR_CWRDOMAIN_MASK) 596 597 #define NETC_F3_SI0_SICCAR_CWRSNP_MASK (0x4000U) 598 #define NETC_F3_SI0_SICCAR_CWRSNP_SHIFT (14U) 599 #define NETC_F3_SI0_SICCAR_CWRSNP_WIDTH (1U) 600 #define NETC_F3_SI0_SICCAR_CWRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICCAR_CWRSNP_SHIFT)) & NETC_F3_SI0_SICCAR_CWRSNP_MASK) 601 602 #define NETC_F3_SI0_SICCAR_CBD_RDCACHE_MASK (0xF0000U) 603 #define NETC_F3_SI0_SICCAR_CBD_RDCACHE_SHIFT (16U) 604 #define NETC_F3_SI0_SICCAR_CBD_RDCACHE_WIDTH (4U) 605 #define NETC_F3_SI0_SICCAR_CBD_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICCAR_CBD_RDCACHE_SHIFT)) & NETC_F3_SI0_SICCAR_CBD_RDCACHE_MASK) 606 607 #define NETC_F3_SI0_SICCAR_CBD_RDDOMAIN_MASK (0x300000U) 608 #define NETC_F3_SI0_SICCAR_CBD_RDDOMAIN_SHIFT (20U) 609 #define NETC_F3_SI0_SICCAR_CBD_RDDOMAIN_WIDTH (2U) 610 #define NETC_F3_SI0_SICCAR_CBD_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICCAR_CBD_RDDOMAIN_SHIFT)) & NETC_F3_SI0_SICCAR_CBD_RDDOMAIN_MASK) 611 612 #define NETC_F3_SI0_SICCAR_CBD_RDSNP_MASK (0x400000U) 613 #define NETC_F3_SI0_SICCAR_CBD_RDSNP_SHIFT (22U) 614 #define NETC_F3_SI0_SICCAR_CBD_RDSNP_WIDTH (1U) 615 #define NETC_F3_SI0_SICCAR_CBD_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICCAR_CBD_RDSNP_SHIFT)) & NETC_F3_SI0_SICCAR_CBD_RDSNP_MASK) 616 617 #define NETC_F3_SI0_SICCAR_CRDCACHE_MASK (0xF000000U) 618 #define NETC_F3_SI0_SICCAR_CRDCACHE_SHIFT (24U) 619 #define NETC_F3_SI0_SICCAR_CRDCACHE_WIDTH (4U) 620 #define NETC_F3_SI0_SICCAR_CRDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICCAR_CRDCACHE_SHIFT)) & NETC_F3_SI0_SICCAR_CRDCACHE_MASK) 621 622 #define NETC_F3_SI0_SICCAR_CRDDOMAIN_MASK (0x30000000U) 623 #define NETC_F3_SI0_SICCAR_CRDDOMAIN_SHIFT (28U) 624 #define NETC_F3_SI0_SICCAR_CRDDOMAIN_WIDTH (2U) 625 #define NETC_F3_SI0_SICCAR_CRDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICCAR_CRDDOMAIN_SHIFT)) & NETC_F3_SI0_SICCAR_CRDDOMAIN_MASK) 626 627 #define NETC_F3_SI0_SICCAR_CRDSNP_MASK (0x40000000U) 628 #define NETC_F3_SI0_SICCAR_CRDSNP_SHIFT (30U) 629 #define NETC_F3_SI0_SICCAR_CRDSNP_WIDTH (1U) 630 #define NETC_F3_SI0_SICCAR_CRDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICCAR_CRDSNP_SHIFT)) & NETC_F3_SI0_SICCAR_CRDSNP_MASK) 631 /*! @} */ 632 633 /*! @name SIPMAR0 - Station interface primary MAC address register 0 */ 634 /*! @{ */ 635 636 #define NETC_F3_SI0_SIPMAR0_PRIM_MAC_ADDR_MASK (0xFFFFFFFFU) 637 #define NETC_F3_SI0_SIPMAR0_PRIM_MAC_ADDR_SHIFT (0U) 638 #define NETC_F3_SI0_SIPMAR0_PRIM_MAC_ADDR_WIDTH (32U) 639 #define NETC_F3_SI0_SIPMAR0_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPMAR0_PRIM_MAC_ADDR_SHIFT)) & NETC_F3_SI0_SIPMAR0_PRIM_MAC_ADDR_MASK) 640 /*! @} */ 641 642 /*! @name SIPMAR1 - Station interface primary MAC address register 1 */ 643 /*! @{ */ 644 645 #define NETC_F3_SI0_SIPMAR1_PRIM_MAC_ADDR_MASK (0xFFFFU) 646 #define NETC_F3_SI0_SIPMAR1_PRIM_MAC_ADDR_SHIFT (0U) 647 #define NETC_F3_SI0_SIPMAR1_PRIM_MAC_ADDR_WIDTH (16U) 648 #define NETC_F3_SI0_SIPMAR1_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIPMAR1_PRIM_MAC_ADDR_SHIFT)) & NETC_F3_SI0_SIPMAR1_PRIM_MAC_ADDR_MASK) 649 /*! @} */ 650 651 /*! @name SICVLANR1 - Station interface custom VLAN register 1 */ 652 /*! @{ */ 653 654 #define NETC_F3_SI0_SICVLANR1_ETYPE_MASK (0xFFFFU) 655 #define NETC_F3_SI0_SICVLANR1_ETYPE_SHIFT (0U) 656 #define NETC_F3_SI0_SICVLANR1_ETYPE_WIDTH (16U) 657 #define NETC_F3_SI0_SICVLANR1_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICVLANR1_ETYPE_SHIFT)) & NETC_F3_SI0_SICVLANR1_ETYPE_MASK) 658 659 #define NETC_F3_SI0_SICVLANR1_V_MASK (0x80000000U) 660 #define NETC_F3_SI0_SICVLANR1_V_SHIFT (31U) 661 #define NETC_F3_SI0_SICVLANR1_V_WIDTH (1U) 662 #define NETC_F3_SI0_SICVLANR1_V(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICVLANR1_V_SHIFT)) & NETC_F3_SI0_SICVLANR1_V_MASK) 663 /*! @} */ 664 665 /*! @name SICVLANR2 - Station interface custom VLAN register 2 */ 666 /*! @{ */ 667 668 #define NETC_F3_SI0_SICVLANR2_ETYPE_MASK (0xFFFFU) 669 #define NETC_F3_SI0_SICVLANR2_ETYPE_SHIFT (0U) 670 #define NETC_F3_SI0_SICVLANR2_ETYPE_WIDTH (16U) 671 #define NETC_F3_SI0_SICVLANR2_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICVLANR2_ETYPE_SHIFT)) & NETC_F3_SI0_SICVLANR2_ETYPE_MASK) 672 673 #define NETC_F3_SI0_SICVLANR2_V_MASK (0x80000000U) 674 #define NETC_F3_SI0_SICVLANR2_V_SHIFT (31U) 675 #define NETC_F3_SI0_SICVLANR2_V_WIDTH (1U) 676 #define NETC_F3_SI0_SICVLANR2_V(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICVLANR2_V_SHIFT)) & NETC_F3_SI0_SICVLANR2_V_MASK) 677 /*! @} */ 678 679 /*! @name SIVLANIPVMR0 - Station interface VLAN to IPV mapping register 0 */ 680 /*! @{ */ 681 682 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_0_MASK (0xFU) 683 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_0_SHIFT (0U) 684 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_0_WIDTH (4U) 685 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_0_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_0_MASK) 686 687 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_1_MASK (0xF0U) 688 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_1_SHIFT (4U) 689 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_1_WIDTH (4U) 690 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_1_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_1_MASK) 691 692 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_2_MASK (0xF00U) 693 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_2_SHIFT (8U) 694 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_2_WIDTH (4U) 695 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_2_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_2_MASK) 696 697 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_3_MASK (0xF000U) 698 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_3_SHIFT (12U) 699 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_3_WIDTH (4U) 700 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_3_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_3_MASK) 701 702 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_4_MASK (0xF0000U) 703 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_4_SHIFT (16U) 704 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_4_WIDTH (4U) 705 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_4_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_4_MASK) 706 707 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_5_MASK (0xF00000U) 708 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_5_SHIFT (20U) 709 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_5_WIDTH (4U) 710 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_5_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_5_MASK) 711 712 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_6_MASK (0xF000000U) 713 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_6_SHIFT (24U) 714 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_6_WIDTH (4U) 715 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_6_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_6_MASK) 716 717 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_7_MASK (0xF0000000U) 718 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_7_SHIFT (28U) 719 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_7_WIDTH (4U) 720 #define NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_7_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR0_PCP_DEI_7_MASK) 721 /*! @} */ 722 723 /*! @name SIVLANIPVMR1 - Station interface VLAN to IPV mapping register 1 */ 724 /*! @{ */ 725 726 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_8_MASK (0xFU) 727 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_8_SHIFT (0U) 728 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_8_WIDTH (4U) 729 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_8(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_8_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_8_MASK) 730 731 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_9_MASK (0xF0U) 732 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_9_SHIFT (4U) 733 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_9_WIDTH (4U) 734 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_9(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_9_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_9_MASK) 735 736 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_10_MASK (0xF00U) 737 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_10_SHIFT (8U) 738 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_10_WIDTH (4U) 739 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_10(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_10_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_10_MASK) 740 741 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_11_MASK (0xF000U) 742 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_11_SHIFT (12U) 743 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_11_WIDTH (4U) 744 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_11(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_11_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_11_MASK) 745 746 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_12_MASK (0xF0000U) 747 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_12_SHIFT (16U) 748 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_12_WIDTH (4U) 749 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_12(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_12_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_12_MASK) 750 751 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_13_MASK (0xF00000U) 752 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_13_SHIFT (20U) 753 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_13_WIDTH (4U) 754 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_13(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_13_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_13_MASK) 755 756 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_14_MASK (0xF000000U) 757 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_14_SHIFT (24U) 758 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_14_WIDTH (4U) 759 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_14(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_14_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_14_MASK) 760 761 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_15_MASK (0xF0000000U) 762 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_15_SHIFT (28U) 763 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_15_WIDTH (4U) 764 #define NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_15(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_15_SHIFT)) & NETC_F3_SI0_SIVLANIPVMR1_PCP_DEI_15_MASK) 765 /*! @} */ 766 767 /*! @name SIIPVBDRMR0 - Station interface IPV to ring mapping register */ 768 /*! @{ */ 769 770 #define NETC_F3_SI0_SIIPVBDRMR0_IPV0BDR_MASK (0x7U) 771 #define NETC_F3_SI0_SIIPVBDRMR0_IPV0BDR_SHIFT (0U) 772 #define NETC_F3_SI0_SIIPVBDRMR0_IPV0BDR_WIDTH (3U) 773 #define NETC_F3_SI0_SIIPVBDRMR0_IPV0BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIIPVBDRMR0_IPV0BDR_SHIFT)) & NETC_F3_SI0_SIIPVBDRMR0_IPV0BDR_MASK) 774 775 #define NETC_F3_SI0_SIIPVBDRMR0_IPV1BDR_MASK (0x70U) 776 #define NETC_F3_SI0_SIIPVBDRMR0_IPV1BDR_SHIFT (4U) 777 #define NETC_F3_SI0_SIIPVBDRMR0_IPV1BDR_WIDTH (3U) 778 #define NETC_F3_SI0_SIIPVBDRMR0_IPV1BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIIPVBDRMR0_IPV1BDR_SHIFT)) & NETC_F3_SI0_SIIPVBDRMR0_IPV1BDR_MASK) 779 780 #define NETC_F3_SI0_SIIPVBDRMR0_IPV2BDR_MASK (0x700U) 781 #define NETC_F3_SI0_SIIPVBDRMR0_IPV2BDR_SHIFT (8U) 782 #define NETC_F3_SI0_SIIPVBDRMR0_IPV2BDR_WIDTH (3U) 783 #define NETC_F3_SI0_SIIPVBDRMR0_IPV2BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIIPVBDRMR0_IPV2BDR_SHIFT)) & NETC_F3_SI0_SIIPVBDRMR0_IPV2BDR_MASK) 784 785 #define NETC_F3_SI0_SIIPVBDRMR0_IPV3BDR_MASK (0x7000U) 786 #define NETC_F3_SI0_SIIPVBDRMR0_IPV3BDR_SHIFT (12U) 787 #define NETC_F3_SI0_SIIPVBDRMR0_IPV3BDR_WIDTH (3U) 788 #define NETC_F3_SI0_SIIPVBDRMR0_IPV3BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIIPVBDRMR0_IPV3BDR_SHIFT)) & NETC_F3_SI0_SIIPVBDRMR0_IPV3BDR_MASK) 789 790 #define NETC_F3_SI0_SIIPVBDRMR0_IPV4BDR_MASK (0x70000U) 791 #define NETC_F3_SI0_SIIPVBDRMR0_IPV4BDR_SHIFT (16U) 792 #define NETC_F3_SI0_SIIPVBDRMR0_IPV4BDR_WIDTH (3U) 793 #define NETC_F3_SI0_SIIPVBDRMR0_IPV4BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIIPVBDRMR0_IPV4BDR_SHIFT)) & NETC_F3_SI0_SIIPVBDRMR0_IPV4BDR_MASK) 794 795 #define NETC_F3_SI0_SIIPVBDRMR0_IPV5BDR_MASK (0x700000U) 796 #define NETC_F3_SI0_SIIPVBDRMR0_IPV5BDR_SHIFT (20U) 797 #define NETC_F3_SI0_SIIPVBDRMR0_IPV5BDR_WIDTH (3U) 798 #define NETC_F3_SI0_SIIPVBDRMR0_IPV5BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIIPVBDRMR0_IPV5BDR_SHIFT)) & NETC_F3_SI0_SIIPVBDRMR0_IPV5BDR_MASK) 799 800 #define NETC_F3_SI0_SIIPVBDRMR0_IPV6BDR_MASK (0x7000000U) 801 #define NETC_F3_SI0_SIIPVBDRMR0_IPV6BDR_SHIFT (24U) 802 #define NETC_F3_SI0_SIIPVBDRMR0_IPV6BDR_WIDTH (3U) 803 #define NETC_F3_SI0_SIIPVBDRMR0_IPV6BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIIPVBDRMR0_IPV6BDR_SHIFT)) & NETC_F3_SI0_SIIPVBDRMR0_IPV6BDR_MASK) 804 805 #define NETC_F3_SI0_SIIPVBDRMR0_IPV7BDR_MASK (0x70000000U) 806 #define NETC_F3_SI0_SIIPVBDRMR0_IPV7BDR_SHIFT (28U) 807 #define NETC_F3_SI0_SIIPVBDRMR0_IPV7BDR_WIDTH (3U) 808 #define NETC_F3_SI0_SIIPVBDRMR0_IPV7BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIIPVBDRMR0_IPV7BDR_SHIFT)) & NETC_F3_SI0_SIIPVBDRMR0_IPV7BDR_MASK) 809 /*! @} */ 810 811 /*! @name PSIMSGRR - Physical station interface message receive register */ 812 /*! @{ */ 813 814 #define NETC_F3_SI0_PSIMSGRR_MR1_MASK (0x2U) 815 #define NETC_F3_SI0_PSIMSGRR_MR1_SHIFT (1U) 816 #define NETC_F3_SI0_PSIMSGRR_MR1_WIDTH (1U) 817 #define NETC_F3_SI0_PSIMSGRR_MR1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGRR_MR1_SHIFT)) & NETC_F3_SI0_PSIMSGRR_MR1_MASK) 818 819 #define NETC_F3_SI0_PSIMSGRR_MR2_MASK (0x4U) 820 #define NETC_F3_SI0_PSIMSGRR_MR2_SHIFT (2U) 821 #define NETC_F3_SI0_PSIMSGRR_MR2_WIDTH (1U) 822 #define NETC_F3_SI0_PSIMSGRR_MR2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGRR_MR2_SHIFT)) & NETC_F3_SI0_PSIMSGRR_MR2_MASK) 823 824 #define NETC_F3_SI0_PSIMSGRR_MR3_MASK (0x8U) 825 #define NETC_F3_SI0_PSIMSGRR_MR3_SHIFT (3U) 826 #define NETC_F3_SI0_PSIMSGRR_MR3_WIDTH (1U) 827 #define NETC_F3_SI0_PSIMSGRR_MR3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGRR_MR3_SHIFT)) & NETC_F3_SI0_PSIMSGRR_MR3_MASK) 828 829 #define NETC_F3_SI0_PSIMSGRR_MR4_MASK (0x10U) 830 #define NETC_F3_SI0_PSIMSGRR_MR4_SHIFT (4U) 831 #define NETC_F3_SI0_PSIMSGRR_MR4_WIDTH (1U) 832 #define NETC_F3_SI0_PSIMSGRR_MR4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGRR_MR4_SHIFT)) & NETC_F3_SI0_PSIMSGRR_MR4_MASK) 833 834 #define NETC_F3_SI0_PSIMSGRR_MR5_MASK (0x20U) 835 #define NETC_F3_SI0_PSIMSGRR_MR5_SHIFT (5U) 836 #define NETC_F3_SI0_PSIMSGRR_MR5_WIDTH (1U) 837 #define NETC_F3_SI0_PSIMSGRR_MR5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGRR_MR5_SHIFT)) & NETC_F3_SI0_PSIMSGRR_MR5_MASK) 838 839 #define NETC_F3_SI0_PSIMSGRR_MR6_MASK (0x40U) 840 #define NETC_F3_SI0_PSIMSGRR_MR6_SHIFT (6U) 841 #define NETC_F3_SI0_PSIMSGRR_MR6_WIDTH (1U) 842 #define NETC_F3_SI0_PSIMSGRR_MR6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGRR_MR6_SHIFT)) & NETC_F3_SI0_PSIMSGRR_MR6_MASK) 843 844 #define NETC_F3_SI0_PSIMSGRR_MR7_MASK (0x80U) 845 #define NETC_F3_SI0_PSIMSGRR_MR7_SHIFT (7U) 846 #define NETC_F3_SI0_PSIMSGRR_MR7_WIDTH (1U) 847 #define NETC_F3_SI0_PSIMSGRR_MR7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGRR_MR7_SHIFT)) & NETC_F3_SI0_PSIMSGRR_MR7_MASK) 848 849 #define NETC_F3_SI0_PSIMSGRR_MC_MASK (0xFFFF0000U) 850 #define NETC_F3_SI0_PSIMSGRR_MC_SHIFT (16U) 851 #define NETC_F3_SI0_PSIMSGRR_MC_WIDTH (16U) 852 #define NETC_F3_SI0_PSIMSGRR_MC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGRR_MC_SHIFT)) & NETC_F3_SI0_PSIMSGRR_MC_MASK) 853 /*! @} */ 854 855 /*! @name PSIMSGSR - Physical station interface message send register */ 856 /*! @{ */ 857 858 #define NETC_F3_SI0_PSIMSGSR_MS1_MASK (0x2U) 859 #define NETC_F3_SI0_PSIMSGSR_MS1_SHIFT (1U) 860 #define NETC_F3_SI0_PSIMSGSR_MS1_WIDTH (1U) 861 #define NETC_F3_SI0_PSIMSGSR_MS1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGSR_MS1_SHIFT)) & NETC_F3_SI0_PSIMSGSR_MS1_MASK) 862 863 #define NETC_F3_SI0_PSIMSGSR_MS2_MASK (0x4U) 864 #define NETC_F3_SI0_PSIMSGSR_MS2_SHIFT (2U) 865 #define NETC_F3_SI0_PSIMSGSR_MS2_WIDTH (1U) 866 #define NETC_F3_SI0_PSIMSGSR_MS2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGSR_MS2_SHIFT)) & NETC_F3_SI0_PSIMSGSR_MS2_MASK) 867 868 #define NETC_F3_SI0_PSIMSGSR_MS3_MASK (0x8U) 869 #define NETC_F3_SI0_PSIMSGSR_MS3_SHIFT (3U) 870 #define NETC_F3_SI0_PSIMSGSR_MS3_WIDTH (1U) 871 #define NETC_F3_SI0_PSIMSGSR_MS3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGSR_MS3_SHIFT)) & NETC_F3_SI0_PSIMSGSR_MS3_MASK) 872 873 #define NETC_F3_SI0_PSIMSGSR_MS4_MASK (0x10U) 874 #define NETC_F3_SI0_PSIMSGSR_MS4_SHIFT (4U) 875 #define NETC_F3_SI0_PSIMSGSR_MS4_WIDTH (1U) 876 #define NETC_F3_SI0_PSIMSGSR_MS4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGSR_MS4_SHIFT)) & NETC_F3_SI0_PSIMSGSR_MS4_MASK) 877 878 #define NETC_F3_SI0_PSIMSGSR_MS5_MASK (0x20U) 879 #define NETC_F3_SI0_PSIMSGSR_MS5_SHIFT (5U) 880 #define NETC_F3_SI0_PSIMSGSR_MS5_WIDTH (1U) 881 #define NETC_F3_SI0_PSIMSGSR_MS5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGSR_MS5_SHIFT)) & NETC_F3_SI0_PSIMSGSR_MS5_MASK) 882 883 #define NETC_F3_SI0_PSIMSGSR_MS6_MASK (0x40U) 884 #define NETC_F3_SI0_PSIMSGSR_MS6_SHIFT (6U) 885 #define NETC_F3_SI0_PSIMSGSR_MS6_WIDTH (1U) 886 #define NETC_F3_SI0_PSIMSGSR_MS6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGSR_MS6_SHIFT)) & NETC_F3_SI0_PSIMSGSR_MS6_MASK) 887 888 #define NETC_F3_SI0_PSIMSGSR_MS7_MASK (0x80U) 889 #define NETC_F3_SI0_PSIMSGSR_MS7_SHIFT (7U) 890 #define NETC_F3_SI0_PSIMSGSR_MS7_WIDTH (1U) 891 #define NETC_F3_SI0_PSIMSGSR_MS7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGSR_MS7_SHIFT)) & NETC_F3_SI0_PSIMSGSR_MS7_MASK) 892 893 #define NETC_F3_SI0_PSIMSGSR_MC_MASK (0xFFFF0000U) 894 #define NETC_F3_SI0_PSIMSGSR_MC_SHIFT (16U) 895 #define NETC_F3_SI0_PSIMSGSR_MC_WIDTH (16U) 896 #define NETC_F3_SI0_PSIMSGSR_MC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIMSGSR_MC_SHIFT)) & NETC_F3_SI0_PSIMSGSR_MC_MASK) 897 /*! @} */ 898 899 /*! @name PSIVMSGRCVAR0 - PSI VSI 1 message receive address register 0..PSI VSI 7 message receive address register 0 */ 900 /*! @{ */ 901 902 #define NETC_F3_SI0_PSIVMSGRCVAR0_MSIZE_MASK (0x1FU) 903 #define NETC_F3_SI0_PSIVMSGRCVAR0_MSIZE_SHIFT (0U) 904 #define NETC_F3_SI0_PSIVMSGRCVAR0_MSIZE_WIDTH (5U) 905 #define NETC_F3_SI0_PSIVMSGRCVAR0_MSIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIVMSGRCVAR0_MSIZE_SHIFT)) & NETC_F3_SI0_PSIVMSGRCVAR0_MSIZE_MASK) 906 907 #define NETC_F3_SI0_PSIVMSGRCVAR0_ADDRL_MASK (0xFFFFFFC0U) 908 #define NETC_F3_SI0_PSIVMSGRCVAR0_ADDRL_SHIFT (6U) 909 #define NETC_F3_SI0_PSIVMSGRCVAR0_ADDRL_WIDTH (26U) 910 #define NETC_F3_SI0_PSIVMSGRCVAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIVMSGRCVAR0_ADDRL_SHIFT)) & NETC_F3_SI0_PSIVMSGRCVAR0_ADDRL_MASK) 911 /*! @} */ 912 913 /*! @name PSIVMSGRCVAR1 - PSI VSI 1 message receive address register 1..PSI VSI 7 message receive address register 1 */ 914 /*! @{ */ 915 916 #define NETC_F3_SI0_PSIVMSGRCVAR1_ADDRH_MASK (0xFFFFFFFFU) 917 #define NETC_F3_SI0_PSIVMSGRCVAR1_ADDRH_SHIFT (0U) 918 #define NETC_F3_SI0_PSIVMSGRCVAR1_ADDRH_WIDTH (32U) 919 #define NETC_F3_SI0_PSIVMSGRCVAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIVMSGRCVAR1_ADDRH_SHIFT)) & NETC_F3_SI0_PSIVMSGRCVAR1_ADDRH_MASK) 920 /*! @} */ 921 922 /*! @name SIROCT0 - Station interface receive octets counter (ifInOctets) 0 */ 923 /*! @{ */ 924 925 #define NETC_F3_SI0_SIROCT0_ROCT_LOW_MASK (0xFFFFFFFFU) 926 #define NETC_F3_SI0_SIROCT0_ROCT_LOW_SHIFT (0U) 927 #define NETC_F3_SI0_SIROCT0_ROCT_LOW_WIDTH (32U) 928 #define NETC_F3_SI0_SIROCT0_ROCT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIROCT0_ROCT_LOW_SHIFT)) & NETC_F3_SI0_SIROCT0_ROCT_LOW_MASK) 929 /*! @} */ 930 931 /*! @name SIROCT1 - Station interface receive octets counter (ifInOctets) 1 */ 932 /*! @{ */ 933 934 #define NETC_F3_SI0_SIROCT1_ROCT_HIGH_MASK (0xFFFFFFFFU) 935 #define NETC_F3_SI0_SIROCT1_ROCT_HIGH_SHIFT (0U) 936 #define NETC_F3_SI0_SIROCT1_ROCT_HIGH_WIDTH (32U) 937 #define NETC_F3_SI0_SIROCT1_ROCT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIROCT1_ROCT_HIGH_SHIFT)) & NETC_F3_SI0_SIROCT1_ROCT_HIGH_MASK) 938 /*! @} */ 939 940 /*! @name SIRFRM0 - Station interface receive frame counter (aFrameReceivedOK) 0 */ 941 /*! @{ */ 942 943 #define NETC_F3_SI0_SIRFRM0_RFRM_LOW_MASK (0xFFFFFFFFU) 944 #define NETC_F3_SI0_SIRFRM0_RFRM_LOW_SHIFT (0U) 945 #define NETC_F3_SI0_SIRFRM0_RFRM_LOW_WIDTH (32U) 946 #define NETC_F3_SI0_SIRFRM0_RFRM_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRFRM0_RFRM_LOW_SHIFT)) & NETC_F3_SI0_SIRFRM0_RFRM_LOW_MASK) 947 /*! @} */ 948 949 /*! @name SIRFRM1 - Station interface receive frame counter (aFrameReceivedOK) 1 */ 950 /*! @{ */ 951 952 #define NETC_F3_SI0_SIRFRM1_RFRM_HIGH_MASK (0xFFFFFFFFU) 953 #define NETC_F3_SI0_SIRFRM1_RFRM_HIGH_SHIFT (0U) 954 #define NETC_F3_SI0_SIRFRM1_RFRM_HIGH_WIDTH (32U) 955 #define NETC_F3_SI0_SIRFRM1_RFRM_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRFRM1_RFRM_HIGH_SHIFT)) & NETC_F3_SI0_SIRFRM1_RFRM_HIGH_MASK) 956 /*! @} */ 957 958 /*! @name SIRUCA0 - Station interface receive unicast frame counter (ifInUcastPkts) 0 */ 959 /*! @{ */ 960 961 #define NETC_F3_SI0_SIRUCA0_RUCA_LOW_MASK (0xFFFFFFFFU) 962 #define NETC_F3_SI0_SIRUCA0_RUCA_LOW_SHIFT (0U) 963 #define NETC_F3_SI0_SIRUCA0_RUCA_LOW_WIDTH (32U) 964 #define NETC_F3_SI0_SIRUCA0_RUCA_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRUCA0_RUCA_LOW_SHIFT)) & NETC_F3_SI0_SIRUCA0_RUCA_LOW_MASK) 965 /*! @} */ 966 967 /*! @name SIRUCA1 - Station interface receive unicast frame counter (ifInUcastPkts) 1 */ 968 /*! @{ */ 969 970 #define NETC_F3_SI0_SIRUCA1_RUCA_HIGH_MASK (0xFFFFFFFFU) 971 #define NETC_F3_SI0_SIRUCA1_RUCA_HIGH_SHIFT (0U) 972 #define NETC_F3_SI0_SIRUCA1_RUCA_HIGH_WIDTH (32U) 973 #define NETC_F3_SI0_SIRUCA1_RUCA_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRUCA1_RUCA_HIGH_SHIFT)) & NETC_F3_SI0_SIRUCA1_RUCA_HIGH_MASK) 974 /*! @} */ 975 976 /*! @name SIRMCA0 - Station interface receive multicast frame counter (ifInMulticastPkts) 0 */ 977 /*! @{ */ 978 979 #define NETC_F3_SI0_SIRMCA0_RMCA_LOW_MASK (0xFFFFFFFFU) 980 #define NETC_F3_SI0_SIRMCA0_RMCA_LOW_SHIFT (0U) 981 #define NETC_F3_SI0_SIRMCA0_RMCA_LOW_WIDTH (32U) 982 #define NETC_F3_SI0_SIRMCA0_RMCA_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRMCA0_RMCA_LOW_SHIFT)) & NETC_F3_SI0_SIRMCA0_RMCA_LOW_MASK) 983 /*! @} */ 984 985 /*! @name SIRMCA1 - Station interface receive multicast frame counter (ifInMulticastPkts) 1 */ 986 /*! @{ */ 987 988 #define NETC_F3_SI0_SIRMCA1_RMCA_HIGH_MASK (0xFFFFFFFFU) 989 #define NETC_F3_SI0_SIRMCA1_RMCA_HIGH_SHIFT (0U) 990 #define NETC_F3_SI0_SIRMCA1_RMCA_HIGH_WIDTH (32U) 991 #define NETC_F3_SI0_SIRMCA1_RMCA_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRMCA1_RMCA_HIGH_SHIFT)) & NETC_F3_SI0_SIRMCA1_RMCA_HIGH_MASK) 992 /*! @} */ 993 994 /*! @name SITOCT0 - Station interface transmit octets counter (ifOutOctets) 0 */ 995 /*! @{ */ 996 997 #define NETC_F3_SI0_SITOCT0_TOCT_LOW_MASK (0xFFFFFFFFU) 998 #define NETC_F3_SI0_SITOCT0_TOCT_LOW_SHIFT (0U) 999 #define NETC_F3_SI0_SITOCT0_TOCT_LOW_WIDTH (32U) 1000 #define NETC_F3_SI0_SITOCT0_TOCT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITOCT0_TOCT_LOW_SHIFT)) & NETC_F3_SI0_SITOCT0_TOCT_LOW_MASK) 1001 /*! @} */ 1002 1003 /*! @name SITOCT1 - Station interface transmit octets counter (ifOutOctets) 1 */ 1004 /*! @{ */ 1005 1006 #define NETC_F3_SI0_SITOCT1_TOCT_HIGH_MASK (0xFFFFFFFFU) 1007 #define NETC_F3_SI0_SITOCT1_TOCT_HIGH_SHIFT (0U) 1008 #define NETC_F3_SI0_SITOCT1_TOCT_HIGH_WIDTH (32U) 1009 #define NETC_F3_SI0_SITOCT1_TOCT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITOCT1_TOCT_HIGH_SHIFT)) & NETC_F3_SI0_SITOCT1_TOCT_HIGH_MASK) 1010 /*! @} */ 1011 1012 /*! @name SITFRM0 - Station interface transmit frame counter (aFrameTransmittedOK) 0 */ 1013 /*! @{ */ 1014 1015 #define NETC_F3_SI0_SITFRM0_TFRM_LOW_MASK (0xFFFFFFFFU) 1016 #define NETC_F3_SI0_SITFRM0_TFRM_LOW_SHIFT (0U) 1017 #define NETC_F3_SI0_SITFRM0_TFRM_LOW_WIDTH (32U) 1018 #define NETC_F3_SI0_SITFRM0_TFRM_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITFRM0_TFRM_LOW_SHIFT)) & NETC_F3_SI0_SITFRM0_TFRM_LOW_MASK) 1019 /*! @} */ 1020 1021 /*! @name SITFRM1 - Station interface transmit frame counter (aFrameTransmittedOK) 1 */ 1022 /*! @{ */ 1023 1024 #define NETC_F3_SI0_SITFRM1_TFRM_HIGH_MASK (0xFFFFFFFFU) 1025 #define NETC_F3_SI0_SITFRM1_TFRM_HIGH_SHIFT (0U) 1026 #define NETC_F3_SI0_SITFRM1_TFRM_HIGH_WIDTH (32U) 1027 #define NETC_F3_SI0_SITFRM1_TFRM_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITFRM1_TFRM_HIGH_SHIFT)) & NETC_F3_SI0_SITFRM1_TFRM_HIGH_MASK) 1028 /*! @} */ 1029 1030 /*! @name SITUCA0 - Station interface transmit unicast frame counter (ifOutUcastPkts) 0 */ 1031 /*! @{ */ 1032 1033 #define NETC_F3_SI0_SITUCA0_TUCA_LOW_MASK (0xFFFFFFFFU) 1034 #define NETC_F3_SI0_SITUCA0_TUCA_LOW_SHIFT (0U) 1035 #define NETC_F3_SI0_SITUCA0_TUCA_LOW_WIDTH (32U) 1036 #define NETC_F3_SI0_SITUCA0_TUCA_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITUCA0_TUCA_LOW_SHIFT)) & NETC_F3_SI0_SITUCA0_TUCA_LOW_MASK) 1037 /*! @} */ 1038 1039 /*! @name SITUCA1 - Station interface transmit unicast frame counter (ifOutUcastPkts) 1 */ 1040 /*! @{ */ 1041 1042 #define NETC_F3_SI0_SITUCA1_TUCA_HIGH_MASK (0xFFFFFFFFU) 1043 #define NETC_F3_SI0_SITUCA1_TUCA_HIGH_SHIFT (0U) 1044 #define NETC_F3_SI0_SITUCA1_TUCA_HIGH_WIDTH (32U) 1045 #define NETC_F3_SI0_SITUCA1_TUCA_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITUCA1_TUCA_HIGH_SHIFT)) & NETC_F3_SI0_SITUCA1_TUCA_HIGH_MASK) 1046 /*! @} */ 1047 1048 /*! @name SITMCA0 - Station interface transmit multicast frame counter (ifOutMulticastPkts) 0 */ 1049 /*! @{ */ 1050 1051 #define NETC_F3_SI0_SITMCA0_TMCA_LOW_MASK (0xFFFFFFFFU) 1052 #define NETC_F3_SI0_SITMCA0_TMCA_LOW_SHIFT (0U) 1053 #define NETC_F3_SI0_SITMCA0_TMCA_LOW_WIDTH (32U) 1054 #define NETC_F3_SI0_SITMCA0_TMCA_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITMCA0_TMCA_LOW_SHIFT)) & NETC_F3_SI0_SITMCA0_TMCA_LOW_MASK) 1055 /*! @} */ 1056 1057 /*! @name SITMCA1 - Station interface transmit multicast frame counter (ifOutMulticastPkts) 1 */ 1058 /*! @{ */ 1059 1060 #define NETC_F3_SI0_SITMCA1_TMCA_HIGH_MASK (0xFFFFFFFFU) 1061 #define NETC_F3_SI0_SITMCA1_TMCA_HIGH_SHIFT (0U) 1062 #define NETC_F3_SI0_SITMCA1_TMCA_HIGH_WIDTH (32U) 1063 #define NETC_F3_SI0_SITMCA1_TMCA_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITMCA1_TMCA_HIGH_SHIFT)) & NETC_F3_SI0_SITMCA1_TMCA_HIGH_MASK) 1064 /*! @} */ 1065 1066 /*! @name SICBDRMR - Station interface command BDR mode register */ 1067 /*! @{ */ 1068 1069 #define NETC_F3_SI0_SICBDRMR_EN_MASK (0x80000000U) 1070 #define NETC_F3_SI0_SICBDRMR_EN_SHIFT (31U) 1071 #define NETC_F3_SI0_SICBDRMR_EN_WIDTH (1U) 1072 #define NETC_F3_SI0_SICBDRMR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICBDRMR_EN_SHIFT)) & NETC_F3_SI0_SICBDRMR_EN_MASK) 1073 /*! @} */ 1074 1075 /*! @name SICBDRSR - Station interface command BDR status register */ 1076 /*! @{ */ 1077 1078 #define NETC_F3_SI0_SICBDRSR_BUSY_MASK (0x1U) 1079 #define NETC_F3_SI0_SICBDRSR_BUSY_SHIFT (0U) 1080 #define NETC_F3_SI0_SICBDRSR_BUSY_WIDTH (1U) 1081 #define NETC_F3_SI0_SICBDRSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICBDRSR_BUSY_SHIFT)) & NETC_F3_SI0_SICBDRSR_BUSY_MASK) 1082 /*! @} */ 1083 1084 /*! @name SICBDRBAR0 - Station interface command BDR base address register 0 */ 1085 /*! @{ */ 1086 1087 #define NETC_F3_SI0_SICBDRBAR0_ADDRL_MASK (0xFFFFFF80U) 1088 #define NETC_F3_SI0_SICBDRBAR0_ADDRL_SHIFT (7U) 1089 #define NETC_F3_SI0_SICBDRBAR0_ADDRL_WIDTH (25U) 1090 #define NETC_F3_SI0_SICBDRBAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICBDRBAR0_ADDRL_SHIFT)) & NETC_F3_SI0_SICBDRBAR0_ADDRL_MASK) 1091 /*! @} */ 1092 1093 /*! @name SICBDRBAR1 - Station interface command BDR base address register 1 */ 1094 /*! @{ */ 1095 1096 #define NETC_F3_SI0_SICBDRBAR1_ADDRH_MASK (0xFFFFFFFFU) 1097 #define NETC_F3_SI0_SICBDRBAR1_ADDRH_SHIFT (0U) 1098 #define NETC_F3_SI0_SICBDRBAR1_ADDRH_WIDTH (32U) 1099 #define NETC_F3_SI0_SICBDRBAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICBDRBAR1_ADDRH_SHIFT)) & NETC_F3_SI0_SICBDRBAR1_ADDRH_MASK) 1100 /*! @} */ 1101 1102 /*! @name SICBDRPIR - Station interface command BDR producer index register */ 1103 /*! @{ */ 1104 1105 #define NETC_F3_SI0_SICBDRPIR_BDR_INDEX_MASK (0x3FFU) 1106 #define NETC_F3_SI0_SICBDRPIR_BDR_INDEX_SHIFT (0U) 1107 #define NETC_F3_SI0_SICBDRPIR_BDR_INDEX_WIDTH (10U) 1108 #define NETC_F3_SI0_SICBDRPIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICBDRPIR_BDR_INDEX_SHIFT)) & NETC_F3_SI0_SICBDRPIR_BDR_INDEX_MASK) 1109 /*! @} */ 1110 1111 /*! @name SICBDRCIR - Station interface command BDR consumer index register */ 1112 /*! @{ */ 1113 1114 #define NETC_F3_SI0_SICBDRCIR_BDR_INDEX_MASK (0x3FFU) 1115 #define NETC_F3_SI0_SICBDRCIR_BDR_INDEX_SHIFT (0U) 1116 #define NETC_F3_SI0_SICBDRCIR_BDR_INDEX_WIDTH (10U) 1117 #define NETC_F3_SI0_SICBDRCIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICBDRCIR_BDR_INDEX_SHIFT)) & NETC_F3_SI0_SICBDRCIR_BDR_INDEX_MASK) 1118 /*! @} */ 1119 1120 /*! @name SICBDRLENR - Station interface command BDR length register */ 1121 /*! @{ */ 1122 1123 #define NETC_F3_SI0_SICBDRLENR_LENGTH_MASK (0x7F8U) 1124 #define NETC_F3_SI0_SICBDRLENR_LENGTH_SHIFT (3U) 1125 #define NETC_F3_SI0_SICBDRLENR_LENGTH_WIDTH (8U) 1126 #define NETC_F3_SI0_SICBDRLENR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICBDRLENR_LENGTH_SHIFT)) & NETC_F3_SI0_SICBDRLENR_LENGTH_MASK) 1127 /*! @} */ 1128 1129 /*! @name SICBDRIER - Station interface command BDR interrupt enable register */ 1130 /*! @{ */ 1131 1132 #define NETC_F3_SI0_SICBDRIER_CBDCIE_MASK (0x1U) 1133 #define NETC_F3_SI0_SICBDRIER_CBDCIE_SHIFT (0U) 1134 #define NETC_F3_SI0_SICBDRIER_CBDCIE_WIDTH (1U) 1135 #define NETC_F3_SI0_SICBDRIER_CBDCIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICBDRIER_CBDCIE_SHIFT)) & NETC_F3_SI0_SICBDRIER_CBDCIE_MASK) 1136 /*! @} */ 1137 1138 /*! @name SICBDRIDR - Station interface command BDR interrupt detect register */ 1139 /*! @{ */ 1140 1141 #define NETC_F3_SI0_SICBDRIDR_CBDC_MASK (0x1U) 1142 #define NETC_F3_SI0_SICBDRIDR_CBDC_SHIFT (0U) 1143 #define NETC_F3_SI0_SICBDRIDR_CBDC_WIDTH (1U) 1144 #define NETC_F3_SI0_SICBDRIDR_CBDC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICBDRIDR_CBDC_SHIFT)) & NETC_F3_SI0_SICBDRIDR_CBDC_MASK) 1145 /*! @} */ 1146 1147 /*! @name SICAPR0 - Station interface capability register 0 */ 1148 /*! @{ */ 1149 1150 #define NETC_F3_SI0_SICAPR0_NUM_TX_BDR_MASK (0xFFU) 1151 #define NETC_F3_SI0_SICAPR0_NUM_TX_BDR_SHIFT (0U) 1152 #define NETC_F3_SI0_SICAPR0_NUM_TX_BDR_WIDTH (8U) 1153 #define NETC_F3_SI0_SICAPR0_NUM_TX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICAPR0_NUM_TX_BDR_SHIFT)) & NETC_F3_SI0_SICAPR0_NUM_TX_BDR_MASK) 1154 1155 #define NETC_F3_SI0_SICAPR0_NUM_RX_BDR_MASK (0xFF0000U) 1156 #define NETC_F3_SI0_SICAPR0_NUM_RX_BDR_SHIFT (16U) 1157 #define NETC_F3_SI0_SICAPR0_NUM_RX_BDR_WIDTH (8U) 1158 #define NETC_F3_SI0_SICAPR0_NUM_RX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICAPR0_NUM_RX_BDR_SHIFT)) & NETC_F3_SI0_SICAPR0_NUM_RX_BDR_MASK) 1159 1160 #define NETC_F3_SI0_SICAPR0_NUM_MAC_ADDR_MASK (0xF0000000U) 1161 #define NETC_F3_SI0_SICAPR0_NUM_MAC_ADDR_SHIFT (28U) 1162 #define NETC_F3_SI0_SICAPR0_NUM_MAC_ADDR_WIDTH (4U) 1163 #define NETC_F3_SI0_SICAPR0_NUM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICAPR0_NUM_MAC_ADDR_SHIFT)) & NETC_F3_SI0_SICAPR0_NUM_MAC_ADDR_MASK) 1164 /*! @} */ 1165 1166 /*! @name SICAPR1 - Station interface capability register 1 */ 1167 /*! @{ */ 1168 1169 #define NETC_F3_SI0_SICAPR1_NUM_RX_GRP_MASK (0xFF0000U) 1170 #define NETC_F3_SI0_SICAPR1_NUM_RX_GRP_SHIFT (16U) 1171 #define NETC_F3_SI0_SICAPR1_NUM_RX_GRP_WIDTH (8U) 1172 #define NETC_F3_SI0_SICAPR1_NUM_RX_GRP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICAPR1_NUM_RX_GRP_SHIFT)) & NETC_F3_SI0_SICAPR1_NUM_RX_GRP_MASK) 1173 /*! @} */ 1174 1175 /*! @name SICAPR2 - Station interface capability register 2 */ 1176 /*! @{ */ 1177 1178 #define NETC_F3_SI0_SICAPR2_VTP_MASK (0xFU) 1179 #define NETC_F3_SI0_SICAPR2_VTP_SHIFT (0U) 1180 #define NETC_F3_SI0_SICAPR2_VTP_WIDTH (4U) 1181 #define NETC_F3_SI0_SICAPR2_VTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICAPR2_VTP_SHIFT)) & NETC_F3_SI0_SICAPR2_VTP_MASK) 1182 /*! @} */ 1183 1184 /*! @name PSIIER - Physical station interface interrupt enable register */ 1185 /*! @{ */ 1186 1187 #define NETC_F3_SI0_PSIIER_MR1IE_MASK (0x2U) 1188 #define NETC_F3_SI0_PSIIER_MR1IE_SHIFT (1U) 1189 #define NETC_F3_SI0_PSIIER_MR1IE_WIDTH (1U) 1190 #define NETC_F3_SI0_PSIIER_MR1IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_MR1IE_SHIFT)) & NETC_F3_SI0_PSIIER_MR1IE_MASK) 1191 1192 #define NETC_F3_SI0_PSIIER_MR2IE_MASK (0x4U) 1193 #define NETC_F3_SI0_PSIIER_MR2IE_SHIFT (2U) 1194 #define NETC_F3_SI0_PSIIER_MR2IE_WIDTH (1U) 1195 #define NETC_F3_SI0_PSIIER_MR2IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_MR2IE_SHIFT)) & NETC_F3_SI0_PSIIER_MR2IE_MASK) 1196 1197 #define NETC_F3_SI0_PSIIER_MR3IE_MASK (0x8U) 1198 #define NETC_F3_SI0_PSIIER_MR3IE_SHIFT (3U) 1199 #define NETC_F3_SI0_PSIIER_MR3IE_WIDTH (1U) 1200 #define NETC_F3_SI0_PSIIER_MR3IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_MR3IE_SHIFT)) & NETC_F3_SI0_PSIIER_MR3IE_MASK) 1201 1202 #define NETC_F3_SI0_PSIIER_MR4IE_MASK (0x10U) 1203 #define NETC_F3_SI0_PSIIER_MR4IE_SHIFT (4U) 1204 #define NETC_F3_SI0_PSIIER_MR4IE_WIDTH (1U) 1205 #define NETC_F3_SI0_PSIIER_MR4IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_MR4IE_SHIFT)) & NETC_F3_SI0_PSIIER_MR4IE_MASK) 1206 1207 #define NETC_F3_SI0_PSIIER_MR5IE_MASK (0x20U) 1208 #define NETC_F3_SI0_PSIIER_MR5IE_SHIFT (5U) 1209 #define NETC_F3_SI0_PSIIER_MR5IE_WIDTH (1U) 1210 #define NETC_F3_SI0_PSIIER_MR5IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_MR5IE_SHIFT)) & NETC_F3_SI0_PSIIER_MR5IE_MASK) 1211 1212 #define NETC_F3_SI0_PSIIER_MR6IE_MASK (0x40U) 1213 #define NETC_F3_SI0_PSIIER_MR6IE_SHIFT (6U) 1214 #define NETC_F3_SI0_PSIIER_MR6IE_WIDTH (1U) 1215 #define NETC_F3_SI0_PSIIER_MR6IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_MR6IE_SHIFT)) & NETC_F3_SI0_PSIIER_MR6IE_MASK) 1216 1217 #define NETC_F3_SI0_PSIIER_MR7IE_MASK (0x80U) 1218 #define NETC_F3_SI0_PSIIER_MR7IE_SHIFT (7U) 1219 #define NETC_F3_SI0_PSIIER_MR7IE_WIDTH (1U) 1220 #define NETC_F3_SI0_PSIIER_MR7IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_MR7IE_SHIFT)) & NETC_F3_SI0_PSIIER_MR7IE_MASK) 1221 1222 #define NETC_F3_SI0_PSIIER_FLR1IE_MASK (0x20000U) 1223 #define NETC_F3_SI0_PSIIER_FLR1IE_SHIFT (17U) 1224 #define NETC_F3_SI0_PSIIER_FLR1IE_WIDTH (1U) 1225 #define NETC_F3_SI0_PSIIER_FLR1IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_FLR1IE_SHIFT)) & NETC_F3_SI0_PSIIER_FLR1IE_MASK) 1226 1227 #define NETC_F3_SI0_PSIIER_FLR2IE_MASK (0x40000U) 1228 #define NETC_F3_SI0_PSIIER_FLR2IE_SHIFT (18U) 1229 #define NETC_F3_SI0_PSIIER_FLR2IE_WIDTH (1U) 1230 #define NETC_F3_SI0_PSIIER_FLR2IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_FLR2IE_SHIFT)) & NETC_F3_SI0_PSIIER_FLR2IE_MASK) 1231 1232 #define NETC_F3_SI0_PSIIER_FLR3IE_MASK (0x80000U) 1233 #define NETC_F3_SI0_PSIIER_FLR3IE_SHIFT (19U) 1234 #define NETC_F3_SI0_PSIIER_FLR3IE_WIDTH (1U) 1235 #define NETC_F3_SI0_PSIIER_FLR3IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_FLR3IE_SHIFT)) & NETC_F3_SI0_PSIIER_FLR3IE_MASK) 1236 1237 #define NETC_F3_SI0_PSIIER_FLR4IE_MASK (0x100000U) 1238 #define NETC_F3_SI0_PSIIER_FLR4IE_SHIFT (20U) 1239 #define NETC_F3_SI0_PSIIER_FLR4IE_WIDTH (1U) 1240 #define NETC_F3_SI0_PSIIER_FLR4IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_FLR4IE_SHIFT)) & NETC_F3_SI0_PSIIER_FLR4IE_MASK) 1241 1242 #define NETC_F3_SI0_PSIIER_FLR5IE_MASK (0x200000U) 1243 #define NETC_F3_SI0_PSIIER_FLR5IE_SHIFT (21U) 1244 #define NETC_F3_SI0_PSIIER_FLR5IE_WIDTH (1U) 1245 #define NETC_F3_SI0_PSIIER_FLR5IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_FLR5IE_SHIFT)) & NETC_F3_SI0_PSIIER_FLR5IE_MASK) 1246 1247 #define NETC_F3_SI0_PSIIER_FLR6IE_MASK (0x400000U) 1248 #define NETC_F3_SI0_PSIIER_FLR6IE_SHIFT (22U) 1249 #define NETC_F3_SI0_PSIIER_FLR6IE_WIDTH (1U) 1250 #define NETC_F3_SI0_PSIIER_FLR6IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_FLR6IE_SHIFT)) & NETC_F3_SI0_PSIIER_FLR6IE_MASK) 1251 1252 #define NETC_F3_SI0_PSIIER_FLR7IE_MASK (0x800000U) 1253 #define NETC_F3_SI0_PSIIER_FLR7IE_SHIFT (23U) 1254 #define NETC_F3_SI0_PSIIER_FLR7IE_WIDTH (1U) 1255 #define NETC_F3_SI0_PSIIER_FLR7IE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIER_FLR7IE_SHIFT)) & NETC_F3_SI0_PSIIER_FLR7IE_MASK) 1256 /*! @} */ 1257 1258 /*! @name PSIIDR - Physical station interface interrupt detect register */ 1259 /*! @{ */ 1260 1261 #define NETC_F3_SI0_PSIIDR_TXR_MASK (0x1U) 1262 #define NETC_F3_SI0_PSIIDR_TXR_SHIFT (0U) 1263 #define NETC_F3_SI0_PSIIDR_TXR_WIDTH (1U) 1264 #define NETC_F3_SI0_PSIIDR_TXR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_TXR_SHIFT)) & NETC_F3_SI0_PSIIDR_TXR_MASK) 1265 1266 #define NETC_F3_SI0_PSIIDR_MR1_MASK (0x2U) 1267 #define NETC_F3_SI0_PSIIDR_MR1_SHIFT (1U) 1268 #define NETC_F3_SI0_PSIIDR_MR1_WIDTH (1U) 1269 #define NETC_F3_SI0_PSIIDR_MR1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_MR1_SHIFT)) & NETC_F3_SI0_PSIIDR_MR1_MASK) 1270 1271 #define NETC_F3_SI0_PSIIDR_MR2_MASK (0x4U) 1272 #define NETC_F3_SI0_PSIIDR_MR2_SHIFT (2U) 1273 #define NETC_F3_SI0_PSIIDR_MR2_WIDTH (1U) 1274 #define NETC_F3_SI0_PSIIDR_MR2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_MR2_SHIFT)) & NETC_F3_SI0_PSIIDR_MR2_MASK) 1275 1276 #define NETC_F3_SI0_PSIIDR_MR3_MASK (0x8U) 1277 #define NETC_F3_SI0_PSIIDR_MR3_SHIFT (3U) 1278 #define NETC_F3_SI0_PSIIDR_MR3_WIDTH (1U) 1279 #define NETC_F3_SI0_PSIIDR_MR3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_MR3_SHIFT)) & NETC_F3_SI0_PSIIDR_MR3_MASK) 1280 1281 #define NETC_F3_SI0_PSIIDR_MR4_MASK (0x10U) 1282 #define NETC_F3_SI0_PSIIDR_MR4_SHIFT (4U) 1283 #define NETC_F3_SI0_PSIIDR_MR4_WIDTH (1U) 1284 #define NETC_F3_SI0_PSIIDR_MR4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_MR4_SHIFT)) & NETC_F3_SI0_PSIIDR_MR4_MASK) 1285 1286 #define NETC_F3_SI0_PSIIDR_MR5_MASK (0x20U) 1287 #define NETC_F3_SI0_PSIIDR_MR5_SHIFT (5U) 1288 #define NETC_F3_SI0_PSIIDR_MR5_WIDTH (1U) 1289 #define NETC_F3_SI0_PSIIDR_MR5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_MR5_SHIFT)) & NETC_F3_SI0_PSIIDR_MR5_MASK) 1290 1291 #define NETC_F3_SI0_PSIIDR_MR6_MASK (0x40U) 1292 #define NETC_F3_SI0_PSIIDR_MR6_SHIFT (6U) 1293 #define NETC_F3_SI0_PSIIDR_MR6_WIDTH (1U) 1294 #define NETC_F3_SI0_PSIIDR_MR6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_MR6_SHIFT)) & NETC_F3_SI0_PSIIDR_MR6_MASK) 1295 1296 #define NETC_F3_SI0_PSIIDR_MR7_MASK (0x80U) 1297 #define NETC_F3_SI0_PSIIDR_MR7_SHIFT (7U) 1298 #define NETC_F3_SI0_PSIIDR_MR7_WIDTH (1U) 1299 #define NETC_F3_SI0_PSIIDR_MR7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_MR7_SHIFT)) & NETC_F3_SI0_PSIIDR_MR7_MASK) 1300 1301 #define NETC_F3_SI0_PSIIDR_RXR_MASK (0x10000U) 1302 #define NETC_F3_SI0_PSIIDR_RXR_SHIFT (16U) 1303 #define NETC_F3_SI0_PSIIDR_RXR_WIDTH (1U) 1304 #define NETC_F3_SI0_PSIIDR_RXR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_RXR_SHIFT)) & NETC_F3_SI0_PSIIDR_RXR_MASK) 1305 1306 #define NETC_F3_SI0_PSIIDR_FLR1_MASK (0x20000U) 1307 #define NETC_F3_SI0_PSIIDR_FLR1_SHIFT (17U) 1308 #define NETC_F3_SI0_PSIIDR_FLR1_WIDTH (1U) 1309 #define NETC_F3_SI0_PSIIDR_FLR1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_FLR1_SHIFT)) & NETC_F3_SI0_PSIIDR_FLR1_MASK) 1310 1311 #define NETC_F3_SI0_PSIIDR_FLR2_MASK (0x40000U) 1312 #define NETC_F3_SI0_PSIIDR_FLR2_SHIFT (18U) 1313 #define NETC_F3_SI0_PSIIDR_FLR2_WIDTH (1U) 1314 #define NETC_F3_SI0_PSIIDR_FLR2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_FLR2_SHIFT)) & NETC_F3_SI0_PSIIDR_FLR2_MASK) 1315 1316 #define NETC_F3_SI0_PSIIDR_FLR3_MASK (0x80000U) 1317 #define NETC_F3_SI0_PSIIDR_FLR3_SHIFT (19U) 1318 #define NETC_F3_SI0_PSIIDR_FLR3_WIDTH (1U) 1319 #define NETC_F3_SI0_PSIIDR_FLR3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_FLR3_SHIFT)) & NETC_F3_SI0_PSIIDR_FLR3_MASK) 1320 1321 #define NETC_F3_SI0_PSIIDR_FLR4_MASK (0x100000U) 1322 #define NETC_F3_SI0_PSIIDR_FLR4_SHIFT (20U) 1323 #define NETC_F3_SI0_PSIIDR_FLR4_WIDTH (1U) 1324 #define NETC_F3_SI0_PSIIDR_FLR4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_FLR4_SHIFT)) & NETC_F3_SI0_PSIIDR_FLR4_MASK) 1325 1326 #define NETC_F3_SI0_PSIIDR_FLR5_MASK (0x200000U) 1327 #define NETC_F3_SI0_PSIIDR_FLR5_SHIFT (21U) 1328 #define NETC_F3_SI0_PSIIDR_FLR5_WIDTH (1U) 1329 #define NETC_F3_SI0_PSIIDR_FLR5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_FLR5_SHIFT)) & NETC_F3_SI0_PSIIDR_FLR5_MASK) 1330 1331 #define NETC_F3_SI0_PSIIDR_FLR6_MASK (0x400000U) 1332 #define NETC_F3_SI0_PSIIDR_FLR6_SHIFT (22U) 1333 #define NETC_F3_SI0_PSIIDR_FLR6_WIDTH (1U) 1334 #define NETC_F3_SI0_PSIIDR_FLR6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_FLR6_SHIFT)) & NETC_F3_SI0_PSIIDR_FLR6_MASK) 1335 1336 #define NETC_F3_SI0_PSIIDR_FLR7_MASK (0x800000U) 1337 #define NETC_F3_SI0_PSIIDR_FLR7_SHIFT (23U) 1338 #define NETC_F3_SI0_PSIIDR_FLR7_WIDTH (1U) 1339 #define NETC_F3_SI0_PSIIDR_FLR7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_PSIIDR_FLR7_SHIFT)) & NETC_F3_SI0_PSIIDR_FLR7_MASK) 1340 /*! @} */ 1341 1342 /*! @name SITXIDR0 - Station interface transmit interrupt detect register 0 */ 1343 /*! @{ */ 1344 1345 #define NETC_F3_SI0_SITXIDR0_TXT0_MASK (0x1U) 1346 #define NETC_F3_SI0_SITXIDR0_TXT0_SHIFT (0U) 1347 #define NETC_F3_SI0_SITXIDR0_TXT0_WIDTH (1U) 1348 #define NETC_F3_SI0_SITXIDR0_TXT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT0_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT0_MASK) 1349 1350 #define NETC_F3_SI0_SITXIDR0_TXT1_MASK (0x2U) 1351 #define NETC_F3_SI0_SITXIDR0_TXT1_SHIFT (1U) 1352 #define NETC_F3_SI0_SITXIDR0_TXT1_WIDTH (1U) 1353 #define NETC_F3_SI0_SITXIDR0_TXT1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT1_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT1_MASK) 1354 1355 #define NETC_F3_SI0_SITXIDR0_TXT2_MASK (0x4U) 1356 #define NETC_F3_SI0_SITXIDR0_TXT2_SHIFT (2U) 1357 #define NETC_F3_SI0_SITXIDR0_TXT2_WIDTH (1U) 1358 #define NETC_F3_SI0_SITXIDR0_TXT2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT2_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT2_MASK) 1359 1360 #define NETC_F3_SI0_SITXIDR0_TXT3_MASK (0x8U) 1361 #define NETC_F3_SI0_SITXIDR0_TXT3_SHIFT (3U) 1362 #define NETC_F3_SI0_SITXIDR0_TXT3_WIDTH (1U) 1363 #define NETC_F3_SI0_SITXIDR0_TXT3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT3_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT3_MASK) 1364 1365 #define NETC_F3_SI0_SITXIDR0_TXT4_MASK (0x10U) 1366 #define NETC_F3_SI0_SITXIDR0_TXT4_SHIFT (4U) 1367 #define NETC_F3_SI0_SITXIDR0_TXT4_WIDTH (1U) 1368 #define NETC_F3_SI0_SITXIDR0_TXT4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT4_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT4_MASK) 1369 1370 #define NETC_F3_SI0_SITXIDR0_TXT5_MASK (0x20U) 1371 #define NETC_F3_SI0_SITXIDR0_TXT5_SHIFT (5U) 1372 #define NETC_F3_SI0_SITXIDR0_TXT5_WIDTH (1U) 1373 #define NETC_F3_SI0_SITXIDR0_TXT5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT5_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT5_MASK) 1374 1375 #define NETC_F3_SI0_SITXIDR0_TXT6_MASK (0x40U) 1376 #define NETC_F3_SI0_SITXIDR0_TXT6_SHIFT (6U) 1377 #define NETC_F3_SI0_SITXIDR0_TXT6_WIDTH (1U) 1378 #define NETC_F3_SI0_SITXIDR0_TXT6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT6_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT6_MASK) 1379 1380 #define NETC_F3_SI0_SITXIDR0_TXT7_MASK (0x80U) 1381 #define NETC_F3_SI0_SITXIDR0_TXT7_SHIFT (7U) 1382 #define NETC_F3_SI0_SITXIDR0_TXT7_WIDTH (1U) 1383 #define NETC_F3_SI0_SITXIDR0_TXT7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT7_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT7_MASK) 1384 1385 #define NETC_F3_SI0_SITXIDR0_TXT8_MASK (0x100U) 1386 #define NETC_F3_SI0_SITXIDR0_TXT8_SHIFT (8U) 1387 #define NETC_F3_SI0_SITXIDR0_TXT8_WIDTH (1U) 1388 #define NETC_F3_SI0_SITXIDR0_TXT8(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT8_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT8_MASK) 1389 1390 #define NETC_F3_SI0_SITXIDR0_TXT9_MASK (0x200U) 1391 #define NETC_F3_SI0_SITXIDR0_TXT9_SHIFT (9U) 1392 #define NETC_F3_SI0_SITXIDR0_TXT9_WIDTH (1U) 1393 #define NETC_F3_SI0_SITXIDR0_TXT9(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT9_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT9_MASK) 1394 1395 #define NETC_F3_SI0_SITXIDR0_TXT10_MASK (0x400U) 1396 #define NETC_F3_SI0_SITXIDR0_TXT10_SHIFT (10U) 1397 #define NETC_F3_SI0_SITXIDR0_TXT10_WIDTH (1U) 1398 #define NETC_F3_SI0_SITXIDR0_TXT10(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT10_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT10_MASK) 1399 1400 #define NETC_F3_SI0_SITXIDR0_TXT11_MASK (0x800U) 1401 #define NETC_F3_SI0_SITXIDR0_TXT11_SHIFT (11U) 1402 #define NETC_F3_SI0_SITXIDR0_TXT11_WIDTH (1U) 1403 #define NETC_F3_SI0_SITXIDR0_TXT11(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT11_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT11_MASK) 1404 1405 #define NETC_F3_SI0_SITXIDR0_TXT12_MASK (0x1000U) 1406 #define NETC_F3_SI0_SITXIDR0_TXT12_SHIFT (12U) 1407 #define NETC_F3_SI0_SITXIDR0_TXT12_WIDTH (1U) 1408 #define NETC_F3_SI0_SITXIDR0_TXT12(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT12_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT12_MASK) 1409 1410 #define NETC_F3_SI0_SITXIDR0_TXT13_MASK (0x2000U) 1411 #define NETC_F3_SI0_SITXIDR0_TXT13_SHIFT (13U) 1412 #define NETC_F3_SI0_SITXIDR0_TXT13_WIDTH (1U) 1413 #define NETC_F3_SI0_SITXIDR0_TXT13(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT13_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT13_MASK) 1414 1415 #define NETC_F3_SI0_SITXIDR0_TXT14_MASK (0x4000U) 1416 #define NETC_F3_SI0_SITXIDR0_TXT14_SHIFT (14U) 1417 #define NETC_F3_SI0_SITXIDR0_TXT14_WIDTH (1U) 1418 #define NETC_F3_SI0_SITXIDR0_TXT14(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT14_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT14_MASK) 1419 1420 #define NETC_F3_SI0_SITXIDR0_TXT15_MASK (0x8000U) 1421 #define NETC_F3_SI0_SITXIDR0_TXT15_SHIFT (15U) 1422 #define NETC_F3_SI0_SITXIDR0_TXT15_WIDTH (1U) 1423 #define NETC_F3_SI0_SITXIDR0_TXT15(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXT15_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXT15_MASK) 1424 1425 #define NETC_F3_SI0_SITXIDR0_TXF0_MASK (0x10000U) 1426 #define NETC_F3_SI0_SITXIDR0_TXF0_SHIFT (16U) 1427 #define NETC_F3_SI0_SITXIDR0_TXF0_WIDTH (1U) 1428 #define NETC_F3_SI0_SITXIDR0_TXF0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF0_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF0_MASK) 1429 1430 #define NETC_F3_SI0_SITXIDR0_TXF1_MASK (0x20000U) 1431 #define NETC_F3_SI0_SITXIDR0_TXF1_SHIFT (17U) 1432 #define NETC_F3_SI0_SITXIDR0_TXF1_WIDTH (1U) 1433 #define NETC_F3_SI0_SITXIDR0_TXF1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF1_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF1_MASK) 1434 1435 #define NETC_F3_SI0_SITXIDR0_TXF2_MASK (0x40000U) 1436 #define NETC_F3_SI0_SITXIDR0_TXF2_SHIFT (18U) 1437 #define NETC_F3_SI0_SITXIDR0_TXF2_WIDTH (1U) 1438 #define NETC_F3_SI0_SITXIDR0_TXF2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF2_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF2_MASK) 1439 1440 #define NETC_F3_SI0_SITXIDR0_TXF3_MASK (0x80000U) 1441 #define NETC_F3_SI0_SITXIDR0_TXF3_SHIFT (19U) 1442 #define NETC_F3_SI0_SITXIDR0_TXF3_WIDTH (1U) 1443 #define NETC_F3_SI0_SITXIDR0_TXF3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF3_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF3_MASK) 1444 1445 #define NETC_F3_SI0_SITXIDR0_TXF4_MASK (0x100000U) 1446 #define NETC_F3_SI0_SITXIDR0_TXF4_SHIFT (20U) 1447 #define NETC_F3_SI0_SITXIDR0_TXF4_WIDTH (1U) 1448 #define NETC_F3_SI0_SITXIDR0_TXF4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF4_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF4_MASK) 1449 1450 #define NETC_F3_SI0_SITXIDR0_TXF5_MASK (0x200000U) 1451 #define NETC_F3_SI0_SITXIDR0_TXF5_SHIFT (21U) 1452 #define NETC_F3_SI0_SITXIDR0_TXF5_WIDTH (1U) 1453 #define NETC_F3_SI0_SITXIDR0_TXF5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF5_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF5_MASK) 1454 1455 #define NETC_F3_SI0_SITXIDR0_TXF6_MASK (0x400000U) 1456 #define NETC_F3_SI0_SITXIDR0_TXF6_SHIFT (22U) 1457 #define NETC_F3_SI0_SITXIDR0_TXF6_WIDTH (1U) 1458 #define NETC_F3_SI0_SITXIDR0_TXF6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF6_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF6_MASK) 1459 1460 #define NETC_F3_SI0_SITXIDR0_TXF7_MASK (0x800000U) 1461 #define NETC_F3_SI0_SITXIDR0_TXF7_SHIFT (23U) 1462 #define NETC_F3_SI0_SITXIDR0_TXF7_WIDTH (1U) 1463 #define NETC_F3_SI0_SITXIDR0_TXF7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF7_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF7_MASK) 1464 1465 #define NETC_F3_SI0_SITXIDR0_TXF8_MASK (0x1000000U) 1466 #define NETC_F3_SI0_SITXIDR0_TXF8_SHIFT (24U) 1467 #define NETC_F3_SI0_SITXIDR0_TXF8_WIDTH (1U) 1468 #define NETC_F3_SI0_SITXIDR0_TXF8(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF8_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF8_MASK) 1469 1470 #define NETC_F3_SI0_SITXIDR0_TXF9_MASK (0x2000000U) 1471 #define NETC_F3_SI0_SITXIDR0_TXF9_SHIFT (25U) 1472 #define NETC_F3_SI0_SITXIDR0_TXF9_WIDTH (1U) 1473 #define NETC_F3_SI0_SITXIDR0_TXF9(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF9_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF9_MASK) 1474 1475 #define NETC_F3_SI0_SITXIDR0_TXF10_MASK (0x4000000U) 1476 #define NETC_F3_SI0_SITXIDR0_TXF10_SHIFT (26U) 1477 #define NETC_F3_SI0_SITXIDR0_TXF10_WIDTH (1U) 1478 #define NETC_F3_SI0_SITXIDR0_TXF10(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF10_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF10_MASK) 1479 1480 #define NETC_F3_SI0_SITXIDR0_TXF11_MASK (0x8000000U) 1481 #define NETC_F3_SI0_SITXIDR0_TXF11_SHIFT (27U) 1482 #define NETC_F3_SI0_SITXIDR0_TXF11_WIDTH (1U) 1483 #define NETC_F3_SI0_SITXIDR0_TXF11(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF11_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF11_MASK) 1484 1485 #define NETC_F3_SI0_SITXIDR0_TXF12_MASK (0x10000000U) 1486 #define NETC_F3_SI0_SITXIDR0_TXF12_SHIFT (28U) 1487 #define NETC_F3_SI0_SITXIDR0_TXF12_WIDTH (1U) 1488 #define NETC_F3_SI0_SITXIDR0_TXF12(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF12_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF12_MASK) 1489 1490 #define NETC_F3_SI0_SITXIDR0_TXF13_MASK (0x20000000U) 1491 #define NETC_F3_SI0_SITXIDR0_TXF13_SHIFT (29U) 1492 #define NETC_F3_SI0_SITXIDR0_TXF13_WIDTH (1U) 1493 #define NETC_F3_SI0_SITXIDR0_TXF13(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF13_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF13_MASK) 1494 1495 #define NETC_F3_SI0_SITXIDR0_TXF14_MASK (0x40000000U) 1496 #define NETC_F3_SI0_SITXIDR0_TXF14_SHIFT (30U) 1497 #define NETC_F3_SI0_SITXIDR0_TXF14_WIDTH (1U) 1498 #define NETC_F3_SI0_SITXIDR0_TXF14(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF14_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF14_MASK) 1499 1500 #define NETC_F3_SI0_SITXIDR0_TXF15_MASK (0x80000000U) 1501 #define NETC_F3_SI0_SITXIDR0_TXF15_SHIFT (31U) 1502 #define NETC_F3_SI0_SITXIDR0_TXF15_WIDTH (1U) 1503 #define NETC_F3_SI0_SITXIDR0_TXF15(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR0_TXF15_SHIFT)) & NETC_F3_SI0_SITXIDR0_TXF15_MASK) 1504 /*! @} */ 1505 1506 /*! @name SITXIDR1 - Station interface transmit interrupt detect register 1 */ 1507 /*! @{ */ 1508 1509 #define NETC_F3_SI0_SITXIDR1_TXT16_MASK (0x1U) 1510 #define NETC_F3_SI0_SITXIDR1_TXT16_SHIFT (0U) 1511 #define NETC_F3_SI0_SITXIDR1_TXT16_WIDTH (1U) 1512 #define NETC_F3_SI0_SITXIDR1_TXT16(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR1_TXT16_SHIFT)) & NETC_F3_SI0_SITXIDR1_TXT16_MASK) 1513 1514 #define NETC_F3_SI0_SITXIDR1_TXT17_MASK (0x2U) 1515 #define NETC_F3_SI0_SITXIDR1_TXT17_SHIFT (1U) 1516 #define NETC_F3_SI0_SITXIDR1_TXT17_WIDTH (1U) 1517 #define NETC_F3_SI0_SITXIDR1_TXT17(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR1_TXT17_SHIFT)) & NETC_F3_SI0_SITXIDR1_TXT17_MASK) 1518 1519 #define NETC_F3_SI0_SITXIDR1_TXF16_MASK (0x10000U) 1520 #define NETC_F3_SI0_SITXIDR1_TXF16_SHIFT (16U) 1521 #define NETC_F3_SI0_SITXIDR1_TXF16_WIDTH (1U) 1522 #define NETC_F3_SI0_SITXIDR1_TXF16(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR1_TXF16_SHIFT)) & NETC_F3_SI0_SITXIDR1_TXF16_MASK) 1523 1524 #define NETC_F3_SI0_SITXIDR1_TXF17_MASK (0x20000U) 1525 #define NETC_F3_SI0_SITXIDR1_TXF17_SHIFT (17U) 1526 #define NETC_F3_SI0_SITXIDR1_TXF17_WIDTH (1U) 1527 #define NETC_F3_SI0_SITXIDR1_TXF17(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITXIDR1_TXF17_SHIFT)) & NETC_F3_SI0_SITXIDR1_TXF17_MASK) 1528 /*! @} */ 1529 1530 /*! @name SIRXIDR0 - Station interface receive interrupt detect register 0 */ 1531 /*! @{ */ 1532 1533 #define NETC_F3_SI0_SIRXIDR0_RX0_MASK (0x1U) 1534 #define NETC_F3_SI0_SIRXIDR0_RX0_SHIFT (0U) 1535 #define NETC_F3_SI0_SIRXIDR0_RX0_WIDTH (1U) 1536 #define NETC_F3_SI0_SIRXIDR0_RX0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX0_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX0_MASK) 1537 1538 #define NETC_F3_SI0_SIRXIDR0_RX1_MASK (0x2U) 1539 #define NETC_F3_SI0_SIRXIDR0_RX1_SHIFT (1U) 1540 #define NETC_F3_SI0_SIRXIDR0_RX1_WIDTH (1U) 1541 #define NETC_F3_SI0_SIRXIDR0_RX1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX1_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX1_MASK) 1542 1543 #define NETC_F3_SI0_SIRXIDR0_RX2_MASK (0x4U) 1544 #define NETC_F3_SI0_SIRXIDR0_RX2_SHIFT (2U) 1545 #define NETC_F3_SI0_SIRXIDR0_RX2_WIDTH (1U) 1546 #define NETC_F3_SI0_SIRXIDR0_RX2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX2_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX2_MASK) 1547 1548 #define NETC_F3_SI0_SIRXIDR0_RX3_MASK (0x8U) 1549 #define NETC_F3_SI0_SIRXIDR0_RX3_SHIFT (3U) 1550 #define NETC_F3_SI0_SIRXIDR0_RX3_WIDTH (1U) 1551 #define NETC_F3_SI0_SIRXIDR0_RX3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX3_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX3_MASK) 1552 1553 #define NETC_F3_SI0_SIRXIDR0_RX4_MASK (0x10U) 1554 #define NETC_F3_SI0_SIRXIDR0_RX4_SHIFT (4U) 1555 #define NETC_F3_SI0_SIRXIDR0_RX4_WIDTH (1U) 1556 #define NETC_F3_SI0_SIRXIDR0_RX4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX4_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX4_MASK) 1557 1558 #define NETC_F3_SI0_SIRXIDR0_RX5_MASK (0x20U) 1559 #define NETC_F3_SI0_SIRXIDR0_RX5_SHIFT (5U) 1560 #define NETC_F3_SI0_SIRXIDR0_RX5_WIDTH (1U) 1561 #define NETC_F3_SI0_SIRXIDR0_RX5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX5_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX5_MASK) 1562 1563 #define NETC_F3_SI0_SIRXIDR0_RX6_MASK (0x40U) 1564 #define NETC_F3_SI0_SIRXIDR0_RX6_SHIFT (6U) 1565 #define NETC_F3_SI0_SIRXIDR0_RX6_WIDTH (1U) 1566 #define NETC_F3_SI0_SIRXIDR0_RX6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX6_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX6_MASK) 1567 1568 #define NETC_F3_SI0_SIRXIDR0_RX7_MASK (0x80U) 1569 #define NETC_F3_SI0_SIRXIDR0_RX7_SHIFT (7U) 1570 #define NETC_F3_SI0_SIRXIDR0_RX7_WIDTH (1U) 1571 #define NETC_F3_SI0_SIRXIDR0_RX7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX7_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX7_MASK) 1572 1573 #define NETC_F3_SI0_SIRXIDR0_RX8_MASK (0x100U) 1574 #define NETC_F3_SI0_SIRXIDR0_RX8_SHIFT (8U) 1575 #define NETC_F3_SI0_SIRXIDR0_RX8_WIDTH (1U) 1576 #define NETC_F3_SI0_SIRXIDR0_RX8(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX8_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX8_MASK) 1577 1578 #define NETC_F3_SI0_SIRXIDR0_RX9_MASK (0x200U) 1579 #define NETC_F3_SI0_SIRXIDR0_RX9_SHIFT (9U) 1580 #define NETC_F3_SI0_SIRXIDR0_RX9_WIDTH (1U) 1581 #define NETC_F3_SI0_SIRXIDR0_RX9(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX9_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX9_MASK) 1582 1583 #define NETC_F3_SI0_SIRXIDR0_RX10_MASK (0x400U) 1584 #define NETC_F3_SI0_SIRXIDR0_RX10_SHIFT (10U) 1585 #define NETC_F3_SI0_SIRXIDR0_RX10_WIDTH (1U) 1586 #define NETC_F3_SI0_SIRXIDR0_RX10(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX10_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX10_MASK) 1587 1588 #define NETC_F3_SI0_SIRXIDR0_RX11_MASK (0x800U) 1589 #define NETC_F3_SI0_SIRXIDR0_RX11_SHIFT (11U) 1590 #define NETC_F3_SI0_SIRXIDR0_RX11_WIDTH (1U) 1591 #define NETC_F3_SI0_SIRXIDR0_RX11(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX11_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX11_MASK) 1592 1593 #define NETC_F3_SI0_SIRXIDR0_RX12_MASK (0x1000U) 1594 #define NETC_F3_SI0_SIRXIDR0_RX12_SHIFT (12U) 1595 #define NETC_F3_SI0_SIRXIDR0_RX12_WIDTH (1U) 1596 #define NETC_F3_SI0_SIRXIDR0_RX12(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX12_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX12_MASK) 1597 1598 #define NETC_F3_SI0_SIRXIDR0_RX13_MASK (0x2000U) 1599 #define NETC_F3_SI0_SIRXIDR0_RX13_SHIFT (13U) 1600 #define NETC_F3_SI0_SIRXIDR0_RX13_WIDTH (1U) 1601 #define NETC_F3_SI0_SIRXIDR0_RX13(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX13_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX13_MASK) 1602 1603 #define NETC_F3_SI0_SIRXIDR0_RX14_MASK (0x4000U) 1604 #define NETC_F3_SI0_SIRXIDR0_RX14_SHIFT (14U) 1605 #define NETC_F3_SI0_SIRXIDR0_RX14_WIDTH (1U) 1606 #define NETC_F3_SI0_SIRXIDR0_RX14(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX14_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX14_MASK) 1607 1608 #define NETC_F3_SI0_SIRXIDR0_RX15_MASK (0x8000U) 1609 #define NETC_F3_SI0_SIRXIDR0_RX15_SHIFT (15U) 1610 #define NETC_F3_SI0_SIRXIDR0_RX15_WIDTH (1U) 1611 #define NETC_F3_SI0_SIRXIDR0_RX15(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR0_RX15_SHIFT)) & NETC_F3_SI0_SIRXIDR0_RX15_MASK) 1612 /*! @} */ 1613 1614 /*! @name SIRXIDR1 - Station interface receive interrupt detect register 1 */ 1615 /*! @{ */ 1616 1617 #define NETC_F3_SI0_SIRXIDR1_RX16_MASK (0x1U) 1618 #define NETC_F3_SI0_SIRXIDR1_RX16_SHIFT (0U) 1619 #define NETC_F3_SI0_SIRXIDR1_RX16_WIDTH (1U) 1620 #define NETC_F3_SI0_SIRXIDR1_RX16(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR1_RX16_SHIFT)) & NETC_F3_SI0_SIRXIDR1_RX16_MASK) 1621 1622 #define NETC_F3_SI0_SIRXIDR1_RX17_MASK (0x2U) 1623 #define NETC_F3_SI0_SIRXIDR1_RX17_SHIFT (1U) 1624 #define NETC_F3_SI0_SIRXIDR1_RX17_WIDTH (1U) 1625 #define NETC_F3_SI0_SIRXIDR1_RX17(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRXIDR1_RX17_SHIFT)) & NETC_F3_SI0_SIRXIDR1_RX17_MASK) 1626 /*! @} */ 1627 1628 /*! @name SIMSIVR - Station interface MSI-X vector register */ 1629 /*! @{ */ 1630 1631 #define NETC_F3_SI0_SIMSIVR_VECTOR_MASK (0x3FU) 1632 #define NETC_F3_SI0_SIMSIVR_VECTOR_SHIFT (0U) 1633 #define NETC_F3_SI0_SIMSIVR_VECTOR_WIDTH (6U) 1634 #define NETC_F3_SI0_SIMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMSIVR_VECTOR_SHIFT)) & NETC_F3_SI0_SIMSIVR_VECTOR_MASK) 1635 /*! @} */ 1636 1637 /*! @name SICMSIVR - Station interface command MSI-X vector register */ 1638 /*! @{ */ 1639 1640 #define NETC_F3_SI0_SICMSIVR_VECTOR_MASK (0x3FU) 1641 #define NETC_F3_SI0_SICMSIVR_VECTOR_SHIFT (0U) 1642 #define NETC_F3_SI0_SICMSIVR_VECTOR_WIDTH (6U) 1643 #define NETC_F3_SI0_SICMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICMSIVR_VECTOR_SHIFT)) & NETC_F3_SI0_SICMSIVR_VECTOR_MASK) 1644 /*! @} */ 1645 1646 /*! @name SITMRIER - Station interface timer interrupt enable register */ 1647 /*! @{ */ 1648 1649 #define NETC_F3_SI0_SITMRIER_SYNCE_MASK (0x1U) 1650 #define NETC_F3_SI0_SITMRIER_SYNCE_SHIFT (0U) 1651 #define NETC_F3_SI0_SITMRIER_SYNCE_WIDTH (1U) 1652 #define NETC_F3_SI0_SITMRIER_SYNCE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITMRIER_SYNCE_SHIFT)) & NETC_F3_SI0_SITMRIER_SYNCE_MASK) 1653 /*! @} */ 1654 1655 /*! @name SITMRIDR - Station interface timer interrupt detect register */ 1656 /*! @{ */ 1657 1658 #define NETC_F3_SI0_SITMRIDR_SYNC_MASK (0x1U) 1659 #define NETC_F3_SI0_SITMRIDR_SYNC_SHIFT (0U) 1660 #define NETC_F3_SI0_SITMRIDR_SYNC_WIDTH (1U) 1661 #define NETC_F3_SI0_SITMRIDR_SYNC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITMRIDR_SYNC_SHIFT)) & NETC_F3_SI0_SITMRIDR_SYNC_MASK) 1662 /*! @} */ 1663 1664 /*! @name SITMRMSIVR - Station interface timer MSI-X vector register */ 1665 /*! @{ */ 1666 1667 #define NETC_F3_SI0_SITMRMSIVR_VECTOR_MASK (0x3FU) 1668 #define NETC_F3_SI0_SITMRMSIVR_VECTOR_SHIFT (0U) 1669 #define NETC_F3_SI0_SITMRMSIVR_VECTOR_WIDTH (6U) 1670 #define NETC_F3_SI0_SITMRMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SITMRMSIVR_VECTOR_SHIFT)) & NETC_F3_SI0_SITMRMSIVR_VECTOR_MASK) 1671 /*! @} */ 1672 1673 /*! @name SIMSITRVR - Station interface MSI-X transmit ring 0 vector register..Station interface MSI-X transmit ring 17 vector register */ 1674 /*! @{ */ 1675 1676 #define NETC_F3_SI0_SIMSITRVR_VECTOR_MASK (0x3FU) 1677 #define NETC_F3_SI0_SIMSITRVR_VECTOR_SHIFT (0U) 1678 #define NETC_F3_SI0_SIMSITRVR_VECTOR_WIDTH (6U) 1679 #define NETC_F3_SI0_SIMSITRVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMSITRVR_VECTOR_SHIFT)) & NETC_F3_SI0_SIMSITRVR_VECTOR_MASK) 1680 /*! @} */ 1681 1682 /*! @name SIMSIRRVR - Station interface MSI-X receive ring 0 vector register..Station interface MSI-X receive ring 17 vector register */ 1683 /*! @{ */ 1684 1685 #define NETC_F3_SI0_SIMSIRRVR_VECTOR_MASK (0x3FU) 1686 #define NETC_F3_SI0_SIMSIRRVR_VECTOR_SHIFT (0U) 1687 #define NETC_F3_SI0_SIMSIRRVR_VECTOR_WIDTH (6U) 1688 #define NETC_F3_SI0_SIMSIRRVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMSIRRVR_VECTOR_SHIFT)) & NETC_F3_SI0_SIMSIRRVR_VECTOR_MASK) 1689 /*! @} */ 1690 1691 /*! @name SICMECR - Station interface correctable memory error configuration register */ 1692 /*! @{ */ 1693 1694 #define NETC_F3_SI0_SICMECR_THRESHOLD_MASK (0xFFU) 1695 #define NETC_F3_SI0_SICMECR_THRESHOLD_SHIFT (0U) 1696 #define NETC_F3_SI0_SICMECR_THRESHOLD_WIDTH (8U) 1697 #define NETC_F3_SI0_SICMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICMECR_THRESHOLD_SHIFT)) & NETC_F3_SI0_SICMECR_THRESHOLD_MASK) 1698 /*! @} */ 1699 1700 /*! @name SICMESR - Station interface correctable memory error status register */ 1701 /*! @{ */ 1702 1703 #define NETC_F3_SI0_SICMESR_MEM_ID_MASK (0x1F0000U) 1704 #define NETC_F3_SI0_SICMESR_MEM_ID_SHIFT (16U) 1705 #define NETC_F3_SI0_SICMESR_MEM_ID_WIDTH (5U) 1706 #define NETC_F3_SI0_SICMESR_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICMESR_MEM_ID_SHIFT)) & NETC_F3_SI0_SICMESR_MEM_ID_MASK) 1707 1708 #define NETC_F3_SI0_SICMESR_SBEE_MASK (0x80000000U) 1709 #define NETC_F3_SI0_SICMESR_SBEE_SHIFT (31U) 1710 #define NETC_F3_SI0_SICMESR_SBEE_WIDTH (1U) 1711 #define NETC_F3_SI0_SICMESR_SBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICMESR_SBEE_SHIFT)) & NETC_F3_SI0_SICMESR_SBEE_MASK) 1712 /*! @} */ 1713 1714 /*! @name SICMECTR - Station interface correctable memory error count register */ 1715 /*! @{ */ 1716 1717 #define NETC_F3_SI0_SICMECTR_COUNT_MASK (0xFFU) 1718 #define NETC_F3_SI0_SICMECTR_COUNT_SHIFT (0U) 1719 #define NETC_F3_SI0_SICMECTR_COUNT_WIDTH (8U) 1720 #define NETC_F3_SI0_SICMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SICMECTR_COUNT_SHIFT)) & NETC_F3_SI0_SICMECTR_COUNT_MASK) 1721 /*! @} */ 1722 1723 /*! @name SIUPECR - Station interface uncorrectable programming error configuration register */ 1724 /*! @{ */ 1725 1726 #define NETC_F3_SI0_SIUPECR_RD_MASK (0x80000000U) 1727 #define NETC_F3_SI0_SIUPECR_RD_SHIFT (31U) 1728 #define NETC_F3_SI0_SIUPECR_RD_WIDTH (1U) 1729 #define NETC_F3_SI0_SIUPECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUPECR_RD_SHIFT)) & NETC_F3_SI0_SIUPECR_RD_MASK) 1730 /*! @} */ 1731 1732 /*! @name SIUPESR - Station interface uncorrectable programming error status register */ 1733 /*! @{ */ 1734 1735 #define NETC_F3_SI0_SIUPESR_DROP_SI_EN_MASK (0x1U) 1736 #define NETC_F3_SI0_SIUPESR_DROP_SI_EN_SHIFT (0U) 1737 #define NETC_F3_SI0_SIUPESR_DROP_SI_EN_WIDTH (1U) 1738 #define NETC_F3_SI0_SIUPESR_DROP_SI_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUPESR_DROP_SI_EN_SHIFT)) & NETC_F3_SI0_SIUPESR_DROP_SI_EN_MASK) 1739 1740 #define NETC_F3_SI0_SIUPESR_DROP_RING_EN_MASK (0x2U) 1741 #define NETC_F3_SI0_SIUPESR_DROP_RING_EN_SHIFT (1U) 1742 #define NETC_F3_SI0_SIUPESR_DROP_RING_EN_WIDTH (1U) 1743 #define NETC_F3_SI0_SIUPESR_DROP_RING_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUPESR_DROP_RING_EN_SHIFT)) & NETC_F3_SI0_SIUPESR_DROP_RING_EN_MASK) 1744 1745 #define NETC_F3_SI0_SIUPESR_DROP_GRP_SEL_MASK (0x4U) 1746 #define NETC_F3_SI0_SIUPESR_DROP_GRP_SEL_SHIFT (2U) 1747 #define NETC_F3_SI0_SIUPESR_DROP_GRP_SEL_WIDTH (1U) 1748 #define NETC_F3_SI0_SIUPESR_DROP_GRP_SEL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUPESR_DROP_GRP_SEL_SHIFT)) & NETC_F3_SI0_SIUPESR_DROP_GRP_SEL_MASK) 1749 1750 #define NETC_F3_SI0_SIUPESR_DROP_RING_SEL_MASK (0x8U) 1751 #define NETC_F3_SI0_SIUPESR_DROP_RING_SEL_SHIFT (3U) 1752 #define NETC_F3_SI0_SIUPESR_DROP_RING_SEL_WIDTH (1U) 1753 #define NETC_F3_SI0_SIUPESR_DROP_RING_SEL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUPESR_DROP_RING_SEL_SHIFT)) & NETC_F3_SI0_SIUPESR_DROP_RING_SEL_MASK) 1754 1755 #define NETC_F3_SI0_SIUPESR_M_MASK (0x40000000U) 1756 #define NETC_F3_SI0_SIUPESR_M_SHIFT (30U) 1757 #define NETC_F3_SI0_SIUPESR_M_WIDTH (1U) 1758 #define NETC_F3_SI0_SIUPESR_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUPESR_M_SHIFT)) & NETC_F3_SI0_SIUPESR_M_MASK) 1759 1760 #define NETC_F3_SI0_SIUPESR_PE_MASK (0x80000000U) 1761 #define NETC_F3_SI0_SIUPESR_PE_SHIFT (31U) 1762 #define NETC_F3_SI0_SIUPESR_PE_WIDTH (1U) 1763 #define NETC_F3_SI0_SIUPESR_PE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUPESR_PE_SHIFT)) & NETC_F3_SI0_SIUPESR_PE_MASK) 1764 /*! @} */ 1765 1766 /*! @name SIUPECTR - Station interface uncorrectable programming error count register */ 1767 /*! @{ */ 1768 1769 #define NETC_F3_SI0_SIUPECTR_COUNT_MASK (0xFFFFFFFFU) 1770 #define NETC_F3_SI0_SIUPECTR_COUNT_SHIFT (0U) 1771 #define NETC_F3_SI0_SIUPECTR_COUNT_WIDTH (32U) 1772 #define NETC_F3_SI0_SIUPECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUPECTR_COUNT_SHIFT)) & NETC_F3_SI0_SIUPECTR_COUNT_MASK) 1773 /*! @} */ 1774 1775 /*! @name SIUNSBECR - Station interface uncorrectable non-fatal system bus error configuration register */ 1776 /*! @{ */ 1777 1778 #define NETC_F3_SI0_SIUNSBECR_THRESHOLD_MASK (0xFFU) 1779 #define NETC_F3_SI0_SIUNSBECR_THRESHOLD_SHIFT (0U) 1780 #define NETC_F3_SI0_SIUNSBECR_THRESHOLD_WIDTH (8U) 1781 #define NETC_F3_SI0_SIUNSBECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNSBECR_THRESHOLD_SHIFT)) & NETC_F3_SI0_SIUNSBECR_THRESHOLD_MASK) 1782 /*! @} */ 1783 1784 /*! @name SIUNSBESR - Station interface uncorrectable non-fatal system bus error status register */ 1785 /*! @{ */ 1786 1787 #define NETC_F3_SI0_SIUNSBESR_SB_ID_MASK (0xFU) 1788 #define NETC_F3_SI0_SIUNSBESR_SB_ID_SHIFT (0U) 1789 #define NETC_F3_SI0_SIUNSBESR_SB_ID_WIDTH (4U) 1790 #define NETC_F3_SI0_SIUNSBESR_SB_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNSBESR_SB_ID_SHIFT)) & NETC_F3_SI0_SIUNSBESR_SB_ID_MASK) 1791 1792 #define NETC_F3_SI0_SIUNSBESR_SBE_MASK (0x80000000U) 1793 #define NETC_F3_SI0_SIUNSBESR_SBE_SHIFT (31U) 1794 #define NETC_F3_SI0_SIUNSBESR_SBE_WIDTH (1U) 1795 #define NETC_F3_SI0_SIUNSBESR_SBE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNSBESR_SBE_SHIFT)) & NETC_F3_SI0_SIUNSBESR_SBE_MASK) 1796 /*! @} */ 1797 1798 /*! @name SIUNSBECTR - Station interface uncorrectable non-fatal system bus error count register */ 1799 /*! @{ */ 1800 1801 #define NETC_F3_SI0_SIUNSBECTR_COUNT_MASK (0xFFU) 1802 #define NETC_F3_SI0_SIUNSBECTR_COUNT_SHIFT (0U) 1803 #define NETC_F3_SI0_SIUNSBECTR_COUNT_WIDTH (8U) 1804 #define NETC_F3_SI0_SIUNSBECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNSBECTR_COUNT_SHIFT)) & NETC_F3_SI0_SIUNSBECTR_COUNT_MASK) 1805 /*! @} */ 1806 1807 /*! @name SIUFSBECR - Station interface uncorrectable fatal system bus error configuration register */ 1808 /*! @{ */ 1809 1810 #define NETC_F3_SI0_SIUFSBECR_RD_MASK (0x80000000U) 1811 #define NETC_F3_SI0_SIUFSBECR_RD_SHIFT (31U) 1812 #define NETC_F3_SI0_SIUFSBECR_RD_WIDTH (1U) 1813 #define NETC_F3_SI0_SIUFSBECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFSBECR_RD_SHIFT)) & NETC_F3_SI0_SIUFSBECR_RD_MASK) 1814 /*! @} */ 1815 1816 /*! @name SIUFSBESR - Station interface uncorrectable fatal system bus error status register */ 1817 /*! @{ */ 1818 1819 #define NETC_F3_SI0_SIUFSBESR_SB_ID_MASK (0xFU) 1820 #define NETC_F3_SI0_SIUFSBESR_SB_ID_SHIFT (0U) 1821 #define NETC_F3_SI0_SIUFSBESR_SB_ID_WIDTH (4U) 1822 #define NETC_F3_SI0_SIUFSBESR_SB_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFSBESR_SB_ID_SHIFT)) & NETC_F3_SI0_SIUFSBESR_SB_ID_MASK) 1823 1824 #define NETC_F3_SI0_SIUFSBESR_M_MASK (0x40000000U) 1825 #define NETC_F3_SI0_SIUFSBESR_M_SHIFT (30U) 1826 #define NETC_F3_SI0_SIUFSBESR_M_WIDTH (1U) 1827 #define NETC_F3_SI0_SIUFSBESR_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFSBESR_M_SHIFT)) & NETC_F3_SI0_SIUFSBESR_M_MASK) 1828 1829 #define NETC_F3_SI0_SIUFSBESR_SBE_MASK (0x80000000U) 1830 #define NETC_F3_SI0_SIUFSBESR_SBE_SHIFT (31U) 1831 #define NETC_F3_SI0_SIUFSBESR_SBE_WIDTH (1U) 1832 #define NETC_F3_SI0_SIUFSBESR_SBE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFSBESR_SBE_SHIFT)) & NETC_F3_SI0_SIUFSBESR_SBE_MASK) 1833 /*! @} */ 1834 1835 /*! @name SIUNMECR - Station interface uncorrectable non-fatal memory error configuration register */ 1836 /*! @{ */ 1837 1838 #define NETC_F3_SI0_SIUNMECR_THRESHOLD_MASK (0xFFU) 1839 #define NETC_F3_SI0_SIUNMECR_THRESHOLD_SHIFT (0U) 1840 #define NETC_F3_SI0_SIUNMECR_THRESHOLD_WIDTH (8U) 1841 #define NETC_F3_SI0_SIUNMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNMECR_THRESHOLD_SHIFT)) & NETC_F3_SI0_SIUNMECR_THRESHOLD_MASK) 1842 1843 #define NETC_F3_SI0_SIUNMECR_RD_MASK (0x80000000U) 1844 #define NETC_F3_SI0_SIUNMECR_RD_SHIFT (31U) 1845 #define NETC_F3_SI0_SIUNMECR_RD_WIDTH (1U) 1846 #define NETC_F3_SI0_SIUNMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNMECR_RD_SHIFT)) & NETC_F3_SI0_SIUNMECR_RD_MASK) 1847 /*! @} */ 1848 1849 /*! @name SIUNMESR0 - Station interface uncorrectable non-fatal memory error status register 0 */ 1850 /*! @{ */ 1851 1852 #define NETC_F3_SI0_SIUNMESR0_SYNDROME_MASK (0x7FFU) 1853 #define NETC_F3_SI0_SIUNMESR0_SYNDROME_SHIFT (0U) 1854 #define NETC_F3_SI0_SIUNMESR0_SYNDROME_WIDTH (11U) 1855 #define NETC_F3_SI0_SIUNMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNMESR0_SYNDROME_SHIFT)) & NETC_F3_SI0_SIUNMESR0_SYNDROME_MASK) 1856 1857 #define NETC_F3_SI0_SIUNMESR0_MEM_ID_MASK (0x1F0000U) 1858 #define NETC_F3_SI0_SIUNMESR0_MEM_ID_SHIFT (16U) 1859 #define NETC_F3_SI0_SIUNMESR0_MEM_ID_WIDTH (5U) 1860 #define NETC_F3_SI0_SIUNMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNMESR0_MEM_ID_SHIFT)) & NETC_F3_SI0_SIUNMESR0_MEM_ID_MASK) 1861 1862 #define NETC_F3_SI0_SIUNMESR0_MBEE_MASK (0x80000000U) 1863 #define NETC_F3_SI0_SIUNMESR0_MBEE_SHIFT (31U) 1864 #define NETC_F3_SI0_SIUNMESR0_MBEE_WIDTH (1U) 1865 #define NETC_F3_SI0_SIUNMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNMESR0_MBEE_SHIFT)) & NETC_F3_SI0_SIUNMESR0_MBEE_MASK) 1866 /*! @} */ 1867 1868 /*! @name SIUNMESR1 - Station interface uncorrectable non-fatal memory error status register 1 */ 1869 /*! @{ */ 1870 1871 #define NETC_F3_SI0_SIUNMESR1_ADDR_MASK (0xFFFFFFFFU) 1872 #define NETC_F3_SI0_SIUNMESR1_ADDR_SHIFT (0U) 1873 #define NETC_F3_SI0_SIUNMESR1_ADDR_WIDTH (32U) 1874 #define NETC_F3_SI0_SIUNMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNMESR1_ADDR_SHIFT)) & NETC_F3_SI0_SIUNMESR1_ADDR_MASK) 1875 /*! @} */ 1876 1877 /*! @name SIUNMECTR - Station interface uncorrectable non-fatal memory error count register */ 1878 /*! @{ */ 1879 1880 #define NETC_F3_SI0_SIUNMECTR_COUNT_MASK (0xFFU) 1881 #define NETC_F3_SI0_SIUNMECTR_COUNT_SHIFT (0U) 1882 #define NETC_F3_SI0_SIUNMECTR_COUNT_WIDTH (8U) 1883 #define NETC_F3_SI0_SIUNMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNMECTR_COUNT_SHIFT)) & NETC_F3_SI0_SIUNMECTR_COUNT_MASK) 1884 /*! @} */ 1885 1886 /*! @name SIUFMECR - Station interface uncorrectable fatal memory error configuration register */ 1887 /*! @{ */ 1888 1889 #define NETC_F3_SI0_SIUFMECR_RD_MASK (0x80000000U) 1890 #define NETC_F3_SI0_SIUFMECR_RD_SHIFT (31U) 1891 #define NETC_F3_SI0_SIUFMECR_RD_WIDTH (1U) 1892 #define NETC_F3_SI0_SIUFMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFMECR_RD_SHIFT)) & NETC_F3_SI0_SIUFMECR_RD_MASK) 1893 /*! @} */ 1894 1895 /*! @name SIUFMESR0 - Station interface uncorrectable fatal memory error status register 0 */ 1896 /*! @{ */ 1897 1898 #define NETC_F3_SI0_SIUFMESR0_SYNDROME_MASK (0x7FFU) 1899 #define NETC_F3_SI0_SIUFMESR0_SYNDROME_SHIFT (0U) 1900 #define NETC_F3_SI0_SIUFMESR0_SYNDROME_WIDTH (11U) 1901 #define NETC_F3_SI0_SIUFMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFMESR0_SYNDROME_SHIFT)) & NETC_F3_SI0_SIUFMESR0_SYNDROME_MASK) 1902 1903 #define NETC_F3_SI0_SIUFMESR0_MEM_ID_MASK (0x1F0000U) 1904 #define NETC_F3_SI0_SIUFMESR0_MEM_ID_SHIFT (16U) 1905 #define NETC_F3_SI0_SIUFMESR0_MEM_ID_WIDTH (5U) 1906 #define NETC_F3_SI0_SIUFMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFMESR0_MEM_ID_SHIFT)) & NETC_F3_SI0_SIUFMESR0_MEM_ID_MASK) 1907 1908 #define NETC_F3_SI0_SIUFMESR0_M_MASK (0x40000000U) 1909 #define NETC_F3_SI0_SIUFMESR0_M_SHIFT (30U) 1910 #define NETC_F3_SI0_SIUFMESR0_M_WIDTH (1U) 1911 #define NETC_F3_SI0_SIUFMESR0_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFMESR0_M_SHIFT)) & NETC_F3_SI0_SIUFMESR0_M_MASK) 1912 1913 #define NETC_F3_SI0_SIUFMESR0_MBEE_MASK (0x80000000U) 1914 #define NETC_F3_SI0_SIUFMESR0_MBEE_SHIFT (31U) 1915 #define NETC_F3_SI0_SIUFMESR0_MBEE_WIDTH (1U) 1916 #define NETC_F3_SI0_SIUFMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFMESR0_MBEE_SHIFT)) & NETC_F3_SI0_SIUFMESR0_MBEE_MASK) 1917 /*! @} */ 1918 1919 /*! @name SIUFMESR1 - Station interface uncorrectable fatal memory error status register 1 */ 1920 /*! @{ */ 1921 1922 #define NETC_F3_SI0_SIUFMESR1_ADDR_MASK (0xFFFFFFFFU) 1923 #define NETC_F3_SI0_SIUFMESR1_ADDR_SHIFT (0U) 1924 #define NETC_F3_SI0_SIUFMESR1_ADDR_WIDTH (32U) 1925 #define NETC_F3_SI0_SIUFMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFMESR1_ADDR_SHIFT)) & NETC_F3_SI0_SIUFMESR1_ADDR_MASK) 1926 /*! @} */ 1927 1928 /*! @name SIUNIECR - Station interface uncorrectable non-fatal integrity error configuration register */ 1929 /*! @{ */ 1930 1931 #define NETC_F3_SI0_SIUNIECR_THRESHOLD_MASK (0xFFU) 1932 #define NETC_F3_SI0_SIUNIECR_THRESHOLD_SHIFT (0U) 1933 #define NETC_F3_SI0_SIUNIECR_THRESHOLD_WIDTH (8U) 1934 #define NETC_F3_SI0_SIUNIECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNIECR_THRESHOLD_SHIFT)) & NETC_F3_SI0_SIUNIECR_THRESHOLD_MASK) 1935 1936 #define NETC_F3_SI0_SIUNIECR_RD_MASK (0x80000000U) 1937 #define NETC_F3_SI0_SIUNIECR_RD_SHIFT (31U) 1938 #define NETC_F3_SI0_SIUNIECR_RD_WIDTH (1U) 1939 #define NETC_F3_SI0_SIUNIECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNIECR_RD_SHIFT)) & NETC_F3_SI0_SIUNIECR_RD_MASK) 1940 /*! @} */ 1941 1942 /*! @name SIUNIESR - Station interface uncorrectable non-fatal integrity error status register */ 1943 /*! @{ */ 1944 1945 #define NETC_F3_SI0_SIUNIESR_BLOCK_ID_MASK (0xF0U) 1946 #define NETC_F3_SI0_SIUNIESR_BLOCK_ID_SHIFT (4U) 1947 #define NETC_F3_SI0_SIUNIESR_BLOCK_ID_WIDTH (4U) 1948 #define NETC_F3_SI0_SIUNIESR_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNIESR_BLOCK_ID_SHIFT)) & NETC_F3_SI0_SIUNIESR_BLOCK_ID_MASK) 1949 1950 #define NETC_F3_SI0_SIUNIESR_SM_ID_MASK (0x3F00U) 1951 #define NETC_F3_SI0_SIUNIESR_SM_ID_SHIFT (8U) 1952 #define NETC_F3_SI0_SIUNIESR_SM_ID_WIDTH (6U) 1953 #define NETC_F3_SI0_SIUNIESR_SM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNIESR_SM_ID_SHIFT)) & NETC_F3_SI0_SIUNIESR_SM_ID_MASK) 1954 1955 #define NETC_F3_SI0_SIUNIESR_INTERR_MASK (0x80000000U) 1956 #define NETC_F3_SI0_SIUNIESR_INTERR_SHIFT (31U) 1957 #define NETC_F3_SI0_SIUNIESR_INTERR_WIDTH (1U) 1958 #define NETC_F3_SI0_SIUNIESR_INTERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNIESR_INTERR_SHIFT)) & NETC_F3_SI0_SIUNIESR_INTERR_MASK) 1959 /*! @} */ 1960 1961 /*! @name SIUNIECTR - Station interface uncorrectable non-fatal integrity error count register */ 1962 /*! @{ */ 1963 1964 #define NETC_F3_SI0_SIUNIECTR_COUNT_MASK (0xFFU) 1965 #define NETC_F3_SI0_SIUNIECTR_COUNT_SHIFT (0U) 1966 #define NETC_F3_SI0_SIUNIECTR_COUNT_WIDTH (8U) 1967 #define NETC_F3_SI0_SIUNIECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUNIECTR_COUNT_SHIFT)) & NETC_F3_SI0_SIUNIECTR_COUNT_MASK) 1968 /*! @} */ 1969 1970 /*! @name SIUFIECR - Station interface uncorrectable fatal integrity error configuration register */ 1971 /*! @{ */ 1972 1973 #define NETC_F3_SI0_SIUFIECR_RD_MASK (0x80000000U) 1974 #define NETC_F3_SI0_SIUFIECR_RD_SHIFT (31U) 1975 #define NETC_F3_SI0_SIUFIECR_RD_WIDTH (1U) 1976 #define NETC_F3_SI0_SIUFIECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFIECR_RD_SHIFT)) & NETC_F3_SI0_SIUFIECR_RD_MASK) 1977 /*! @} */ 1978 1979 /*! @name SIUFIESR - Station interface uncorrectable fatal integrity error status register */ 1980 /*! @{ */ 1981 1982 #define NETC_F3_SI0_SIUFIESR_BLOCK_ID_MASK (0xF0U) 1983 #define NETC_F3_SI0_SIUFIESR_BLOCK_ID_SHIFT (4U) 1984 #define NETC_F3_SI0_SIUFIESR_BLOCK_ID_WIDTH (4U) 1985 #define NETC_F3_SI0_SIUFIESR_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFIESR_BLOCK_ID_SHIFT)) & NETC_F3_SI0_SIUFIESR_BLOCK_ID_MASK) 1986 1987 #define NETC_F3_SI0_SIUFIESR_SM_ID_MASK (0x3F00U) 1988 #define NETC_F3_SI0_SIUFIESR_SM_ID_SHIFT (8U) 1989 #define NETC_F3_SI0_SIUFIESR_SM_ID_WIDTH (6U) 1990 #define NETC_F3_SI0_SIUFIESR_SM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFIESR_SM_ID_SHIFT)) & NETC_F3_SI0_SIUFIESR_SM_ID_MASK) 1991 1992 #define NETC_F3_SI0_SIUFIESR_M_MASK (0x40000000U) 1993 #define NETC_F3_SI0_SIUFIESR_M_SHIFT (30U) 1994 #define NETC_F3_SI0_SIUFIESR_M_WIDTH (1U) 1995 #define NETC_F3_SI0_SIUFIESR_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFIESR_M_SHIFT)) & NETC_F3_SI0_SIUFIESR_M_MASK) 1996 1997 #define NETC_F3_SI0_SIUFIESR_INTERR_MASK (0x80000000U) 1998 #define NETC_F3_SI0_SIUFIESR_INTERR_SHIFT (31U) 1999 #define NETC_F3_SI0_SIUFIESR_INTERR_WIDTH (1U) 2000 #define NETC_F3_SI0_SIUFIESR_INTERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIUFIESR_INTERR_SHIFT)) & NETC_F3_SI0_SIUFIESR_INTERR_MASK) 2001 /*! @} */ 2002 2003 /*! @name SIMAFTCAPR - Station interface MAC address filter table capability register */ 2004 /*! @{ */ 2005 2006 #define NETC_F3_SI0_SIMAFTCAPR_NUM_MAC_AFTE_MASK (0xFFU) 2007 #define NETC_F3_SI0_SIMAFTCAPR_NUM_MAC_AFTE_SHIFT (0U) 2008 #define NETC_F3_SI0_SIMAFTCAPR_NUM_MAC_AFTE_WIDTH (8U) 2009 #define NETC_F3_SI0_SIMAFTCAPR_NUM_MAC_AFTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIMAFTCAPR_NUM_MAC_AFTE_SHIFT)) & NETC_F3_SI0_SIMAFTCAPR_NUM_MAC_AFTE_MASK) 2010 /*! @} */ 2011 2012 /*! @name SIVFTCAPR - Station interface VLAN filter table capability register */ 2013 /*! @{ */ 2014 2015 #define NETC_F3_SI0_SIVFTCAPR_NUM_VLAN_FTE_MASK (0xFFU) 2016 #define NETC_F3_SI0_SIVFTCAPR_NUM_VLAN_FTE_SHIFT (0U) 2017 #define NETC_F3_SI0_SIVFTCAPR_NUM_VLAN_FTE_WIDTH (8U) 2018 #define NETC_F3_SI0_SIVFTCAPR_NUM_VLAN_FTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIVFTCAPR_NUM_VLAN_FTE_SHIFT)) & NETC_F3_SI0_SIVFTCAPR_NUM_VLAN_FTE_MASK) 2019 /*! @} */ 2020 2021 /*! @name SIRFSCAPR - Station interface RFS capability register */ 2022 /*! @{ */ 2023 2024 #define NETC_F3_SI0_SIRFSCAPR_NUM_RFS_MASK (0x1FFU) 2025 #define NETC_F3_SI0_SIRFSCAPR_NUM_RFS_SHIFT (0U) 2026 #define NETC_F3_SI0_SIRFSCAPR_NUM_RFS_WIDTH (9U) 2027 #define NETC_F3_SI0_SIRFSCAPR_NUM_RFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_SIRFSCAPR_NUM_RFS_SHIFT)) & NETC_F3_SI0_SIRFSCAPR_NUM_RFS_MASK) 2028 /*! @} */ 2029 2030 /*! @name TBMR - Tx BDR 0 mode register..Tx BDR 17 mode register */ 2031 /*! @{ */ 2032 2033 #define NETC_F3_SI0_TBMR_PRIO_MASK (0x7U) 2034 #define NETC_F3_SI0_TBMR_PRIO_SHIFT (0U) 2035 #define NETC_F3_SI0_TBMR_PRIO_WIDTH (3U) 2036 #define NETC_F3_SI0_TBMR_PRIO(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBMR_PRIO_SHIFT)) & NETC_F3_SI0_TBMR_PRIO_MASK) 2037 2038 #define NETC_F3_SI0_TBMR_WRR_MASK (0x70U) 2039 #define NETC_F3_SI0_TBMR_WRR_SHIFT (4U) 2040 #define NETC_F3_SI0_TBMR_WRR_WIDTH (3U) 2041 #define NETC_F3_SI0_TBMR_WRR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBMR_WRR_SHIFT)) & NETC_F3_SI0_TBMR_WRR_MASK) 2042 2043 #define NETC_F3_SI0_TBMR_CRC_MASK (0x100U) 2044 #define NETC_F3_SI0_TBMR_CRC_SHIFT (8U) 2045 #define NETC_F3_SI0_TBMR_CRC_WIDTH (1U) 2046 #define NETC_F3_SI0_TBMR_CRC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBMR_CRC_SHIFT)) & NETC_F3_SI0_TBMR_CRC_MASK) 2047 2048 #define NETC_F3_SI0_TBMR_VIH_MASK (0x200U) 2049 #define NETC_F3_SI0_TBMR_VIH_SHIFT (9U) 2050 #define NETC_F3_SI0_TBMR_VIH_WIDTH (1U) 2051 #define NETC_F3_SI0_TBMR_VIH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBMR_VIH_SHIFT)) & NETC_F3_SI0_TBMR_VIH_MASK) 2052 2053 #define NETC_F3_SI0_TBMR_EN_MASK (0x80000000U) 2054 #define NETC_F3_SI0_TBMR_EN_SHIFT (31U) 2055 #define NETC_F3_SI0_TBMR_EN_WIDTH (1U) 2056 #define NETC_F3_SI0_TBMR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBMR_EN_SHIFT)) & NETC_F3_SI0_TBMR_EN_MASK) 2057 /*! @} */ 2058 2059 /*! @name TBSR - Tx BDR 0 status register..Tx BDR 17 status register */ 2060 /*! @{ */ 2061 2062 #define NETC_F3_SI0_TBSR_BUSY_MASK (0x1U) 2063 #define NETC_F3_SI0_TBSR_BUSY_SHIFT (0U) 2064 #define NETC_F3_SI0_TBSR_BUSY_WIDTH (1U) 2065 #define NETC_F3_SI0_TBSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBSR_BUSY_SHIFT)) & NETC_F3_SI0_TBSR_BUSY_MASK) 2066 2067 #define NETC_F3_SI0_TBSR_SBE_MASK (0x10000U) 2068 #define NETC_F3_SI0_TBSR_SBE_SHIFT (16U) 2069 #define NETC_F3_SI0_TBSR_SBE_WIDTH (1U) 2070 #define NETC_F3_SI0_TBSR_SBE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBSR_SBE_SHIFT)) & NETC_F3_SI0_TBSR_SBE_MASK) 2071 /*! @} */ 2072 2073 /*! @name TBBAR0 - Tx BDR 0 base address register 0..Tx BDR 17 base address register 0 */ 2074 /*! @{ */ 2075 2076 #define NETC_F3_SI0_TBBAR0_ADDRL_MASK (0xFFFFFF80U) 2077 #define NETC_F3_SI0_TBBAR0_ADDRL_SHIFT (7U) 2078 #define NETC_F3_SI0_TBBAR0_ADDRL_WIDTH (25U) 2079 #define NETC_F3_SI0_TBBAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBBAR0_ADDRL_SHIFT)) & NETC_F3_SI0_TBBAR0_ADDRL_MASK) 2080 /*! @} */ 2081 2082 /*! @name TBBAR1 - Tx BDR 0 base address register 1..Tx BDR 17 base address register 1 */ 2083 /*! @{ */ 2084 2085 #define NETC_F3_SI0_TBBAR1_ADDRH_MASK (0xFFFFFFFFU) 2086 #define NETC_F3_SI0_TBBAR1_ADDRH_SHIFT (0U) 2087 #define NETC_F3_SI0_TBBAR1_ADDRH_WIDTH (32U) 2088 #define NETC_F3_SI0_TBBAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBBAR1_ADDRH_SHIFT)) & NETC_F3_SI0_TBBAR1_ADDRH_MASK) 2089 /*! @} */ 2090 2091 /*! @name TBPIR - Tx BDR 0 producer index register..Tx BDR 17 producer index register */ 2092 /*! @{ */ 2093 2094 #define NETC_F3_SI0_TBPIR_BDR_INDEX_MASK (0xFFFFU) 2095 #define NETC_F3_SI0_TBPIR_BDR_INDEX_SHIFT (0U) 2096 #define NETC_F3_SI0_TBPIR_BDR_INDEX_WIDTH (16U) 2097 #define NETC_F3_SI0_TBPIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBPIR_BDR_INDEX_SHIFT)) & NETC_F3_SI0_TBPIR_BDR_INDEX_MASK) 2098 /*! @} */ 2099 2100 /*! @name TBCIR - Tx BDR 0 consumer index register..Tx BDR 17 consumer index register */ 2101 /*! @{ */ 2102 2103 #define NETC_F3_SI0_TBCIR_BDR_INDEX_MASK (0xFFFFU) 2104 #define NETC_F3_SI0_TBCIR_BDR_INDEX_SHIFT (0U) 2105 #define NETC_F3_SI0_TBCIR_BDR_INDEX_WIDTH (16U) 2106 #define NETC_F3_SI0_TBCIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBCIR_BDR_INDEX_SHIFT)) & NETC_F3_SI0_TBCIR_BDR_INDEX_MASK) 2107 2108 #define NETC_F3_SI0_TBCIR_STAT_ID_MASK (0xFFFF0000U) 2109 #define NETC_F3_SI0_TBCIR_STAT_ID_SHIFT (16U) 2110 #define NETC_F3_SI0_TBCIR_STAT_ID_WIDTH (16U) 2111 #define NETC_F3_SI0_TBCIR_STAT_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBCIR_STAT_ID_SHIFT)) & NETC_F3_SI0_TBCIR_STAT_ID_MASK) 2112 /*! @} */ 2113 2114 /*! @name TBLENR - Tx BDR 0 length register..Tx BDR 17 length register */ 2115 /*! @{ */ 2116 2117 #define NETC_F3_SI0_TBLENR_LENGTH_MASK (0x1FFF8U) 2118 #define NETC_F3_SI0_TBLENR_LENGTH_SHIFT (3U) 2119 #define NETC_F3_SI0_TBLENR_LENGTH_WIDTH (14U) 2120 #define NETC_F3_SI0_TBLENR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBLENR_LENGTH_SHIFT)) & NETC_F3_SI0_TBLENR_LENGTH_MASK) 2121 /*! @} */ 2122 2123 /*! @name TBIER - Tx BDR 0 interrupt enable register..Tx BDR 17 interrupt enable register */ 2124 /*! @{ */ 2125 2126 #define NETC_F3_SI0_TBIER_TXTIE_MASK (0x1U) 2127 #define NETC_F3_SI0_TBIER_TXTIE_SHIFT (0U) 2128 #define NETC_F3_SI0_TBIER_TXTIE_WIDTH (1U) 2129 #define NETC_F3_SI0_TBIER_TXTIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBIER_TXTIE_SHIFT)) & NETC_F3_SI0_TBIER_TXTIE_MASK) 2130 2131 #define NETC_F3_SI0_TBIER_TXFIE_MASK (0x2U) 2132 #define NETC_F3_SI0_TBIER_TXFIE_SHIFT (1U) 2133 #define NETC_F3_SI0_TBIER_TXFIE_WIDTH (1U) 2134 #define NETC_F3_SI0_TBIER_TXFIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBIER_TXFIE_SHIFT)) & NETC_F3_SI0_TBIER_TXFIE_MASK) 2135 /*! @} */ 2136 2137 /*! @name TBIDR - Tx BDR 0 interrupt detect register..Tx BDR 17 interrupt detect register */ 2138 /*! @{ */ 2139 2140 #define NETC_F3_SI0_TBIDR_TXT_MASK (0x1U) 2141 #define NETC_F3_SI0_TBIDR_TXT_SHIFT (0U) 2142 #define NETC_F3_SI0_TBIDR_TXT_WIDTH (1U) 2143 #define NETC_F3_SI0_TBIDR_TXT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBIDR_TXT_SHIFT)) & NETC_F3_SI0_TBIDR_TXT_MASK) 2144 2145 #define NETC_F3_SI0_TBIDR_TXF_MASK (0x2U) 2146 #define NETC_F3_SI0_TBIDR_TXF_SHIFT (1U) 2147 #define NETC_F3_SI0_TBIDR_TXF_WIDTH (1U) 2148 #define NETC_F3_SI0_TBIDR_TXF(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBIDR_TXF_SHIFT)) & NETC_F3_SI0_TBIDR_TXF_MASK) 2149 /*! @} */ 2150 2151 /*! @name TBICR0 - Tx BDR 0 interrupt coalescing register 0..Tx BDR 17 interrupt coalescing register 0 */ 2152 /*! @{ */ 2153 2154 #define NETC_F3_SI0_TBICR0_ICPT_MASK (0xFU) 2155 #define NETC_F3_SI0_TBICR0_ICPT_SHIFT (0U) 2156 #define NETC_F3_SI0_TBICR0_ICPT_WIDTH (4U) 2157 #define NETC_F3_SI0_TBICR0_ICPT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBICR0_ICPT_SHIFT)) & NETC_F3_SI0_TBICR0_ICPT_MASK) 2158 2159 #define NETC_F3_SI0_TBICR0_ICEN_MASK (0x80000000U) 2160 #define NETC_F3_SI0_TBICR0_ICEN_SHIFT (31U) 2161 #define NETC_F3_SI0_TBICR0_ICEN_WIDTH (1U) 2162 #define NETC_F3_SI0_TBICR0_ICEN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBICR0_ICEN_SHIFT)) & NETC_F3_SI0_TBICR0_ICEN_MASK) 2163 /*! @} */ 2164 2165 /*! @name TBICR1 - Tx BDR 0 interrupt coalescing register 1..Tx BDR 17 interrupt coalescing register 1 */ 2166 /*! @{ */ 2167 2168 #define NETC_F3_SI0_TBICR1_ICTT_MASK (0xFFFFFFFFU) 2169 #define NETC_F3_SI0_TBICR1_ICTT_SHIFT (0U) 2170 #define NETC_F3_SI0_TBICR1_ICTT_WIDTH (32U) 2171 #define NETC_F3_SI0_TBICR1_ICTT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_TBICR1_ICTT_SHIFT)) & NETC_F3_SI0_TBICR1_ICTT_MASK) 2172 /*! @} */ 2173 2174 /*! @name RBMR - Rx BDR 0 mode register..Rx BDR 17 mode register */ 2175 /*! @{ */ 2176 2177 #define NETC_F3_SI0_RBMR_AL_MASK (0x1U) 2178 #define NETC_F3_SI0_RBMR_AL_SHIFT (0U) 2179 #define NETC_F3_SI0_RBMR_AL_WIDTH (1U) 2180 #define NETC_F3_SI0_RBMR_AL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBMR_AL_SHIFT)) & NETC_F3_SI0_RBMR_AL_MASK) 2181 2182 #define NETC_F3_SI0_RBMR_BDS_MASK (0x4U) 2183 #define NETC_F3_SI0_RBMR_BDS_SHIFT (2U) 2184 #define NETC_F3_SI0_RBMR_BDS_WIDTH (1U) 2185 #define NETC_F3_SI0_RBMR_BDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBMR_BDS_SHIFT)) & NETC_F3_SI0_RBMR_BDS_MASK) 2186 2187 #define NETC_F3_SI0_RBMR_CM_MASK (0x10U) 2188 #define NETC_F3_SI0_RBMR_CM_SHIFT (4U) 2189 #define NETC_F3_SI0_RBMR_CM_WIDTH (1U) 2190 #define NETC_F3_SI0_RBMR_CM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBMR_CM_SHIFT)) & NETC_F3_SI0_RBMR_CM_MASK) 2191 2192 #define NETC_F3_SI0_RBMR_VTE_MASK (0x20U) 2193 #define NETC_F3_SI0_RBMR_VTE_SHIFT (5U) 2194 #define NETC_F3_SI0_RBMR_VTE_WIDTH (1U) 2195 #define NETC_F3_SI0_RBMR_VTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBMR_VTE_SHIFT)) & NETC_F3_SI0_RBMR_VTE_MASK) 2196 2197 #define NETC_F3_SI0_RBMR_VTPD_MASK (0x40U) 2198 #define NETC_F3_SI0_RBMR_VTPD_SHIFT (6U) 2199 #define NETC_F3_SI0_RBMR_VTPD_WIDTH (1U) 2200 #define NETC_F3_SI0_RBMR_VTPD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBMR_VTPD_SHIFT)) & NETC_F3_SI0_RBMR_VTPD_MASK) 2201 2202 #define NETC_F3_SI0_RBMR_CRC_MASK (0x100U) 2203 #define NETC_F3_SI0_RBMR_CRC_SHIFT (8U) 2204 #define NETC_F3_SI0_RBMR_CRC_WIDTH (1U) 2205 #define NETC_F3_SI0_RBMR_CRC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBMR_CRC_SHIFT)) & NETC_F3_SI0_RBMR_CRC_MASK) 2206 2207 #define NETC_F3_SI0_RBMR_EN_MASK (0x80000000U) 2208 #define NETC_F3_SI0_RBMR_EN_SHIFT (31U) 2209 #define NETC_F3_SI0_RBMR_EN_WIDTH (1U) 2210 #define NETC_F3_SI0_RBMR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBMR_EN_SHIFT)) & NETC_F3_SI0_RBMR_EN_MASK) 2211 /*! @} */ 2212 2213 /*! @name RBSR - Rx BDR 0 status register..Rx BDR 17 status register */ 2214 /*! @{ */ 2215 2216 #define NETC_F3_SI0_RBSR_EMPTY_MASK (0x1U) 2217 #define NETC_F3_SI0_RBSR_EMPTY_SHIFT (0U) 2218 #define NETC_F3_SI0_RBSR_EMPTY_WIDTH (1U) 2219 #define NETC_F3_SI0_RBSR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBSR_EMPTY_SHIFT)) & NETC_F3_SI0_RBSR_EMPTY_MASK) 2220 2221 #define NETC_F3_SI0_RBSR_SBE_MASK (0x10000U) 2222 #define NETC_F3_SI0_RBSR_SBE_SHIFT (16U) 2223 #define NETC_F3_SI0_RBSR_SBE_WIDTH (1U) 2224 #define NETC_F3_SI0_RBSR_SBE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBSR_SBE_SHIFT)) & NETC_F3_SI0_RBSR_SBE_MASK) 2225 /*! @} */ 2226 2227 /*! @name RBBSR - Rx BDR 0 buffer size register..Rx BDR 17 buffer size register */ 2228 /*! @{ */ 2229 2230 #define NETC_F3_SI0_RBBSR_BSIZE_MASK (0xFFFFU) 2231 #define NETC_F3_SI0_RBBSR_BSIZE_SHIFT (0U) 2232 #define NETC_F3_SI0_RBBSR_BSIZE_WIDTH (16U) 2233 #define NETC_F3_SI0_RBBSR_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBBSR_BSIZE_SHIFT)) & NETC_F3_SI0_RBBSR_BSIZE_MASK) 2234 /*! @} */ 2235 2236 /*! @name RBCIR - Rx BDR 0 consumer index register..Rx BDR 17 consumer index register */ 2237 /*! @{ */ 2238 2239 #define NETC_F3_SI0_RBCIR_BDR_INDEX_MASK (0xFFFFU) 2240 #define NETC_F3_SI0_RBCIR_BDR_INDEX_SHIFT (0U) 2241 #define NETC_F3_SI0_RBCIR_BDR_INDEX_WIDTH (16U) 2242 #define NETC_F3_SI0_RBCIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBCIR_BDR_INDEX_SHIFT)) & NETC_F3_SI0_RBCIR_BDR_INDEX_MASK) 2243 /*! @} */ 2244 2245 /*! @name RBBAR0 - Rx BDR 0 base address register 0..Rx BDR 17 base address register 0 */ 2246 /*! @{ */ 2247 2248 #define NETC_F3_SI0_RBBAR0_ADDRL_MASK (0xFFFFFF80U) 2249 #define NETC_F3_SI0_RBBAR0_ADDRL_SHIFT (7U) 2250 #define NETC_F3_SI0_RBBAR0_ADDRL_WIDTH (25U) 2251 #define NETC_F3_SI0_RBBAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBBAR0_ADDRL_SHIFT)) & NETC_F3_SI0_RBBAR0_ADDRL_MASK) 2252 /*! @} */ 2253 2254 /*! @name RBBAR1 - Rx BDR 0 base address register 1..Rx BDR 17 base address register 1 */ 2255 /*! @{ */ 2256 2257 #define NETC_F3_SI0_RBBAR1_ADDRH_MASK (0xFFFFFFFFU) 2258 #define NETC_F3_SI0_RBBAR1_ADDRH_SHIFT (0U) 2259 #define NETC_F3_SI0_RBBAR1_ADDRH_WIDTH (32U) 2260 #define NETC_F3_SI0_RBBAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBBAR1_ADDRH_SHIFT)) & NETC_F3_SI0_RBBAR1_ADDRH_MASK) 2261 /*! @} */ 2262 2263 /*! @name RBPIR - Rx BDR 0 producer index register..Rx BDR 17 producer index register */ 2264 /*! @{ */ 2265 2266 #define NETC_F3_SI0_RBPIR_BDR_INDEX_MASK (0xFFFFU) 2267 #define NETC_F3_SI0_RBPIR_BDR_INDEX_SHIFT (0U) 2268 #define NETC_F3_SI0_RBPIR_BDR_INDEX_WIDTH (16U) 2269 #define NETC_F3_SI0_RBPIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBPIR_BDR_INDEX_SHIFT)) & NETC_F3_SI0_RBPIR_BDR_INDEX_MASK) 2270 /*! @} */ 2271 2272 /*! @name RBLENR - Rx BDR 0 length register..Rx BDR 17 length register */ 2273 /*! @{ */ 2274 2275 #define NETC_F3_SI0_RBLENR_LENGTH_MASK (0x1FFF8U) 2276 #define NETC_F3_SI0_RBLENR_LENGTH_SHIFT (3U) 2277 #define NETC_F3_SI0_RBLENR_LENGTH_WIDTH (14U) 2278 #define NETC_F3_SI0_RBLENR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBLENR_LENGTH_SHIFT)) & NETC_F3_SI0_RBLENR_LENGTH_MASK) 2279 /*! @} */ 2280 2281 /*! @name RBDCR - Rx BDR 0 drop count register..Rx BDR 17 drop count register */ 2282 /*! @{ */ 2283 2284 #define NETC_F3_SI0_RBDCR_COUNT_MASK (0xFFFFFFFFU) 2285 #define NETC_F3_SI0_RBDCR_COUNT_SHIFT (0U) 2286 #define NETC_F3_SI0_RBDCR_COUNT_WIDTH (32U) 2287 #define NETC_F3_SI0_RBDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBDCR_COUNT_SHIFT)) & NETC_F3_SI0_RBDCR_COUNT_MASK) 2288 /*! @} */ 2289 2290 /*! @name RBIER - Rx BDR 0 interrupt enable register..Rx BDR 17 interrupt enable register */ 2291 /*! @{ */ 2292 2293 #define NETC_F3_SI0_RBIER_RXTIE_MASK (0x1U) 2294 #define NETC_F3_SI0_RBIER_RXTIE_SHIFT (0U) 2295 #define NETC_F3_SI0_RBIER_RXTIE_WIDTH (1U) 2296 #define NETC_F3_SI0_RBIER_RXTIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBIER_RXTIE_SHIFT)) & NETC_F3_SI0_RBIER_RXTIE_MASK) 2297 /*! @} */ 2298 2299 /*! @name RBIDR - Rx BDR 0 interrupt detect register..Rx BDR 17 interrupt detect register */ 2300 /*! @{ */ 2301 2302 #define NETC_F3_SI0_RBIDR_RXT_MASK (0x1U) 2303 #define NETC_F3_SI0_RBIDR_RXT_SHIFT (0U) 2304 #define NETC_F3_SI0_RBIDR_RXT_WIDTH (1U) 2305 #define NETC_F3_SI0_RBIDR_RXT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBIDR_RXT_SHIFT)) & NETC_F3_SI0_RBIDR_RXT_MASK) 2306 /*! @} */ 2307 2308 /*! @name RBICR0 - Rx BDR 0 interrupt coalescing register 0..Rx BDR 17 interrupt coalescing register 0 */ 2309 /*! @{ */ 2310 2311 #define NETC_F3_SI0_RBICR0_ICPT_MASK (0x1FFU) 2312 #define NETC_F3_SI0_RBICR0_ICPT_SHIFT (0U) 2313 #define NETC_F3_SI0_RBICR0_ICPT_WIDTH (9U) 2314 #define NETC_F3_SI0_RBICR0_ICPT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBICR0_ICPT_SHIFT)) & NETC_F3_SI0_RBICR0_ICPT_MASK) 2315 2316 #define NETC_F3_SI0_RBICR0_ICEN_MASK (0x80000000U) 2317 #define NETC_F3_SI0_RBICR0_ICEN_SHIFT (31U) 2318 #define NETC_F3_SI0_RBICR0_ICEN_WIDTH (1U) 2319 #define NETC_F3_SI0_RBICR0_ICEN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBICR0_ICEN_SHIFT)) & NETC_F3_SI0_RBICR0_ICEN_MASK) 2320 /*! @} */ 2321 2322 /*! @name RBICR1 - Rx BDR 0 interrupt coalescing register 1..Rx BDR 17 interrupt coalescing register 1 */ 2323 /*! @{ */ 2324 2325 #define NETC_F3_SI0_RBICR1_ICTT_MASK (0xFFFFFFFFU) 2326 #define NETC_F3_SI0_RBICR1_ICTT_SHIFT (0U) 2327 #define NETC_F3_SI0_RBICR1_ICTT_WIDTH (32U) 2328 #define NETC_F3_SI0_RBICR1_ICTT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SI0_RBICR1_ICTT_SHIFT)) & NETC_F3_SI0_RBICR1_ICTT_MASK) 2329 /*! @} */ 2330 2331 /*! 2332 * @} 2333 */ /* end of group NETC_F3_SI0_Register_Masks */ 2334 2335 /*! 2336 * @} 2337 */ /* end of group NETC_F3_SI0_Peripheral_Access_Layer */ 2338 2339 #endif /* #if !defined(S32Z2_NETC_F3_SI0_H_) */ 2340
