1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_NETC_F3.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_NETC_F3 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_NETC_F3_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_NETC_F3_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- NETC_F3 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup NETC_F3_Peripheral_Access_Layer NETC_F3 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** NETC_F3 - Size of Registers Arrays */ 72 #define NETC_F3_PARCEACR_COUNT 4u 73 #define NETC_F3_PICDRADCR_COUNT 4u 74 #define NETC_F3_TC_TBS_NUM_COUNT 8u 75 #define NETC_F3_NUM_SMHRBDRMR_COUNT 15u 76 #define NETC_F3_NUM_SI_COUNT 8u 77 78 /** NETC_F3 - Register Layout Typedef */ 79 typedef struct { 80 __I uint32_t ECAPR0; /**< ENETC capability register 0, offset: 0x0 */ 81 __I uint32_t ECAPR1; /**< ENETC capability register 1, offset: 0x4 */ 82 __I uint32_t ECAPR2; /**< ENETC capability register 2, offset: 0x8 */ 83 uint8_t RESERVED_0[4]; 84 __IO uint32_t PMR; /**< Port mode register, offset: 0x10 */ 85 uint8_t RESERVED_1[108]; 86 __IO uint32_t PONVLANR; /**< Port outer native VLAN register, offset: 0x80 */ 87 __IO uint32_t PINVLANR; /**< Port inner native VLAN register, offset: 0x84 */ 88 __IO uint32_t PVCLCTR; /**< Port VLAN classification control register, offset: 0x88 */ 89 uint8_t RESERVED_2[16]; 90 __IO uint32_t PARCSCR; /**< Parser checksum configuration register, offset: 0x9C */ 91 __IO uint32_t PARCECR[NETC_F3_PARCEACR_COUNT]; /**< Parser custom Ethertype 0 configuration register..Parser custom Ethertype 3 configuration register, array offset: 0xA0, array step: 0x4 */ 92 uint8_t RESERVED_3[88]; 93 __IO uint32_t PPAUONTR; /**< Port pause ON threshold register, offset: 0x108 */ 94 __IO uint32_t PPAUOFFTR; /**< Port pause OFF threshold register, offset: 0x10C */ 95 uint8_t RESERVED_4[16]; 96 __I uint32_t PRXMBER; /**< Port receive memory buffer entitlement register, offset: 0x120 */ 97 __I uint32_t PRXMBLR; /**< Port receive memory buffer limit register, offset: 0x124 */ 98 __I uint32_t PRXBCR; /**< Port receive buffer count register, offset: 0x128 */ 99 __I uint32_t PRXBCHWMR; /**< Port receive buffer count high watermark register, offset: 0x12C */ 100 uint8_t RESERVED_5[16]; 101 struct { /* offset: 0x140, array step: 0x10 */ 102 __I uint32_t PICDRDCR; /**< Port ingress congestion DR0 discard count register..Port ingress congestion DR3 discard count register, array offset: 0x140, array step: 0x10 */ 103 uint8_t RESERVED_0[4]; 104 __I uint32_t PICDRDCRRR; /**< Port ingress congestion DR0 discard count read-reset register..Port ingress congestion DR3 discard count read-reset register, array offset: 0x148, array step: 0x10 */ 105 uint8_t RESERVED_1[4]; 106 } PICDRADCR[NETC_F3_PICDRADCR_COUNT]; 107 __IO uint32_t PICPDSR; /**< Port ingress congestion priority discard status register, offset: 0x180 */ 108 uint8_t RESERVED_6[124]; 109 __IO uint32_t PSIPMMR; /**< Port station interface promiscuous MAC mode register, offset: 0x200 */ 110 __IO uint32_t PSIPVMR; /**< Port station interface promiscuous VLAN mode register, offset: 0x204 */ 111 __I uint32_t PBFDSIR; /**< Port broadcast frames dropped due to MAC filtering register, offset: 0x208 */ 112 __I uint32_t PFDMSAPR; /**< Port frame drop MAC source address pruning register, offset: 0x20C */ 113 uint8_t RESERVED_7[112]; 114 __I uint32_t PSIMAFCAPR; /**< Port station interface MAC address filtering capability register, offset: 0x280 */ 115 __I uint32_t PUFDMFR; /**< Port unicast frames dropped due to MAC filtering register, offset: 0x284 */ 116 __I uint32_t PMFDMFR; /**< Port multicast frames dropped due to MAC filtering register, offset: 0x288 */ 117 uint8_t RESERVED_8[52]; 118 __I uint32_t PSIVLANFCAPR; /**< Port station interface VLAN filtering capability register, offset: 0x2C0 */ 119 __IO uint32_t PSIVLANFMR; /**< Port station interface VLAN filtering mode register, offset: 0x2C4 */ 120 uint8_t RESERVED_9[8]; 121 __I uint32_t PUFDVFR; /**< Port unicast frames dropped VLAN filtering register, offset: 0x2D0 */ 122 __I uint32_t PMFDVFR; /**< Port multicast frames dropped VLAN filtering register, offset: 0x2D4 */ 123 __I uint32_t PBFDVFR; /**< Port broadcast frames dropped VLAN filtering register, offset: 0x2D8 */ 124 uint8_t RESERVED_10[36]; 125 __I uint32_t PRFSCAPR; /**< Port RFS capability register, offset: 0x300 */ 126 uint8_t RESERVED_11[12]; 127 __IO uint32_t PRFSMR; /**< Port RFS mode register, offset: 0x310 */ 128 uint8_t RESERVED_12[92]; 129 __IO uint32_t IPV2ICMPMR0; /**< Receive IPV to ICM priority mapping register 0, offset: 0x370 */ 130 uint8_t RESERVED_13[12]; 131 __IO uint32_t PRIO2TCMR0; /**< Transmit priority to traffic class mapping register 0, offset: 0x380 */ 132 uint8_t RESERVED_14[12]; 133 __IO uint32_t PTCTSDR[NETC_F3_TC_TBS_NUM_COUNT]; /**< Port traffic class 0 time specific departure register..Port traffic class 7 time specific departure register, array offset: 0x390, array step: 0x4 */ 134 uint8_t RESERVED_15[1104]; 135 __I uint32_t SMCAPR; /**< Switch management capability register, offset: 0x800 */ 136 uint8_t RESERVED_16[124]; 137 __IO uint32_t SMHRBDRMR[NETC_F3_NUM_SMHRBDRMR_COUNT]; /**< Switch management host reason 1 receive BD ring mapping register..Switch management host reason 15 receive BD ring mapping register, array offset: 0x880, array step: 0x4 */ 138 uint8_t RESERVED_17[5956]; 139 struct { /* offset: 0x2000, array step: 0x80 */ 140 __IO uint32_t PSIPMAR0; /**< Port station interface 0 primary MAC address register 0..Port station interface 7 primary MAC address register 0, array offset: 0x2000, array step: 0x80 */ 141 __IO uint32_t PSIPMAR1; /**< Port station interface 0 primary MAC address register 1..Port station interface 7 primary MAC address register 1, array offset: 0x2004, array step: 0x80 */ 142 __IO uint32_t PSIVLANR; /**< Port station interface 0 VLAN register..Port station interface 7 VLAN register, array offset: 0x2008, array step: 0x80 */ 143 uint8_t RESERVED_0[4]; 144 __IO uint32_t PSICFGR0; /**< Port station interface 0 configuration register 0..Port station interface 7 configuration register 0, array offset: 0x2010, array step: 0x80 */ 145 __IO uint32_t PSICFGR1; /**< Port station interface 1 configuration register 1..Port station interface 7 configuration register 1, array offset: 0x2014, array step: 0x80, valid indices: [1-7] */ 146 __IO uint32_t PSICFGR2; /**< Port station interface 0 configuration register 2..Port station interface 7 configuration register 2, array offset: 0x2018, array step: 0x80 */ 147 uint8_t RESERVED_1[20]; 148 __IO uint32_t PSIVMAFCFGR; /**< Port station interface 0 VSI MAC address filtering configuration register..Port station interface 7 VSI MAC address filtering configuration register, array offset: 0x2030, array step: 0x80 */ 149 __IO uint32_t PSIVLANFCFGR; /**< Port station interface 0 VLAN filtering configuration register..Port station interface 7 VLAN filtering configuration register, array offset: 0x2034, array step: 0x80 */ 150 uint8_t RESERVED_2[8]; 151 __I uint32_t PSIRFSCFGR; /**< Port station interface 0 RFS configuration register..Port station interface 7 RFS configuration register, array offset: 0x2040, array step: 0x80 */ 152 uint8_t RESERVED_3[12]; 153 __IO uint32_t PSIUMHFR0; /**< Port station interface 0 unicast MAC hash filter register 0..Port station interface 7 unicast MAC hash filter register 0, array offset: 0x2050, array step: 0x80 */ 154 __IO uint32_t PSIUMHFR1; /**< Port station interface 0 unicast MAC hash filter register 1..Port station interface 7 unicast MAC hash filter register 1, array offset: 0x2054, array step: 0x80 */ 155 __IO uint32_t PSIMMHFR0; /**< Port station interface 0 multicast MAC hash filter register 0..Port station interface 7 multicast MAC hash filter register 0, array offset: 0x2058, array step: 0x80 */ 156 __IO uint32_t PSIMMHFR1; /**< Port station interface 0 multicast MAC hash filter register 1..Port station interface 7 multicast MAC hash filter register 1, array offset: 0x205C, array step: 0x80 */ 157 __IO uint32_t PSIVHFR0; /**< Port station interface 0 VLAN hash filter register 0..Port station interface 7 VLAN hash filter register 0, array offset: 0x2060, array step: 0x80 */ 158 __IO uint32_t PSIVHFR1; /**< Port station interface 0 VLAN hash filter register 1..Port station interface 7 VLAN hash filter register 1, array offset: 0x2064, array step: 0x80 */ 159 uint8_t RESERVED_4[24]; 160 } NUM_SI[NETC_F3_NUM_SI_COUNT]; 161 } NETC_F3_Type, *NETC_F3_MemMapPtr; 162 163 /** Number of instances of the NETC_F3 module. */ 164 #define NETC_F3_INSTANCE_COUNT (1u) 165 166 /* NETC_F3 - Peripheral instance base addresses */ 167 /** Peripheral NETC__ENETC0_BASE base address */ 168 #define IP_NETC__ENETC0_BASE_BASE (0x74B10000u) 169 /** Peripheral NETC__ENETC0_BASE base pointer */ 170 #define IP_NETC__ENETC0_BASE ((NETC_F3_Type *)IP_NETC__ENETC0_BASE_BASE) 171 /** Array initializer of NETC_F3 peripheral base addresses */ 172 #define IP_NETC_F3_BASE_ADDRS { IP_NETC__ENETC0_BASE_BASE } 173 /** Array initializer of NETC_F3 peripheral base pointers */ 174 #define IP_NETC_F3_BASE_PTRS { IP_NETC__ENETC0_BASE } 175 176 /* ---------------------------------------------------------------------------- 177 -- NETC_F3 Register Masks 178 ---------------------------------------------------------------------------- */ 179 180 /*! 181 * @addtogroup NETC_F3_Register_Masks NETC_F3 Register Masks 182 * @{ 183 */ 184 185 /*! @name ECAPR0 - ENETC capability register 0 */ 186 /*! @{ */ 187 188 #define NETC_F3_ECAPR0_RFS_MASK (0x4U) 189 #define NETC_F3_ECAPR0_RFS_SHIFT (2U) 190 #define NETC_F3_ECAPR0_RFS_WIDTH (1U) 191 #define NETC_F3_ECAPR0_RFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR0_RFS_SHIFT)) & NETC_F3_ECAPR0_RFS_MASK) 192 193 #define NETC_F3_ECAPR0_TSD_MASK (0x20U) 194 #define NETC_F3_ECAPR0_TSD_SHIFT (5U) 195 #define NETC_F3_ECAPR0_TSD_WIDTH (1U) 196 #define NETC_F3_ECAPR0_TSD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR0_TSD_SHIFT)) & NETC_F3_ECAPR0_TSD_MASK) 197 198 #define NETC_F3_ECAPR0_RSS_MASK (0x100U) 199 #define NETC_F3_ECAPR0_RSS_SHIFT (8U) 200 #define NETC_F3_ECAPR0_RSS_WIDTH (1U) 201 #define NETC_F3_ECAPR0_RSS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR0_RSS_SHIFT)) & NETC_F3_ECAPR0_RSS_MASK) 202 203 #define NETC_F3_ECAPR0_WO_MASK (0x2000U) 204 #define NETC_F3_ECAPR0_WO_SHIFT (13U) 205 #define NETC_F3_ECAPR0_WO_WIDTH (1U) 206 #define NETC_F3_ECAPR0_WO(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR0_WO_SHIFT)) & NETC_F3_ECAPR0_WO_MASK) 207 208 #define NETC_F3_ECAPR0_FS_MASK (0x10000U) 209 #define NETC_F3_ECAPR0_FS_SHIFT (16U) 210 #define NETC_F3_ECAPR0_FS_WIDTH (1U) 211 #define NETC_F3_ECAPR0_FS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR0_FS_SHIFT)) & NETC_F3_ECAPR0_FS_MASK) 212 /*! @} */ 213 214 /*! @name ECAPR1 - ENETC capability register 1 */ 215 /*! @{ */ 216 217 #define NETC_F3_ECAPR1_NUM_TCS_MASK (0x70U) 218 #define NETC_F3_ECAPR1_NUM_TCS_SHIFT (4U) 219 #define NETC_F3_ECAPR1_NUM_TCS_WIDTH (3U) 220 #define NETC_F3_ECAPR1_NUM_TCS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR1_NUM_TCS_SHIFT)) & NETC_F3_ECAPR1_NUM_TCS_MASK) 221 222 #define NETC_F3_ECAPR1_NUM_MCH_MASK (0x300U) 223 #define NETC_F3_ECAPR1_NUM_MCH_SHIFT (8U) 224 #define NETC_F3_ECAPR1_NUM_MCH_WIDTH (2U) 225 #define NETC_F3_ECAPR1_NUM_MCH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR1_NUM_MCH_SHIFT)) & NETC_F3_ECAPR1_NUM_MCH_MASK) 226 227 #define NETC_F3_ECAPR1_NUM_UCH_MASK (0xC00U) 228 #define NETC_F3_ECAPR1_NUM_UCH_SHIFT (10U) 229 #define NETC_F3_ECAPR1_NUM_UCH_WIDTH (2U) 230 #define NETC_F3_ECAPR1_NUM_UCH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR1_NUM_UCH_SHIFT)) & NETC_F3_ECAPR1_NUM_UCH_MASK) 231 232 #define NETC_F3_ECAPR1_NUM_MSIX_MASK (0x7FF000U) 233 #define NETC_F3_ECAPR1_NUM_MSIX_SHIFT (12U) 234 #define NETC_F3_ECAPR1_NUM_MSIX_WIDTH (11U) 235 #define NETC_F3_ECAPR1_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR1_NUM_MSIX_SHIFT)) & NETC_F3_ECAPR1_NUM_MSIX_MASK) 236 237 #define NETC_F3_ECAPR1_NUM_VSI_MASK (0xF000000U) 238 #define NETC_F3_ECAPR1_NUM_VSI_SHIFT (24U) 239 #define NETC_F3_ECAPR1_NUM_VSI_WIDTH (4U) 240 #define NETC_F3_ECAPR1_NUM_VSI(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR1_NUM_VSI_SHIFT)) & NETC_F3_ECAPR1_NUM_VSI_MASK) 241 242 #define NETC_F3_ECAPR1_NUM_IPV_MASK (0x80000000U) 243 #define NETC_F3_ECAPR1_NUM_IPV_SHIFT (31U) 244 #define NETC_F3_ECAPR1_NUM_IPV_WIDTH (1U) 245 #define NETC_F3_ECAPR1_NUM_IPV(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR1_NUM_IPV_SHIFT)) & NETC_F3_ECAPR1_NUM_IPV_MASK) 246 /*! @} */ 247 248 /*! @name ECAPR2 - ENETC capability register 2 */ 249 /*! @{ */ 250 251 #define NETC_F3_ECAPR2_NUM_TX_BDR_MASK (0x3FFU) 252 #define NETC_F3_ECAPR2_NUM_TX_BDR_SHIFT (0U) 253 #define NETC_F3_ECAPR2_NUM_TX_BDR_WIDTH (10U) 254 #define NETC_F3_ECAPR2_NUM_TX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR2_NUM_TX_BDR_SHIFT)) & NETC_F3_ECAPR2_NUM_TX_BDR_MASK) 255 256 #define NETC_F3_ECAPR2_NUM_RX_BDR_MASK (0x3FF0000U) 257 #define NETC_F3_ECAPR2_NUM_RX_BDR_SHIFT (16U) 258 #define NETC_F3_ECAPR2_NUM_RX_BDR_WIDTH (10U) 259 #define NETC_F3_ECAPR2_NUM_RX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_ECAPR2_NUM_RX_BDR_SHIFT)) & NETC_F3_ECAPR2_NUM_RX_BDR_MASK) 260 /*! @} */ 261 262 /*! @name PMR - Port mode register */ 263 /*! @{ */ 264 265 #define NETC_F3_PMR_SI0EN_MASK (0x10000U) 266 #define NETC_F3_PMR_SI0EN_SHIFT (16U) 267 #define NETC_F3_PMR_SI0EN_WIDTH (1U) 268 #define NETC_F3_PMR_SI0EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PMR_SI0EN_SHIFT)) & NETC_F3_PMR_SI0EN_MASK) 269 270 #define NETC_F3_PMR_SI1EN_MASK (0x20000U) 271 #define NETC_F3_PMR_SI1EN_SHIFT (17U) 272 #define NETC_F3_PMR_SI1EN_WIDTH (1U) 273 #define NETC_F3_PMR_SI1EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PMR_SI1EN_SHIFT)) & NETC_F3_PMR_SI1EN_MASK) 274 275 #define NETC_F3_PMR_SI2EN_MASK (0x40000U) 276 #define NETC_F3_PMR_SI2EN_SHIFT (18U) 277 #define NETC_F3_PMR_SI2EN_WIDTH (1U) 278 #define NETC_F3_PMR_SI2EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PMR_SI2EN_SHIFT)) & NETC_F3_PMR_SI2EN_MASK) 279 280 #define NETC_F3_PMR_SI3EN_MASK (0x80000U) 281 #define NETC_F3_PMR_SI3EN_SHIFT (19U) 282 #define NETC_F3_PMR_SI3EN_WIDTH (1U) 283 #define NETC_F3_PMR_SI3EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PMR_SI3EN_SHIFT)) & NETC_F3_PMR_SI3EN_MASK) 284 285 #define NETC_F3_PMR_SI4EN_MASK (0x100000U) 286 #define NETC_F3_PMR_SI4EN_SHIFT (20U) 287 #define NETC_F3_PMR_SI4EN_WIDTH (1U) 288 #define NETC_F3_PMR_SI4EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PMR_SI4EN_SHIFT)) & NETC_F3_PMR_SI4EN_MASK) 289 290 #define NETC_F3_PMR_SI5EN_MASK (0x200000U) 291 #define NETC_F3_PMR_SI5EN_SHIFT (21U) 292 #define NETC_F3_PMR_SI5EN_WIDTH (1U) 293 #define NETC_F3_PMR_SI5EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PMR_SI5EN_SHIFT)) & NETC_F3_PMR_SI5EN_MASK) 294 295 #define NETC_F3_PMR_SI6EN_MASK (0x400000U) 296 #define NETC_F3_PMR_SI6EN_SHIFT (22U) 297 #define NETC_F3_PMR_SI6EN_WIDTH (1U) 298 #define NETC_F3_PMR_SI6EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PMR_SI6EN_SHIFT)) & NETC_F3_PMR_SI6EN_MASK) 299 300 #define NETC_F3_PMR_SI7EN_MASK (0x800000U) 301 #define NETC_F3_PMR_SI7EN_SHIFT (23U) 302 #define NETC_F3_PMR_SI7EN_WIDTH (1U) 303 #define NETC_F3_PMR_SI7EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PMR_SI7EN_SHIFT)) & NETC_F3_PMR_SI7EN_MASK) 304 /*! @} */ 305 306 /*! @name PONVLANR - Port outer native VLAN register */ 307 /*! @{ */ 308 309 #define NETC_F3_PONVLANR_VID_MASK (0xFFFU) 310 #define NETC_F3_PONVLANR_VID_SHIFT (0U) 311 #define NETC_F3_PONVLANR_VID_WIDTH (12U) 312 #define NETC_F3_PONVLANR_VID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PONVLANR_VID_SHIFT)) & NETC_F3_PONVLANR_VID_MASK) 313 314 #define NETC_F3_PONVLANR_DEI_MASK (0x1000U) 315 #define NETC_F3_PONVLANR_DEI_SHIFT (12U) 316 #define NETC_F3_PONVLANR_DEI_WIDTH (1U) 317 #define NETC_F3_PONVLANR_DEI(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PONVLANR_DEI_SHIFT)) & NETC_F3_PONVLANR_DEI_MASK) 318 319 #define NETC_F3_PONVLANR_PCP_MASK (0xE000U) 320 #define NETC_F3_PONVLANR_PCP_SHIFT (13U) 321 #define NETC_F3_PONVLANR_PCP_WIDTH (3U) 322 #define NETC_F3_PONVLANR_PCP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PONVLANR_PCP_SHIFT)) & NETC_F3_PONVLANR_PCP_MASK) 323 324 #define NETC_F3_PONVLANR_TPID_MASK (0x30000U) 325 #define NETC_F3_PONVLANR_TPID_SHIFT (16U) 326 #define NETC_F3_PONVLANR_TPID_WIDTH (2U) 327 #define NETC_F3_PONVLANR_TPID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PONVLANR_TPID_SHIFT)) & NETC_F3_PONVLANR_TPID_MASK) 328 329 #define NETC_F3_PONVLANR_PNE_MASK (0x40000U) 330 #define NETC_F3_PONVLANR_PNE_SHIFT (18U) 331 #define NETC_F3_PONVLANR_PNE_WIDTH (1U) 332 #define NETC_F3_PONVLANR_PNE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PONVLANR_PNE_SHIFT)) & NETC_F3_PONVLANR_PNE_MASK) 333 334 #define NETC_F3_PONVLANR_VZE_MASK (0x80000U) 335 #define NETC_F3_PONVLANR_VZE_SHIFT (19U) 336 #define NETC_F3_PONVLANR_VZE_WIDTH (1U) 337 #define NETC_F3_PONVLANR_VZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PONVLANR_VZE_SHIFT)) & NETC_F3_PONVLANR_VZE_MASK) 338 /*! @} */ 339 340 /*! @name PINVLANR - Port inner native VLAN register */ 341 /*! @{ */ 342 343 #define NETC_F3_PINVLANR_VID_MASK (0xFFFU) 344 #define NETC_F3_PINVLANR_VID_SHIFT (0U) 345 #define NETC_F3_PINVLANR_VID_WIDTH (12U) 346 #define NETC_F3_PINVLANR_VID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PINVLANR_VID_SHIFT)) & NETC_F3_PINVLANR_VID_MASK) 347 348 #define NETC_F3_PINVLANR_DEI_MASK (0x1000U) 349 #define NETC_F3_PINVLANR_DEI_SHIFT (12U) 350 #define NETC_F3_PINVLANR_DEI_WIDTH (1U) 351 #define NETC_F3_PINVLANR_DEI(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PINVLANR_DEI_SHIFT)) & NETC_F3_PINVLANR_DEI_MASK) 352 353 #define NETC_F3_PINVLANR_PCP_MASK (0xE000U) 354 #define NETC_F3_PINVLANR_PCP_SHIFT (13U) 355 #define NETC_F3_PINVLANR_PCP_WIDTH (3U) 356 #define NETC_F3_PINVLANR_PCP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PINVLANR_PCP_SHIFT)) & NETC_F3_PINVLANR_PCP_MASK) 357 358 #define NETC_F3_PINVLANR_TPID_MASK (0x30000U) 359 #define NETC_F3_PINVLANR_TPID_SHIFT (16U) 360 #define NETC_F3_PINVLANR_TPID_WIDTH (2U) 361 #define NETC_F3_PINVLANR_TPID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PINVLANR_TPID_SHIFT)) & NETC_F3_PINVLANR_TPID_MASK) 362 363 #define NETC_F3_PINVLANR_PNE_MASK (0x40000U) 364 #define NETC_F3_PINVLANR_PNE_SHIFT (18U) 365 #define NETC_F3_PINVLANR_PNE_WIDTH (1U) 366 #define NETC_F3_PINVLANR_PNE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PINVLANR_PNE_SHIFT)) & NETC_F3_PINVLANR_PNE_MASK) 367 368 #define NETC_F3_PINVLANR_VZE_MASK (0x80000U) 369 #define NETC_F3_PINVLANR_VZE_SHIFT (19U) 370 #define NETC_F3_PINVLANR_VZE_WIDTH (1U) 371 #define NETC_F3_PINVLANR_VZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PINVLANR_VZE_SHIFT)) & NETC_F3_PINVLANR_VZE_MASK) 372 /*! @} */ 373 374 /*! @name PVCLCTR - Port VLAN classification control register */ 375 /*! @{ */ 376 377 #define NETC_F3_PVCLCTR_OAI_MASK (0x200U) 378 #define NETC_F3_PVCLCTR_OAI_SHIFT (9U) 379 #define NETC_F3_PVCLCTR_OAI_WIDTH (1U) 380 #define NETC_F3_PVCLCTR_OAI(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PVCLCTR_OAI_SHIFT)) & NETC_F3_PVCLCTR_OAI_MASK) 381 /*! @} */ 382 383 /*! @name PARCSCR - Parser checksum configuration register */ 384 /*! @{ */ 385 386 #define NETC_F3_PARCSCR_L4CD_MASK (0x1U) 387 #define NETC_F3_PARCSCR_L4CD_SHIFT (0U) 388 #define NETC_F3_PARCSCR_L4CD_WIDTH (1U) 389 #define NETC_F3_PARCSCR_L4CD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PARCSCR_L4CD_SHIFT)) & NETC_F3_PARCSCR_L4CD_MASK) 390 391 #define NETC_F3_PARCSCR_L3CD_MASK (0x2U) 392 #define NETC_F3_PARCSCR_L3CD_SHIFT (1U) 393 #define NETC_F3_PARCSCR_L3CD_WIDTH (1U) 394 #define NETC_F3_PARCSCR_L3CD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PARCSCR_L3CD_SHIFT)) & NETC_F3_PARCSCR_L3CD_MASK) 395 /*! @} */ 396 397 /*! @name PARCECR - Parser custom Ethertype 0 configuration register..Parser custom Ethertype 3 configuration register */ 398 /*! @{ */ 399 400 #define NETC_F3_PARCECR_CP_MASK (0xFU) 401 #define NETC_F3_PARCECR_CP_SHIFT (0U) 402 #define NETC_F3_PARCECR_CP_WIDTH (4U) 403 #define NETC_F3_PARCECR_CP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PARCECR_CP_SHIFT)) & NETC_F3_PARCECR_CP_MASK) 404 405 #define NETC_F3_PARCECR_EN_MASK (0x20U) 406 #define NETC_F3_PARCECR_EN_SHIFT (5U) 407 #define NETC_F3_PARCECR_EN_WIDTH (1U) 408 #define NETC_F3_PARCECR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PARCECR_EN_SHIFT)) & NETC_F3_PARCECR_EN_MASK) 409 410 #define NETC_F3_PARCECR_ETYPE_MASK (0xFFFF0000U) 411 #define NETC_F3_PARCECR_ETYPE_SHIFT (16U) 412 #define NETC_F3_PARCECR_ETYPE_WIDTH (16U) 413 #define NETC_F3_PARCECR_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PARCECR_ETYPE_SHIFT)) & NETC_F3_PARCECR_ETYPE_MASK) 414 /*! @} */ 415 416 /*! @name PPAUONTR - Port pause ON threshold register */ 417 /*! @{ */ 418 419 #define NETC_F3_PPAUONTR_THRESH_MASK (0xFFFFFFU) 420 #define NETC_F3_PPAUONTR_THRESH_SHIFT (0U) 421 #define NETC_F3_PPAUONTR_THRESH_WIDTH (24U) 422 #define NETC_F3_PPAUONTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PPAUONTR_THRESH_SHIFT)) & NETC_F3_PPAUONTR_THRESH_MASK) 423 /*! @} */ 424 425 /*! @name PPAUOFFTR - Port pause OFF threshold register */ 426 /*! @{ */ 427 428 #define NETC_F3_PPAUOFFTR_THRESH_MASK (0xFFFFFFU) 429 #define NETC_F3_PPAUOFFTR_THRESH_SHIFT (0U) 430 #define NETC_F3_PPAUOFFTR_THRESH_WIDTH (24U) 431 #define NETC_F3_PPAUOFFTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PPAUOFFTR_THRESH_SHIFT)) & NETC_F3_PPAUOFFTR_THRESH_MASK) 432 /*! @} */ 433 434 /*! @name PRXMBER - Port receive memory buffer entitlement register */ 435 /*! @{ */ 436 437 #define NETC_F3_PRXMBER_AMOUNT_MASK (0xFFFFFFU) 438 #define NETC_F3_PRXMBER_AMOUNT_SHIFT (0U) 439 #define NETC_F3_PRXMBER_AMOUNT_WIDTH (24U) 440 #define NETC_F3_PRXMBER_AMOUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRXMBER_AMOUNT_SHIFT)) & NETC_F3_PRXMBER_AMOUNT_MASK) 441 /*! @} */ 442 443 /*! @name PRXMBLR - Port receive memory buffer limit register */ 444 /*! @{ */ 445 446 #define NETC_F3_PRXMBLR_LIMIT_MASK (0xFFFFFFU) 447 #define NETC_F3_PRXMBLR_LIMIT_SHIFT (0U) 448 #define NETC_F3_PRXMBLR_LIMIT_WIDTH (24U) 449 #define NETC_F3_PRXMBLR_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRXMBLR_LIMIT_SHIFT)) & NETC_F3_PRXMBLR_LIMIT_MASK) 450 /*! @} */ 451 452 /*! @name PRXBCR - Port receive buffer count register */ 453 /*! @{ */ 454 455 #define NETC_F3_PRXBCR_COUNT_MASK (0xFFFFFFU) 456 #define NETC_F3_PRXBCR_COUNT_SHIFT (0U) 457 #define NETC_F3_PRXBCR_COUNT_WIDTH (24U) 458 #define NETC_F3_PRXBCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRXBCR_COUNT_SHIFT)) & NETC_F3_PRXBCR_COUNT_MASK) 459 /*! @} */ 460 461 /*! @name PRXBCHWMR - Port receive buffer count high watermark register */ 462 /*! @{ */ 463 464 #define NETC_F3_PRXBCHWMR_WATERMARK_MASK (0xFFFFFFU) 465 #define NETC_F3_PRXBCHWMR_WATERMARK_SHIFT (0U) 466 #define NETC_F3_PRXBCHWMR_WATERMARK_WIDTH (24U) 467 #define NETC_F3_PRXBCHWMR_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRXBCHWMR_WATERMARK_SHIFT)) & NETC_F3_PRXBCHWMR_WATERMARK_MASK) 468 /*! @} */ 469 470 /*! @name PICDRDCR - Port ingress congestion DR0 discard count register..Port ingress congestion DR3 discard count register */ 471 /*! @{ */ 472 473 #define NETC_F3_PICDRDCR_COUNT_MASK (0xFFFFFFFFU) 474 #define NETC_F3_PICDRDCR_COUNT_SHIFT (0U) 475 #define NETC_F3_PICDRDCR_COUNT_WIDTH (32U) 476 #define NETC_F3_PICDRDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PICDRDCR_COUNT_SHIFT)) & NETC_F3_PICDRDCR_COUNT_MASK) 477 /*! @} */ 478 479 /*! @name PICDRDCRRR - Port ingress congestion DR0 discard count read-reset register..Port ingress congestion DR3 discard count read-reset register */ 480 /*! @{ */ 481 482 #define NETC_F3_PICDRDCRRR_COUNT_MASK (0xFFFFFFFFU) 483 #define NETC_F3_PICDRDCRRR_COUNT_SHIFT (0U) 484 #define NETC_F3_PICDRDCRRR_COUNT_WIDTH (32U) 485 #define NETC_F3_PICDRDCRRR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PICDRDCRRR_COUNT_SHIFT)) & NETC_F3_PICDRDCRRR_COUNT_MASK) 486 /*! @} */ 487 488 /*! @name PICPDSR - Port ingress congestion priority discard status register */ 489 /*! @{ */ 490 491 #define NETC_F3_PICPDSR_DR0_P0DS_MASK (0x1U) 492 #define NETC_F3_PICPDSR_DR0_P0DS_SHIFT (0U) 493 #define NETC_F3_PICPDSR_DR0_P0DS_WIDTH (1U) 494 #define NETC_F3_PICPDSR_DR0_P0DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PICPDSR_DR0_P0DS_SHIFT)) & NETC_F3_PICPDSR_DR0_P0DS_MASK) 495 496 #define NETC_F3_PICPDSR_DR0_P1DS_MASK (0x10U) 497 #define NETC_F3_PICPDSR_DR0_P1DS_SHIFT (4U) 498 #define NETC_F3_PICPDSR_DR0_P1DS_WIDTH (1U) 499 #define NETC_F3_PICPDSR_DR0_P1DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PICPDSR_DR0_P1DS_SHIFT)) & NETC_F3_PICPDSR_DR0_P1DS_MASK) 500 501 #define NETC_F3_PICPDSR_DR1_P0DS_MASK (0x100U) 502 #define NETC_F3_PICPDSR_DR1_P0DS_SHIFT (8U) 503 #define NETC_F3_PICPDSR_DR1_P0DS_WIDTH (1U) 504 #define NETC_F3_PICPDSR_DR1_P0DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PICPDSR_DR1_P0DS_SHIFT)) & NETC_F3_PICPDSR_DR1_P0DS_MASK) 505 506 #define NETC_F3_PICPDSR_DR1_P1DS_MASK (0x1000U) 507 #define NETC_F3_PICPDSR_DR1_P1DS_SHIFT (12U) 508 #define NETC_F3_PICPDSR_DR1_P1DS_WIDTH (1U) 509 #define NETC_F3_PICPDSR_DR1_P1DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PICPDSR_DR1_P1DS_SHIFT)) & NETC_F3_PICPDSR_DR1_P1DS_MASK) 510 511 #define NETC_F3_PICPDSR_DR2_P0DS_MASK (0x10000U) 512 #define NETC_F3_PICPDSR_DR2_P0DS_SHIFT (16U) 513 #define NETC_F3_PICPDSR_DR2_P0DS_WIDTH (1U) 514 #define NETC_F3_PICPDSR_DR2_P0DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PICPDSR_DR2_P0DS_SHIFT)) & NETC_F3_PICPDSR_DR2_P0DS_MASK) 515 516 #define NETC_F3_PICPDSR_DR2_P1DS_MASK (0x100000U) 517 #define NETC_F3_PICPDSR_DR2_P1DS_SHIFT (20U) 518 #define NETC_F3_PICPDSR_DR2_P1DS_WIDTH (1U) 519 #define NETC_F3_PICPDSR_DR2_P1DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PICPDSR_DR2_P1DS_SHIFT)) & NETC_F3_PICPDSR_DR2_P1DS_MASK) 520 521 #define NETC_F3_PICPDSR_DR3_P0DS_MASK (0x1000000U) 522 #define NETC_F3_PICPDSR_DR3_P0DS_SHIFT (24U) 523 #define NETC_F3_PICPDSR_DR3_P0DS_WIDTH (1U) 524 #define NETC_F3_PICPDSR_DR3_P0DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PICPDSR_DR3_P0DS_SHIFT)) & NETC_F3_PICPDSR_DR3_P0DS_MASK) 525 526 #define NETC_F3_PICPDSR_DR3_P1DS_MASK (0x10000000U) 527 #define NETC_F3_PICPDSR_DR3_P1DS_SHIFT (28U) 528 #define NETC_F3_PICPDSR_DR3_P1DS_WIDTH (1U) 529 #define NETC_F3_PICPDSR_DR3_P1DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PICPDSR_DR3_P1DS_SHIFT)) & NETC_F3_PICPDSR_DR3_P1DS_MASK) 530 /*! @} */ 531 532 /*! @name PSIPMMR - Port station interface promiscuous MAC mode register */ 533 /*! @{ */ 534 535 #define NETC_F3_PSIPMMR_SI0_MAC_UP_MASK (0x1U) 536 #define NETC_F3_PSIPMMR_SI0_MAC_UP_SHIFT (0U) 537 #define NETC_F3_PSIPMMR_SI0_MAC_UP_WIDTH (1U) 538 #define NETC_F3_PSIPMMR_SI0_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI0_MAC_UP_SHIFT)) & NETC_F3_PSIPMMR_SI0_MAC_UP_MASK) 539 540 #define NETC_F3_PSIPMMR_SI1_MAC_UP_MASK (0x2U) 541 #define NETC_F3_PSIPMMR_SI1_MAC_UP_SHIFT (1U) 542 #define NETC_F3_PSIPMMR_SI1_MAC_UP_WIDTH (1U) 543 #define NETC_F3_PSIPMMR_SI1_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI1_MAC_UP_SHIFT)) & NETC_F3_PSIPMMR_SI1_MAC_UP_MASK) 544 545 #define NETC_F3_PSIPMMR_SI2_MAC_UP_MASK (0x4U) 546 #define NETC_F3_PSIPMMR_SI2_MAC_UP_SHIFT (2U) 547 #define NETC_F3_PSIPMMR_SI2_MAC_UP_WIDTH (1U) 548 #define NETC_F3_PSIPMMR_SI2_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI2_MAC_UP_SHIFT)) & NETC_F3_PSIPMMR_SI2_MAC_UP_MASK) 549 550 #define NETC_F3_PSIPMMR_SI3_MAC_UP_MASK (0x8U) 551 #define NETC_F3_PSIPMMR_SI3_MAC_UP_SHIFT (3U) 552 #define NETC_F3_PSIPMMR_SI3_MAC_UP_WIDTH (1U) 553 #define NETC_F3_PSIPMMR_SI3_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI3_MAC_UP_SHIFT)) & NETC_F3_PSIPMMR_SI3_MAC_UP_MASK) 554 555 #define NETC_F3_PSIPMMR_SI4_MAC_UP_MASK (0x10U) 556 #define NETC_F3_PSIPMMR_SI4_MAC_UP_SHIFT (4U) 557 #define NETC_F3_PSIPMMR_SI4_MAC_UP_WIDTH (1U) 558 #define NETC_F3_PSIPMMR_SI4_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI4_MAC_UP_SHIFT)) & NETC_F3_PSIPMMR_SI4_MAC_UP_MASK) 559 560 #define NETC_F3_PSIPMMR_SI5_MAC_UP_MASK (0x20U) 561 #define NETC_F3_PSIPMMR_SI5_MAC_UP_SHIFT (5U) 562 #define NETC_F3_PSIPMMR_SI5_MAC_UP_WIDTH (1U) 563 #define NETC_F3_PSIPMMR_SI5_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI5_MAC_UP_SHIFT)) & NETC_F3_PSIPMMR_SI5_MAC_UP_MASK) 564 565 #define NETC_F3_PSIPMMR_SI6_MAC_UP_MASK (0x40U) 566 #define NETC_F3_PSIPMMR_SI6_MAC_UP_SHIFT (6U) 567 #define NETC_F3_PSIPMMR_SI6_MAC_UP_WIDTH (1U) 568 #define NETC_F3_PSIPMMR_SI6_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI6_MAC_UP_SHIFT)) & NETC_F3_PSIPMMR_SI6_MAC_UP_MASK) 569 570 #define NETC_F3_PSIPMMR_SI7_MAC_UP_MASK (0x80U) 571 #define NETC_F3_PSIPMMR_SI7_MAC_UP_SHIFT (7U) 572 #define NETC_F3_PSIPMMR_SI7_MAC_UP_WIDTH (1U) 573 #define NETC_F3_PSIPMMR_SI7_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI7_MAC_UP_SHIFT)) & NETC_F3_PSIPMMR_SI7_MAC_UP_MASK) 574 575 #define NETC_F3_PSIPMMR_SI0_MAC_MP_MASK (0x10000U) 576 #define NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT (16U) 577 #define NETC_F3_PSIPMMR_SI0_MAC_MP_WIDTH (1U) 578 #define NETC_F3_PSIPMMR_SI0_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI0_MAC_MP_SHIFT)) & NETC_F3_PSIPMMR_SI0_MAC_MP_MASK) 579 580 #define NETC_F3_PSIPMMR_SI1_MAC_MP_MASK (0x20000U) 581 #define NETC_F3_PSIPMMR_SI1_MAC_MP_SHIFT (17U) 582 #define NETC_F3_PSIPMMR_SI1_MAC_MP_WIDTH (1U) 583 #define NETC_F3_PSIPMMR_SI1_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI1_MAC_MP_SHIFT)) & NETC_F3_PSIPMMR_SI1_MAC_MP_MASK) 584 585 #define NETC_F3_PSIPMMR_SI2_MAC_MP_MASK (0x40000U) 586 #define NETC_F3_PSIPMMR_SI2_MAC_MP_SHIFT (18U) 587 #define NETC_F3_PSIPMMR_SI2_MAC_MP_WIDTH (1U) 588 #define NETC_F3_PSIPMMR_SI2_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI2_MAC_MP_SHIFT)) & NETC_F3_PSIPMMR_SI2_MAC_MP_MASK) 589 590 #define NETC_F3_PSIPMMR_SI3_MAC_MP_MASK (0x80000U) 591 #define NETC_F3_PSIPMMR_SI3_MAC_MP_SHIFT (19U) 592 #define NETC_F3_PSIPMMR_SI3_MAC_MP_WIDTH (1U) 593 #define NETC_F3_PSIPMMR_SI3_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI3_MAC_MP_SHIFT)) & NETC_F3_PSIPMMR_SI3_MAC_MP_MASK) 594 595 #define NETC_F3_PSIPMMR_SI4_MAC_MP_MASK (0x100000U) 596 #define NETC_F3_PSIPMMR_SI4_MAC_MP_SHIFT (20U) 597 #define NETC_F3_PSIPMMR_SI4_MAC_MP_WIDTH (1U) 598 #define NETC_F3_PSIPMMR_SI4_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI4_MAC_MP_SHIFT)) & NETC_F3_PSIPMMR_SI4_MAC_MP_MASK) 599 600 #define NETC_F3_PSIPMMR_SI5_MAC_MP_MASK (0x200000U) 601 #define NETC_F3_PSIPMMR_SI5_MAC_MP_SHIFT (21U) 602 #define NETC_F3_PSIPMMR_SI5_MAC_MP_WIDTH (1U) 603 #define NETC_F3_PSIPMMR_SI5_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI5_MAC_MP_SHIFT)) & NETC_F3_PSIPMMR_SI5_MAC_MP_MASK) 604 605 #define NETC_F3_PSIPMMR_SI6_MAC_MP_MASK (0x400000U) 606 #define NETC_F3_PSIPMMR_SI6_MAC_MP_SHIFT (22U) 607 #define NETC_F3_PSIPMMR_SI6_MAC_MP_WIDTH (1U) 608 #define NETC_F3_PSIPMMR_SI6_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI6_MAC_MP_SHIFT)) & NETC_F3_PSIPMMR_SI6_MAC_MP_MASK) 609 610 #define NETC_F3_PSIPMMR_SI7_MAC_MP_MASK (0x800000U) 611 #define NETC_F3_PSIPMMR_SI7_MAC_MP_SHIFT (23U) 612 #define NETC_F3_PSIPMMR_SI7_MAC_MP_WIDTH (1U) 613 #define NETC_F3_PSIPMMR_SI7_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMMR_SI7_MAC_MP_SHIFT)) & NETC_F3_PSIPMMR_SI7_MAC_MP_MASK) 614 /*! @} */ 615 616 /*! @name PSIPVMR - Port station interface promiscuous VLAN mode register */ 617 /*! @{ */ 618 619 #define NETC_F3_PSIPVMR_SI0_VLAN_P_MASK (0x1U) 620 #define NETC_F3_PSIPVMR_SI0_VLAN_P_SHIFT (0U) 621 #define NETC_F3_PSIPVMR_SI0_VLAN_P_WIDTH (1U) 622 #define NETC_F3_PSIPVMR_SI0_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI0_VLAN_P_SHIFT)) & NETC_F3_PSIPVMR_SI0_VLAN_P_MASK) 623 624 #define NETC_F3_PSIPVMR_SI1_VLAN_P_MASK (0x2U) 625 #define NETC_F3_PSIPVMR_SI1_VLAN_P_SHIFT (1U) 626 #define NETC_F3_PSIPVMR_SI1_VLAN_P_WIDTH (1U) 627 #define NETC_F3_PSIPVMR_SI1_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI1_VLAN_P_SHIFT)) & NETC_F3_PSIPVMR_SI1_VLAN_P_MASK) 628 629 #define NETC_F3_PSIPVMR_SI2_VLAN_P_MASK (0x4U) 630 #define NETC_F3_PSIPVMR_SI2_VLAN_P_SHIFT (2U) 631 #define NETC_F3_PSIPVMR_SI2_VLAN_P_WIDTH (1U) 632 #define NETC_F3_PSIPVMR_SI2_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI2_VLAN_P_SHIFT)) & NETC_F3_PSIPVMR_SI2_VLAN_P_MASK) 633 634 #define NETC_F3_PSIPVMR_SI3_VLAN_P_MASK (0x8U) 635 #define NETC_F3_PSIPVMR_SI3_VLAN_P_SHIFT (3U) 636 #define NETC_F3_PSIPVMR_SI3_VLAN_P_WIDTH (1U) 637 #define NETC_F3_PSIPVMR_SI3_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI3_VLAN_P_SHIFT)) & NETC_F3_PSIPVMR_SI3_VLAN_P_MASK) 638 639 #define NETC_F3_PSIPVMR_SI4_VLAN_P_MASK (0x10U) 640 #define NETC_F3_PSIPVMR_SI4_VLAN_P_SHIFT (4U) 641 #define NETC_F3_PSIPVMR_SI4_VLAN_P_WIDTH (1U) 642 #define NETC_F3_PSIPVMR_SI4_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI4_VLAN_P_SHIFT)) & NETC_F3_PSIPVMR_SI4_VLAN_P_MASK) 643 644 #define NETC_F3_PSIPVMR_SI5_VLAN_P_MASK (0x20U) 645 #define NETC_F3_PSIPVMR_SI5_VLAN_P_SHIFT (5U) 646 #define NETC_F3_PSIPVMR_SI5_VLAN_P_WIDTH (1U) 647 #define NETC_F3_PSIPVMR_SI5_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI5_VLAN_P_SHIFT)) & NETC_F3_PSIPVMR_SI5_VLAN_P_MASK) 648 649 #define NETC_F3_PSIPVMR_SI6_VLAN_P_MASK (0x40U) 650 #define NETC_F3_PSIPVMR_SI6_VLAN_P_SHIFT (6U) 651 #define NETC_F3_PSIPVMR_SI6_VLAN_P_WIDTH (1U) 652 #define NETC_F3_PSIPVMR_SI6_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI6_VLAN_P_SHIFT)) & NETC_F3_PSIPVMR_SI6_VLAN_P_MASK) 653 654 #define NETC_F3_PSIPVMR_SI7_VLAN_P_MASK (0x80U) 655 #define NETC_F3_PSIPVMR_SI7_VLAN_P_SHIFT (7U) 656 #define NETC_F3_PSIPVMR_SI7_VLAN_P_WIDTH (1U) 657 #define NETC_F3_PSIPVMR_SI7_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI7_VLAN_P_SHIFT)) & NETC_F3_PSIPVMR_SI7_VLAN_P_MASK) 658 659 #define NETC_F3_PSIPVMR_SI0_VLAN_UTA_MASK (0x10000U) 660 #define NETC_F3_PSIPVMR_SI0_VLAN_UTA_SHIFT (16U) 661 #define NETC_F3_PSIPVMR_SI0_VLAN_UTA_WIDTH (1U) 662 #define NETC_F3_PSIPVMR_SI0_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI0_VLAN_UTA_SHIFT)) & NETC_F3_PSIPVMR_SI0_VLAN_UTA_MASK) 663 664 #define NETC_F3_PSIPVMR_SI1_VLAN_UTA_MASK (0x20000U) 665 #define NETC_F3_PSIPVMR_SI1_VLAN_UTA_SHIFT (17U) 666 #define NETC_F3_PSIPVMR_SI1_VLAN_UTA_WIDTH (1U) 667 #define NETC_F3_PSIPVMR_SI1_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI1_VLAN_UTA_SHIFT)) & NETC_F3_PSIPVMR_SI1_VLAN_UTA_MASK) 668 669 #define NETC_F3_PSIPVMR_SI2_VLAN_UTA_MASK (0x40000U) 670 #define NETC_F3_PSIPVMR_SI2_VLAN_UTA_SHIFT (18U) 671 #define NETC_F3_PSIPVMR_SI2_VLAN_UTA_WIDTH (1U) 672 #define NETC_F3_PSIPVMR_SI2_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI2_VLAN_UTA_SHIFT)) & NETC_F3_PSIPVMR_SI2_VLAN_UTA_MASK) 673 674 #define NETC_F3_PSIPVMR_SI3_VLAN_UTA_MASK (0x80000U) 675 #define NETC_F3_PSIPVMR_SI3_VLAN_UTA_SHIFT (19U) 676 #define NETC_F3_PSIPVMR_SI3_VLAN_UTA_WIDTH (1U) 677 #define NETC_F3_PSIPVMR_SI3_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI3_VLAN_UTA_SHIFT)) & NETC_F3_PSIPVMR_SI3_VLAN_UTA_MASK) 678 679 #define NETC_F3_PSIPVMR_SI4_VLAN_UTA_MASK (0x100000U) 680 #define NETC_F3_PSIPVMR_SI4_VLAN_UTA_SHIFT (20U) 681 #define NETC_F3_PSIPVMR_SI4_VLAN_UTA_WIDTH (1U) 682 #define NETC_F3_PSIPVMR_SI4_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI4_VLAN_UTA_SHIFT)) & NETC_F3_PSIPVMR_SI4_VLAN_UTA_MASK) 683 684 #define NETC_F3_PSIPVMR_SI5_VLAN_UTA_MASK (0x200000U) 685 #define NETC_F3_PSIPVMR_SI5_VLAN_UTA_SHIFT (21U) 686 #define NETC_F3_PSIPVMR_SI5_VLAN_UTA_WIDTH (1U) 687 #define NETC_F3_PSIPVMR_SI5_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI5_VLAN_UTA_SHIFT)) & NETC_F3_PSIPVMR_SI5_VLAN_UTA_MASK) 688 689 #define NETC_F3_PSIPVMR_SI6_VLAN_UTA_MASK (0x400000U) 690 #define NETC_F3_PSIPVMR_SI6_VLAN_UTA_SHIFT (22U) 691 #define NETC_F3_PSIPVMR_SI6_VLAN_UTA_WIDTH (1U) 692 #define NETC_F3_PSIPVMR_SI6_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI6_VLAN_UTA_SHIFT)) & NETC_F3_PSIPVMR_SI6_VLAN_UTA_MASK) 693 694 #define NETC_F3_PSIPVMR_SI7_VLAN_UTA_MASK (0x800000U) 695 #define NETC_F3_PSIPVMR_SI7_VLAN_UTA_SHIFT (23U) 696 #define NETC_F3_PSIPVMR_SI7_VLAN_UTA_WIDTH (1U) 697 #define NETC_F3_PSIPVMR_SI7_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPVMR_SI7_VLAN_UTA_SHIFT)) & NETC_F3_PSIPVMR_SI7_VLAN_UTA_MASK) 698 /*! @} */ 699 700 /*! @name PBFDSIR - Port broadcast frames dropped due to MAC filtering register */ 701 /*! @{ */ 702 703 #define NETC_F3_PBFDSIR_FRAME_DROP_MASK (0xFFFFFFFFU) 704 #define NETC_F3_PBFDSIR_FRAME_DROP_SHIFT (0U) 705 #define NETC_F3_PBFDSIR_FRAME_DROP_WIDTH (32U) 706 #define NETC_F3_PBFDSIR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PBFDSIR_FRAME_DROP_SHIFT)) & NETC_F3_PBFDSIR_FRAME_DROP_MASK) 707 /*! @} */ 708 709 /*! @name PFDMSAPR - Port frame drop MAC source address pruning register */ 710 /*! @{ */ 711 712 #define NETC_F3_PFDMSAPR_FRAME_DROP_MASK (0xFFFFFFFFU) 713 #define NETC_F3_PFDMSAPR_FRAME_DROP_SHIFT (0U) 714 #define NETC_F3_PFDMSAPR_FRAME_DROP_WIDTH (32U) 715 #define NETC_F3_PFDMSAPR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PFDMSAPR_FRAME_DROP_SHIFT)) & NETC_F3_PFDMSAPR_FRAME_DROP_MASK) 716 /*! @} */ 717 718 /*! @name PSIMAFCAPR - Port station interface MAC address filtering capability register */ 719 /*! @{ */ 720 721 #define NETC_F3_PSIMAFCAPR_NUM_MAC_AFTE_MASK (0xFFFU) 722 #define NETC_F3_PSIMAFCAPR_NUM_MAC_AFTE_SHIFT (0U) 723 #define NETC_F3_PSIMAFCAPR_NUM_MAC_AFTE_WIDTH (12U) 724 #define NETC_F3_PSIMAFCAPR_NUM_MAC_AFTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIMAFCAPR_NUM_MAC_AFTE_SHIFT)) & NETC_F3_PSIMAFCAPR_NUM_MAC_AFTE_MASK) 725 /*! @} */ 726 727 /*! @name PUFDMFR - Port unicast frames dropped due to MAC filtering register */ 728 /*! @{ */ 729 730 #define NETC_F3_PUFDMFR_FRAME_DROP_MASK (0xFFFFFFFFU) 731 #define NETC_F3_PUFDMFR_FRAME_DROP_SHIFT (0U) 732 #define NETC_F3_PUFDMFR_FRAME_DROP_WIDTH (32U) 733 #define NETC_F3_PUFDMFR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PUFDMFR_FRAME_DROP_SHIFT)) & NETC_F3_PUFDMFR_FRAME_DROP_MASK) 734 /*! @} */ 735 736 /*! @name PMFDMFR - Port multicast frames dropped due to MAC filtering register */ 737 /*! @{ */ 738 739 #define NETC_F3_PMFDMFR_FRAME_DROP_MASK (0xFFFFFFFFU) 740 #define NETC_F3_PMFDMFR_FRAME_DROP_SHIFT (0U) 741 #define NETC_F3_PMFDMFR_FRAME_DROP_WIDTH (32U) 742 #define NETC_F3_PMFDMFR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PMFDMFR_FRAME_DROP_SHIFT)) & NETC_F3_PMFDMFR_FRAME_DROP_MASK) 743 /*! @} */ 744 745 /*! @name PSIVLANFCAPR - Port station interface VLAN filtering capability register */ 746 /*! @{ */ 747 748 #define NETC_F3_PSIVLANFCAPR_NUM_VLAN_FTE_MASK (0xFFFU) 749 #define NETC_F3_PSIVLANFCAPR_NUM_VLAN_FTE_SHIFT (0U) 750 #define NETC_F3_PSIVLANFCAPR_NUM_VLAN_FTE_WIDTH (12U) 751 #define NETC_F3_PSIVLANFCAPR_NUM_VLAN_FTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIVLANFCAPR_NUM_VLAN_FTE_SHIFT)) & NETC_F3_PSIVLANFCAPR_NUM_VLAN_FTE_MASK) 752 /*! @} */ 753 754 /*! @name PSIVLANFMR - Port station interface VLAN filtering mode register */ 755 /*! @{ */ 756 757 #define NETC_F3_PSIVLANFMR_VS_MASK (0x1U) 758 #define NETC_F3_PSIVLANFMR_VS_SHIFT (0U) 759 #define NETC_F3_PSIVLANFMR_VS_WIDTH (1U) 760 #define NETC_F3_PSIVLANFMR_VS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIVLANFMR_VS_SHIFT)) & NETC_F3_PSIVLANFMR_VS_MASK) 761 /*! @} */ 762 763 /*! @name PUFDVFR - Port unicast frames dropped VLAN filtering register */ 764 /*! @{ */ 765 766 #define NETC_F3_PUFDVFR_FRAME_DROP_MASK (0xFFFFFFFFU) 767 #define NETC_F3_PUFDVFR_FRAME_DROP_SHIFT (0U) 768 #define NETC_F3_PUFDVFR_FRAME_DROP_WIDTH (32U) 769 #define NETC_F3_PUFDVFR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PUFDVFR_FRAME_DROP_SHIFT)) & NETC_F3_PUFDVFR_FRAME_DROP_MASK) 770 /*! @} */ 771 772 /*! @name PMFDVFR - Port multicast frames dropped VLAN filtering register */ 773 /*! @{ */ 774 775 #define NETC_F3_PMFDVFR_FRAME_DROP_MASK (0xFFFFFFFFU) 776 #define NETC_F3_PMFDVFR_FRAME_DROP_SHIFT (0U) 777 #define NETC_F3_PMFDVFR_FRAME_DROP_WIDTH (32U) 778 #define NETC_F3_PMFDVFR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PMFDVFR_FRAME_DROP_SHIFT)) & NETC_F3_PMFDVFR_FRAME_DROP_MASK) 779 /*! @} */ 780 781 /*! @name PBFDVFR - Port broadcast frames dropped VLAN filtering register */ 782 /*! @{ */ 783 784 #define NETC_F3_PBFDVFR_FRAME_DROP_MASK (0xFFFFFFFFU) 785 #define NETC_F3_PBFDVFR_FRAME_DROP_SHIFT (0U) 786 #define NETC_F3_PBFDVFR_FRAME_DROP_WIDTH (32U) 787 #define NETC_F3_PBFDVFR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PBFDVFR_FRAME_DROP_SHIFT)) & NETC_F3_PBFDVFR_FRAME_DROP_MASK) 788 /*! @} */ 789 790 /*! @name PRFSCAPR - Port RFS capability register */ 791 /*! @{ */ 792 793 #define NETC_F3_PRFSCAPR_NUM_RFS_MASK (0xFFU) 794 #define NETC_F3_PRFSCAPR_NUM_RFS_SHIFT (0U) 795 #define NETC_F3_PRFSCAPR_NUM_RFS_WIDTH (8U) 796 #define NETC_F3_PRFSCAPR_NUM_RFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRFSCAPR_NUM_RFS_SHIFT)) & NETC_F3_PRFSCAPR_NUM_RFS_MASK) 797 /*! @} */ 798 799 /*! @name PRFSMR - Port RFS mode register */ 800 /*! @{ */ 801 802 #define NETC_F3_PRFSMR_RFSE_MASK (0x80000000U) 803 #define NETC_F3_PRFSMR_RFSE_SHIFT (31U) 804 #define NETC_F3_PRFSMR_RFSE_WIDTH (1U) 805 #define NETC_F3_PRFSMR_RFSE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRFSMR_RFSE_SHIFT)) & NETC_F3_PRFSMR_RFSE_MASK) 806 /*! @} */ 807 808 /*! @name IPV2ICMPMR0 - Receive IPV to ICM priority mapping register 0 */ 809 /*! @{ */ 810 811 #define NETC_F3_IPV2ICMPMR0_IPV0ICM_MASK (0x1U) 812 #define NETC_F3_IPV2ICMPMR0_IPV0ICM_SHIFT (0U) 813 #define NETC_F3_IPV2ICMPMR0_IPV0ICM_WIDTH (1U) 814 #define NETC_F3_IPV2ICMPMR0_IPV0ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_IPV2ICMPMR0_IPV0ICM_SHIFT)) & NETC_F3_IPV2ICMPMR0_IPV0ICM_MASK) 815 816 #define NETC_F3_IPV2ICMPMR0_IPV1ICM_MASK (0x10U) 817 #define NETC_F3_IPV2ICMPMR0_IPV1ICM_SHIFT (4U) 818 #define NETC_F3_IPV2ICMPMR0_IPV1ICM_WIDTH (1U) 819 #define NETC_F3_IPV2ICMPMR0_IPV1ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_IPV2ICMPMR0_IPV1ICM_SHIFT)) & NETC_F3_IPV2ICMPMR0_IPV1ICM_MASK) 820 821 #define NETC_F3_IPV2ICMPMR0_IPV2ICM_MASK (0x100U) 822 #define NETC_F3_IPV2ICMPMR0_IPV2ICM_SHIFT (8U) 823 #define NETC_F3_IPV2ICMPMR0_IPV2ICM_WIDTH (1U) 824 #define NETC_F3_IPV2ICMPMR0_IPV2ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_IPV2ICMPMR0_IPV2ICM_SHIFT)) & NETC_F3_IPV2ICMPMR0_IPV2ICM_MASK) 825 826 #define NETC_F3_IPV2ICMPMR0_IPV3ICM_MASK (0x1000U) 827 #define NETC_F3_IPV2ICMPMR0_IPV3ICM_SHIFT (12U) 828 #define NETC_F3_IPV2ICMPMR0_IPV3ICM_WIDTH (1U) 829 #define NETC_F3_IPV2ICMPMR0_IPV3ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_IPV2ICMPMR0_IPV3ICM_SHIFT)) & NETC_F3_IPV2ICMPMR0_IPV3ICM_MASK) 830 831 #define NETC_F3_IPV2ICMPMR0_IPV4ICM_MASK (0x10000U) 832 #define NETC_F3_IPV2ICMPMR0_IPV4ICM_SHIFT (16U) 833 #define NETC_F3_IPV2ICMPMR0_IPV4ICM_WIDTH (1U) 834 #define NETC_F3_IPV2ICMPMR0_IPV4ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_IPV2ICMPMR0_IPV4ICM_SHIFT)) & NETC_F3_IPV2ICMPMR0_IPV4ICM_MASK) 835 836 #define NETC_F3_IPV2ICMPMR0_IPV5ICM_MASK (0x100000U) 837 #define NETC_F3_IPV2ICMPMR0_IPV5ICM_SHIFT (20U) 838 #define NETC_F3_IPV2ICMPMR0_IPV5ICM_WIDTH (1U) 839 #define NETC_F3_IPV2ICMPMR0_IPV5ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_IPV2ICMPMR0_IPV5ICM_SHIFT)) & NETC_F3_IPV2ICMPMR0_IPV5ICM_MASK) 840 841 #define NETC_F3_IPV2ICMPMR0_IPV6ICM_MASK (0x1000000U) 842 #define NETC_F3_IPV2ICMPMR0_IPV6ICM_SHIFT (24U) 843 #define NETC_F3_IPV2ICMPMR0_IPV6ICM_WIDTH (1U) 844 #define NETC_F3_IPV2ICMPMR0_IPV6ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_IPV2ICMPMR0_IPV6ICM_SHIFT)) & NETC_F3_IPV2ICMPMR0_IPV6ICM_MASK) 845 846 #define NETC_F3_IPV2ICMPMR0_IPV7ICM_MASK (0x10000000U) 847 #define NETC_F3_IPV2ICMPMR0_IPV7ICM_SHIFT (28U) 848 #define NETC_F3_IPV2ICMPMR0_IPV7ICM_WIDTH (1U) 849 #define NETC_F3_IPV2ICMPMR0_IPV7ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_IPV2ICMPMR0_IPV7ICM_SHIFT)) & NETC_F3_IPV2ICMPMR0_IPV7ICM_MASK) 850 /*! @} */ 851 852 /*! @name PRIO2TCMR0 - Transmit priority to traffic class mapping register 0 */ 853 /*! @{ */ 854 855 #define NETC_F3_PRIO2TCMR0_PRIO0TC_MASK (0x7U) 856 #define NETC_F3_PRIO2TCMR0_PRIO0TC_SHIFT (0U) 857 #define NETC_F3_PRIO2TCMR0_PRIO0TC_WIDTH (3U) 858 #define NETC_F3_PRIO2TCMR0_PRIO0TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRIO2TCMR0_PRIO0TC_SHIFT)) & NETC_F3_PRIO2TCMR0_PRIO0TC_MASK) 859 860 #define NETC_F3_PRIO2TCMR0_PRIO1TC_MASK (0x70U) 861 #define NETC_F3_PRIO2TCMR0_PRIO1TC_SHIFT (4U) 862 #define NETC_F3_PRIO2TCMR0_PRIO1TC_WIDTH (3U) 863 #define NETC_F3_PRIO2TCMR0_PRIO1TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRIO2TCMR0_PRIO1TC_SHIFT)) & NETC_F3_PRIO2TCMR0_PRIO1TC_MASK) 864 865 #define NETC_F3_PRIO2TCMR0_PRIO2TC_MASK (0x700U) 866 #define NETC_F3_PRIO2TCMR0_PRIO2TC_SHIFT (8U) 867 #define NETC_F3_PRIO2TCMR0_PRIO2TC_WIDTH (3U) 868 #define NETC_F3_PRIO2TCMR0_PRIO2TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRIO2TCMR0_PRIO2TC_SHIFT)) & NETC_F3_PRIO2TCMR0_PRIO2TC_MASK) 869 870 #define NETC_F3_PRIO2TCMR0_PRIO3TC_MASK (0x7000U) 871 #define NETC_F3_PRIO2TCMR0_PRIO3TC_SHIFT (12U) 872 #define NETC_F3_PRIO2TCMR0_PRIO3TC_WIDTH (3U) 873 #define NETC_F3_PRIO2TCMR0_PRIO3TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRIO2TCMR0_PRIO3TC_SHIFT)) & NETC_F3_PRIO2TCMR0_PRIO3TC_MASK) 874 875 #define NETC_F3_PRIO2TCMR0_PRIO4TC_MASK (0x70000U) 876 #define NETC_F3_PRIO2TCMR0_PRIO4TC_SHIFT (16U) 877 #define NETC_F3_PRIO2TCMR0_PRIO4TC_WIDTH (3U) 878 #define NETC_F3_PRIO2TCMR0_PRIO4TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRIO2TCMR0_PRIO4TC_SHIFT)) & NETC_F3_PRIO2TCMR0_PRIO4TC_MASK) 879 880 #define NETC_F3_PRIO2TCMR0_PRIO5TC_MASK (0x700000U) 881 #define NETC_F3_PRIO2TCMR0_PRIO5TC_SHIFT (20U) 882 #define NETC_F3_PRIO2TCMR0_PRIO5TC_WIDTH (3U) 883 #define NETC_F3_PRIO2TCMR0_PRIO5TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRIO2TCMR0_PRIO5TC_SHIFT)) & NETC_F3_PRIO2TCMR0_PRIO5TC_MASK) 884 885 #define NETC_F3_PRIO2TCMR0_PRIO6TC_MASK (0x7000000U) 886 #define NETC_F3_PRIO2TCMR0_PRIO6TC_SHIFT (24U) 887 #define NETC_F3_PRIO2TCMR0_PRIO6TC_WIDTH (3U) 888 #define NETC_F3_PRIO2TCMR0_PRIO6TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRIO2TCMR0_PRIO6TC_SHIFT)) & NETC_F3_PRIO2TCMR0_PRIO6TC_MASK) 889 890 #define NETC_F3_PRIO2TCMR0_PRIO7TC_MASK (0x70000000U) 891 #define NETC_F3_PRIO2TCMR0_PRIO7TC_SHIFT (28U) 892 #define NETC_F3_PRIO2TCMR0_PRIO7TC_WIDTH (3U) 893 #define NETC_F3_PRIO2TCMR0_PRIO7TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PRIO2TCMR0_PRIO7TC_SHIFT)) & NETC_F3_PRIO2TCMR0_PRIO7TC_MASK) 894 /*! @} */ 895 896 /*! @name PTCTSDR - Port traffic class 0 time specific departure register..Port traffic class 7 time specific departure register */ 897 /*! @{ */ 898 899 #define NETC_F3_PTCTSDR_TSDE_MASK (0x80000000U) 900 #define NETC_F3_PTCTSDR_TSDE_SHIFT (31U) 901 #define NETC_F3_PTCTSDR_TSDE_WIDTH (1U) 902 #define NETC_F3_PTCTSDR_TSDE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PTCTSDR_TSDE_SHIFT)) & NETC_F3_PTCTSDR_TSDE_MASK) 903 /*! @} */ 904 905 /*! @name SMCAPR - Switch management capability register */ 906 /*! @{ */ 907 908 #define NETC_F3_SMCAPR_SM_MASK (0x1U) 909 #define NETC_F3_SMCAPR_SM_SHIFT (0U) 910 #define NETC_F3_SMCAPR_SM_WIDTH (1U) 911 #define NETC_F3_SMCAPR_SM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SMCAPR_SM_SHIFT)) & NETC_F3_SMCAPR_SM_MASK) 912 /*! @} */ 913 914 /*! @name SMHRBDRMR - Switch management host reason 1 receive BD ring mapping register..Switch management host reason 15 receive BD ring mapping register */ 915 /*! @{ */ 916 917 #define NETC_F3_SMHRBDRMR_RXBDR_MASK (0xFFU) 918 #define NETC_F3_SMHRBDRMR_RXBDR_SHIFT (0U) 919 #define NETC_F3_SMHRBDRMR_RXBDR_WIDTH (8U) 920 #define NETC_F3_SMHRBDRMR_RXBDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_SMHRBDRMR_RXBDR_SHIFT)) & NETC_F3_SMHRBDRMR_RXBDR_MASK) 921 /*! @} */ 922 923 /*! @name PSIPMAR0 - Port station interface 0 primary MAC address register 0..Port station interface 7 primary MAC address register 0 */ 924 /*! @{ */ 925 926 #define NETC_F3_PSIPMAR0_PRIM_MAC_ADDR_MASK (0xFFFFFFFFU) 927 #define NETC_F3_PSIPMAR0_PRIM_MAC_ADDR_SHIFT (0U) 928 #define NETC_F3_PSIPMAR0_PRIM_MAC_ADDR_WIDTH (32U) 929 #define NETC_F3_PSIPMAR0_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMAR0_PRIM_MAC_ADDR_SHIFT)) & NETC_F3_PSIPMAR0_PRIM_MAC_ADDR_MASK) 930 /*! @} */ 931 932 /*! @name PSIPMAR1 - Port station interface 0 primary MAC address register 1..Port station interface 7 primary MAC address register 1 */ 933 /*! @{ */ 934 935 #define NETC_F3_PSIPMAR1_PRIM_MAC_ADDR_MASK (0xFFFFU) 936 #define NETC_F3_PSIPMAR1_PRIM_MAC_ADDR_SHIFT (0U) 937 #define NETC_F3_PSIPMAR1_PRIM_MAC_ADDR_WIDTH (16U) 938 #define NETC_F3_PSIPMAR1_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIPMAR1_PRIM_MAC_ADDR_SHIFT)) & NETC_F3_PSIPMAR1_PRIM_MAC_ADDR_MASK) 939 /*! @} */ 940 941 /*! @name PSIVLANR - Port station interface 0 VLAN register..Port station interface 7 VLAN register */ 942 /*! @{ */ 943 944 #define NETC_F3_PSIVLANR_VID_MASK (0xFFFU) 945 #define NETC_F3_PSIVLANR_VID_SHIFT (0U) 946 #define NETC_F3_PSIVLANR_VID_WIDTH (12U) 947 #define NETC_F3_PSIVLANR_VID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIVLANR_VID_SHIFT)) & NETC_F3_PSIVLANR_VID_MASK) 948 949 #define NETC_F3_PSIVLANR_DEI_MASK (0x1000U) 950 #define NETC_F3_PSIVLANR_DEI_SHIFT (12U) 951 #define NETC_F3_PSIVLANR_DEI_WIDTH (1U) 952 #define NETC_F3_PSIVLANR_DEI(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIVLANR_DEI_SHIFT)) & NETC_F3_PSIVLANR_DEI_MASK) 953 954 #define NETC_F3_PSIVLANR_PCP_MASK (0xE000U) 955 #define NETC_F3_PSIVLANR_PCP_SHIFT (13U) 956 #define NETC_F3_PSIVLANR_PCP_WIDTH (3U) 957 #define NETC_F3_PSIVLANR_PCP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIVLANR_PCP_SHIFT)) & NETC_F3_PSIVLANR_PCP_MASK) 958 959 #define NETC_F3_PSIVLANR_TPID_MASK (0x30000U) 960 #define NETC_F3_PSIVLANR_TPID_SHIFT (16U) 961 #define NETC_F3_PSIVLANR_TPID_WIDTH (2U) 962 #define NETC_F3_PSIVLANR_TPID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIVLANR_TPID_SHIFT)) & NETC_F3_PSIVLANR_TPID_MASK) 963 964 #define NETC_F3_PSIVLANR_E_MASK (0x80000000U) 965 #define NETC_F3_PSIVLANR_E_SHIFT (31U) 966 #define NETC_F3_PSIVLANR_E_WIDTH (1U) 967 #define NETC_F3_PSIVLANR_E(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIVLANR_E_SHIFT)) & NETC_F3_PSIVLANR_E_MASK) 968 /*! @} */ 969 970 /*! @name PSICFGR0 - Port station interface 0 configuration register 0..Port station interface 7 configuration register 0 */ 971 /*! @{ */ 972 973 #define NETC_F3_PSICFGR0_NUM_TX_BDR_MASK (0x7FU) 974 #define NETC_F3_PSICFGR0_NUM_TX_BDR_SHIFT (0U) 975 #define NETC_F3_PSICFGR0_NUM_TX_BDR_WIDTH (7U) 976 #define NETC_F3_PSICFGR0_NUM_TX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR0_NUM_TX_BDR_SHIFT)) & NETC_F3_PSICFGR0_NUM_TX_BDR_MASK) 977 978 #define NETC_F3_PSICFGR0_SPE_MASK (0x800U) 979 #define NETC_F3_PSICFGR0_SPE_SHIFT (11U) 980 #define NETC_F3_PSICFGR0_SPE_WIDTH (1U) 981 #define NETC_F3_PSICFGR0_SPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR0_SPE_SHIFT)) & NETC_F3_PSICFGR0_SPE_MASK) 982 983 #define NETC_F3_PSICFGR0_VTE_MASK (0x1000U) 984 #define NETC_F3_PSICFGR0_VTE_SHIFT (12U) 985 #define NETC_F3_PSICFGR0_VTE_WIDTH (1U) 986 #define NETC_F3_PSICFGR0_VTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR0_VTE_SHIFT)) & NETC_F3_PSICFGR0_VTE_MASK) 987 988 #define NETC_F3_PSICFGR0_SIVIE_MASK (0x4000U) 989 #define NETC_F3_PSICFGR0_SIVIE_SHIFT (14U) 990 #define NETC_F3_PSICFGR0_SIVIE_WIDTH (1U) 991 #define NETC_F3_PSICFGR0_SIVIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR0_SIVIE_SHIFT)) & NETC_F3_PSICFGR0_SIVIE_MASK) 992 993 #define NETC_F3_PSICFGR0_ASE_MASK (0x8000U) 994 #define NETC_F3_PSICFGR0_ASE_SHIFT (15U) 995 #define NETC_F3_PSICFGR0_ASE_WIDTH (1U) 996 #define NETC_F3_PSICFGR0_ASE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR0_ASE_SHIFT)) & NETC_F3_PSICFGR0_ASE_MASK) 997 998 #define NETC_F3_PSICFGR0_NUM_RX_BDR_MASK (0x7F0000U) 999 #define NETC_F3_PSICFGR0_NUM_RX_BDR_SHIFT (16U) 1000 #define NETC_F3_PSICFGR0_NUM_RX_BDR_WIDTH (7U) 1001 #define NETC_F3_PSICFGR0_NUM_RX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR0_NUM_RX_BDR_SHIFT)) & NETC_F3_PSICFGR0_NUM_RX_BDR_MASK) 1002 1003 #define NETC_F3_PSICFGR0_SIVC_MASK (0xF000000U) 1004 #define NETC_F3_PSICFGR0_SIVC_SHIFT (24U) 1005 #define NETC_F3_PSICFGR0_SIVC_WIDTH (4U) 1006 #define NETC_F3_PSICFGR0_SIVC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR0_SIVC_SHIFT)) & NETC_F3_PSICFGR0_SIVC_MASK) 1007 1008 #define NETC_F3_PSICFGR0_SIBW_MASK (0xF0000000U) 1009 #define NETC_F3_PSICFGR0_SIBW_SHIFT (28U) 1010 #define NETC_F3_PSICFGR0_SIBW_WIDTH (4U) 1011 #define NETC_F3_PSICFGR0_SIBW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR0_SIBW_SHIFT)) & NETC_F3_PSICFGR0_SIBW_MASK) 1012 /*! @} */ 1013 1014 /*! @name PSICFGR1 - Port station interface 1 configuration register 1..Port station interface 7 configuration register 1 */ 1015 /*! @{ */ 1016 1017 #define NETC_F3_PSICFGR1_TC0_MAP_MASK (0x7U) 1018 #define NETC_F3_PSICFGR1_TC0_MAP_SHIFT (0U) 1019 #define NETC_F3_PSICFGR1_TC0_MAP_WIDTH (3U) 1020 #define NETC_F3_PSICFGR1_TC0_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR1_TC0_MAP_SHIFT)) & NETC_F3_PSICFGR1_TC0_MAP_MASK) 1021 1022 #define NETC_F3_PSICFGR1_TC1_MAP_MASK (0x70U) 1023 #define NETC_F3_PSICFGR1_TC1_MAP_SHIFT (4U) 1024 #define NETC_F3_PSICFGR1_TC1_MAP_WIDTH (3U) 1025 #define NETC_F3_PSICFGR1_TC1_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR1_TC1_MAP_SHIFT)) & NETC_F3_PSICFGR1_TC1_MAP_MASK) 1026 1027 #define NETC_F3_PSICFGR1_TC2_MAP_MASK (0x700U) 1028 #define NETC_F3_PSICFGR1_TC2_MAP_SHIFT (8U) 1029 #define NETC_F3_PSICFGR1_TC2_MAP_WIDTH (3U) 1030 #define NETC_F3_PSICFGR1_TC2_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR1_TC2_MAP_SHIFT)) & NETC_F3_PSICFGR1_TC2_MAP_MASK) 1031 1032 #define NETC_F3_PSICFGR1_TC3_MAP_MASK (0x7000U) 1033 #define NETC_F3_PSICFGR1_TC3_MAP_SHIFT (12U) 1034 #define NETC_F3_PSICFGR1_TC3_MAP_WIDTH (3U) 1035 #define NETC_F3_PSICFGR1_TC3_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR1_TC3_MAP_SHIFT)) & NETC_F3_PSICFGR1_TC3_MAP_MASK) 1036 1037 #define NETC_F3_PSICFGR1_TC4_MAP_MASK (0x70000U) 1038 #define NETC_F3_PSICFGR1_TC4_MAP_SHIFT (16U) 1039 #define NETC_F3_PSICFGR1_TC4_MAP_WIDTH (3U) 1040 #define NETC_F3_PSICFGR1_TC4_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR1_TC4_MAP_SHIFT)) & NETC_F3_PSICFGR1_TC4_MAP_MASK) 1041 1042 #define NETC_F3_PSICFGR1_TC5_MAP_MASK (0x700000U) 1043 #define NETC_F3_PSICFGR1_TC5_MAP_SHIFT (20U) 1044 #define NETC_F3_PSICFGR1_TC5_MAP_WIDTH (3U) 1045 #define NETC_F3_PSICFGR1_TC5_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR1_TC5_MAP_SHIFT)) & NETC_F3_PSICFGR1_TC5_MAP_MASK) 1046 1047 #define NETC_F3_PSICFGR1_TC6_MAP_MASK (0x7000000U) 1048 #define NETC_F3_PSICFGR1_TC6_MAP_SHIFT (24U) 1049 #define NETC_F3_PSICFGR1_TC6_MAP_WIDTH (3U) 1050 #define NETC_F3_PSICFGR1_TC6_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR1_TC6_MAP_SHIFT)) & NETC_F3_PSICFGR1_TC6_MAP_MASK) 1051 1052 #define NETC_F3_PSICFGR1_TC7_MAP_MASK (0x70000000U) 1053 #define NETC_F3_PSICFGR1_TC7_MAP_SHIFT (28U) 1054 #define NETC_F3_PSICFGR1_TC7_MAP_WIDTH (3U) 1055 #define NETC_F3_PSICFGR1_TC7_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR1_TC7_MAP_SHIFT)) & NETC_F3_PSICFGR1_TC7_MAP_MASK) 1056 /*! @} */ 1057 1058 /*! @name PSICFGR2 - Port station interface 0 configuration register 2..Port station interface 7 configuration register 2 */ 1059 /*! @{ */ 1060 1061 #define NETC_F3_PSICFGR2_NUM_MSIX_MASK (0x3FU) 1062 #define NETC_F3_PSICFGR2_NUM_MSIX_SHIFT (0U) 1063 #define NETC_F3_PSICFGR2_NUM_MSIX_WIDTH (6U) 1064 #define NETC_F3_PSICFGR2_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSICFGR2_NUM_MSIX_SHIFT)) & NETC_F3_PSICFGR2_NUM_MSIX_MASK) 1065 /*! @} */ 1066 1067 /*! @name PSIVMAFCFGR - Port station interface 0 VSI MAC address filtering configuration register..Port station interface 7 VSI MAC address filtering configuration register */ 1068 /*! @{ */ 1069 1070 #define NETC_F3_PSIVMAFCFGR_NUM_MAC_AFTE_MASK (0xFFU) 1071 #define NETC_F3_PSIVMAFCFGR_NUM_MAC_AFTE_SHIFT (0U) 1072 #define NETC_F3_PSIVMAFCFGR_NUM_MAC_AFTE_WIDTH (8U) 1073 #define NETC_F3_PSIVMAFCFGR_NUM_MAC_AFTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIVMAFCFGR_NUM_MAC_AFTE_SHIFT)) & NETC_F3_PSIVMAFCFGR_NUM_MAC_AFTE_MASK) 1074 /*! @} */ 1075 1076 /*! @name PSIVLANFCFGR - Port station interface 0 VLAN filtering configuration register..Port station interface 7 VLAN filtering configuration register */ 1077 /*! @{ */ 1078 1079 #define NETC_F3_PSIVLANFCFGR_NUM_VLAN_FTE_MASK (0xFFU) 1080 #define NETC_F3_PSIVLANFCFGR_NUM_VLAN_FTE_SHIFT (0U) 1081 #define NETC_F3_PSIVLANFCFGR_NUM_VLAN_FTE_WIDTH (8U) 1082 #define NETC_F3_PSIVLANFCFGR_NUM_VLAN_FTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIVLANFCFGR_NUM_VLAN_FTE_SHIFT)) & NETC_F3_PSIVLANFCFGR_NUM_VLAN_FTE_MASK) 1083 /*! @} */ 1084 1085 /*! @name PSIRFSCFGR - Port station interface 0 RFS configuration register..Port station interface 7 RFS configuration register */ 1086 /*! @{ */ 1087 1088 #define NETC_F3_PSIRFSCFGR_NUM_RFS_MASK (0x1FFU) 1089 #define NETC_F3_PSIRFSCFGR_NUM_RFS_SHIFT (0U) 1090 #define NETC_F3_PSIRFSCFGR_NUM_RFS_WIDTH (9U) 1091 #define NETC_F3_PSIRFSCFGR_NUM_RFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIRFSCFGR_NUM_RFS_SHIFT)) & NETC_F3_PSIRFSCFGR_NUM_RFS_MASK) 1092 /*! @} */ 1093 1094 /*! @name PSIUMHFR0 - Port station interface 0 unicast MAC hash filter register 0..Port station interface 7 unicast MAC hash filter register 0 */ 1095 /*! @{ */ 1096 1097 #define NETC_F3_PSIUMHFR0_MAC_HASH_FLT_LOW_MASK (0xFFFFFFFFU) 1098 #define NETC_F3_PSIUMHFR0_MAC_HASH_FLT_LOW_SHIFT (0U) 1099 #define NETC_F3_PSIUMHFR0_MAC_HASH_FLT_LOW_WIDTH (32U) 1100 #define NETC_F3_PSIUMHFR0_MAC_HASH_FLT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIUMHFR0_MAC_HASH_FLT_LOW_SHIFT)) & NETC_F3_PSIUMHFR0_MAC_HASH_FLT_LOW_MASK) 1101 /*! @} */ 1102 1103 /*! @name PSIUMHFR1 - Port station interface 0 unicast MAC hash filter register 1..Port station interface 7 unicast MAC hash filter register 1 */ 1104 /*! @{ */ 1105 1106 #define NETC_F3_PSIUMHFR1_MAC_HASH_FLT_HIGH_MASK (0xFFFFFFFFU) 1107 #define NETC_F3_PSIUMHFR1_MAC_HASH_FLT_HIGH_SHIFT (0U) 1108 #define NETC_F3_PSIUMHFR1_MAC_HASH_FLT_HIGH_WIDTH (32U) 1109 #define NETC_F3_PSIUMHFR1_MAC_HASH_FLT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIUMHFR1_MAC_HASH_FLT_HIGH_SHIFT)) & NETC_F3_PSIUMHFR1_MAC_HASH_FLT_HIGH_MASK) 1110 /*! @} */ 1111 1112 /*! @name PSIMMHFR0 - Port station interface 0 multicast MAC hash filter register 0..Port station interface 7 multicast MAC hash filter register 0 */ 1113 /*! @{ */ 1114 1115 #define NETC_F3_PSIMMHFR0_MAC_HASH_FLT_LOW_MASK (0xFFFFFFFFU) 1116 #define NETC_F3_PSIMMHFR0_MAC_HASH_FLT_LOW_SHIFT (0U) 1117 #define NETC_F3_PSIMMHFR0_MAC_HASH_FLT_LOW_WIDTH (32U) 1118 #define NETC_F3_PSIMMHFR0_MAC_HASH_FLT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIMMHFR0_MAC_HASH_FLT_LOW_SHIFT)) & NETC_F3_PSIMMHFR0_MAC_HASH_FLT_LOW_MASK) 1119 /*! @} */ 1120 1121 /*! @name PSIMMHFR1 - Port station interface 0 multicast MAC hash filter register 1..Port station interface 7 multicast MAC hash filter register 1 */ 1122 /*! @{ */ 1123 1124 #define NETC_F3_PSIMMHFR1_MAC_HASH_FLT_HIGH_MASK (0xFFFFFFFFU) 1125 #define NETC_F3_PSIMMHFR1_MAC_HASH_FLT_HIGH_SHIFT (0U) 1126 #define NETC_F3_PSIMMHFR1_MAC_HASH_FLT_HIGH_WIDTH (32U) 1127 #define NETC_F3_PSIMMHFR1_MAC_HASH_FLT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIMMHFR1_MAC_HASH_FLT_HIGH_SHIFT)) & NETC_F3_PSIMMHFR1_MAC_HASH_FLT_HIGH_MASK) 1128 /*! @} */ 1129 1130 /*! @name PSIVHFR0 - Port station interface 0 VLAN hash filter register 0..Port station interface 7 VLAN hash filter register 0 */ 1131 /*! @{ */ 1132 1133 #define NETC_F3_PSIVHFR0_VLAN_HASH_FLT_LOW_MASK (0xFFFFFFFFU) 1134 #define NETC_F3_PSIVHFR0_VLAN_HASH_FLT_LOW_SHIFT (0U) 1135 #define NETC_F3_PSIVHFR0_VLAN_HASH_FLT_LOW_WIDTH (32U) 1136 #define NETC_F3_PSIVHFR0_VLAN_HASH_FLT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIVHFR0_VLAN_HASH_FLT_LOW_SHIFT)) & NETC_F3_PSIVHFR0_VLAN_HASH_FLT_LOW_MASK) 1137 /*! @} */ 1138 1139 /*! @name PSIVHFR1 - Port station interface 0 VLAN hash filter register 1..Port station interface 7 VLAN hash filter register 1 */ 1140 /*! @{ */ 1141 1142 #define NETC_F3_PSIVHFR1_VLAN_HASH_FLT_HIGH_MASK (0xFFFFFFFFU) 1143 #define NETC_F3_PSIVHFR1_VLAN_HASH_FLT_HIGH_SHIFT (0U) 1144 #define NETC_F3_PSIVHFR1_VLAN_HASH_FLT_HIGH_WIDTH (32U) 1145 #define NETC_F3_PSIVHFR1_VLAN_HASH_FLT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_PSIVHFR1_VLAN_HASH_FLT_HIGH_SHIFT)) & NETC_F3_PSIVHFR1_VLAN_HASH_FLT_HIGH_MASK) 1146 /*! @} */ 1147 1148 /*! 1149 * @} 1150 */ /* end of group NETC_F3_Register_Masks */ 1151 1152 /*! 1153 * @} 1154 */ /* end of group NETC_F3_Peripheral_Access_Layer */ 1155 1156 #endif /* #if !defined(S32Z2_NETC_F3_H_) */ 1157
