1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_NETC_F2.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_NETC_F2 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_NETC_F2_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_NETC_F2_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- NETC_F2 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup NETC_F2_Peripheral_Access_Layer NETC_F2 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** NETC_F2 - Size of Registers Arrays */ 72 #define NETC_F2_NUM_CBDR_COUNT 2u 73 #define NETC_F2_NUM_CBDR_INT_COUNT 2u 74 #define NETC_F2_MAP_PCP_MAP_IPV_COUNT 4u 75 #define NETC_F2_MAP_PCP_COUNT 2u 76 #define NETC_F2_NUM_PCP2PCPMPR_COUNT 2u 77 78 /** NETC_F2 - Register Layout Typedef */ 79 typedef struct { 80 __I uint32_t SCAPR0; /**< Switch capability register 0, offset: 0x0 */ 81 __I uint32_t SCAPR1; /**< Switch capability register 1, offset: 0x4 */ 82 __I uint32_t BPCAPR; /**< Buffer pool capability register, offset: 0x8 */ 83 uint8_t RESERVED_0[12]; 84 __I uint32_t FCAPR; /**< Forwarding capability register, offset: 0x18 */ 85 uint8_t RESERVED_1[36]; 86 __I uint32_t SMBCAPR; /**< Shared memory buffer capability register, offset: 0x40 */ 87 __I uint32_t SMBOR0; /**< Shared memory buffer operational register 0, offset: 0x44 */ 88 __I uint32_t SMBOR1; /**< Shared memory buffer operational register 1, offset: 0x48 */ 89 uint8_t RESERVED_2[52]; 90 __IO uint32_t CCAR; /**< Command cache attribute register, offset: 0x80 */ 91 uint8_t RESERVED_3[892]; 92 __I uint32_t MPCR; /**< Management port configuration register, offset: 0x400 */ 93 uint8_t RESERVED_4[28]; 94 __IO uint32_t IMDCR0; /**< Ingress mirror destination configuration register 0, offset: 0x420 */ 95 __IO uint32_t IMDCR1; /**< Ingress mirror destination configuration register 1, offset: 0x424 */ 96 uint8_t RESERVED_5[24]; 97 __IO uint32_t CTFCR; /**< Cut-through forwarding count register, offset: 0x440 */ 98 uint8_t RESERVED_6[956]; 99 struct { /* offset: 0x800, array step: 0x30 */ 100 __IO uint32_t CBDRMR; /**< Command BDR 0 mode register..Command BDR 1 mode register, array offset: 0x800, array step: 0x30 */ 101 __I uint32_t CBDRSR; /**< Command BDR 0 status register..Command BDR 1 status register, array offset: 0x804, array step: 0x30 */ 102 uint8_t RESERVED_0[8]; 103 __IO uint32_t CBDRBAR0; /**< Command BDR base address register 0, array offset: 0x810, array step: 0x30 */ 104 __IO uint32_t CBDRBAR1; /**< Command BDR 0 base address register 1..Command BDR 1 base address register 1, array offset: 0x814, array step: 0x30 */ 105 __IO uint32_t CBDRPIR; /**< Command BDR 0 producer index register..Command BDR 1 producer index register, array offset: 0x818, array step: 0x30 */ 106 __IO uint32_t CBDRCIR; /**< Command BDR 0 consumer index register..Command BDR 1 consumer index register, array offset: 0x81C, array step: 0x30 */ 107 __IO uint32_t CBDRLENR; /**< Command BDR 0 length register..Command BDR 1 length register, array offset: 0x820, array step: 0x30 */ 108 uint8_t RESERVED_1[12]; 109 } NUM_CBDR[NETC_F2_NUM_CBDR_COUNT]; 110 uint8_t RESERVED_7[64]; 111 struct { /* offset: 0x8A0, array step: 0x10 */ 112 __IO uint32_t CBDRIER; /**< Command BDR 0 interrupt enable register..Command BDR 1 interrupt enable register, array offset: 0x8A0, array step: 0x10 */ 113 __IO uint32_t CBDRIDR; /**< Command BDR 0 interrupt detect register..Command BDR 1 interrupt detect register, array offset: 0x8A4, array step: 0x10 */ 114 __IO uint32_t CBDRMSIVR; /**< Command BDR 0 MSI-X vector register..Command BDR 1 MSI-X vector register, array offset: 0x8A8, array step: 0x10 */ 115 uint8_t RESERVED_0[4]; 116 } NUM_CBDR_INT[NETC_F2_NUM_CBDR_INT_COUNT]; 117 uint8_t RESERVED_8[64]; 118 struct { /* offset: 0x900, array step: 0x20 */ 119 __IO uint32_t QOSVLANMPR[NETC_F2_MAP_PCP_MAP_IPV_COUNT]; /**< QoS to VLAN mapping profile 0 register 0..QoS to VLAN mapping profile 1 register 3, array offset: 0x900, array step: index*0x20, index2*0x4 */ 120 uint8_t RESERVED_0[16]; 121 } MAP_PCP[NETC_F2_MAP_PCP_COUNT]; 122 uint8_t RESERVED_9[448]; 123 __IO uint32_t PCP2PCPMPR[NETC_F2_NUM_PCP2PCPMPR_COUNT]; /**< PCP to PCP mapping profile 0 register..PCP to PCP mapping profile 1 register, array offset: 0xB00, array step: 0x4 */ 124 uint8_t RESERVED_10[5368]; 125 __I uint32_t BRCAPR; /**< Bridge capability register, offset: 0x2000 */ 126 uint8_t RESERVED_11[4]; 127 __I uint32_t VFHTCAPR; /**< VLAN filter hash table capability register, offset: 0x2008 */ 128 __I uint32_t VFHTOR; /**< VLAN filter hash table operational register, offset: 0x200C */ 129 __IO uint32_t VFHTDECR0; /**< VLAN Filter (hash) table default entry configuration registers 0, offset: 0x2010 */ 130 __IO uint32_t VFHTDECR1; /**< VLAN filter hash table default entry configuration registers 1, offset: 0x2014 */ 131 __IO uint32_t VFHTDECR2; /**< VLAN filter hash table default entry configuration registers 2, offset: 0x2018 */ 132 uint8_t RESERVED_12[4]; 133 __I uint32_t FDBHTCAPR; /**< FDB hash table capability register, offset: 0x2020 */ 134 __IO uint32_t FDBHTMCR; /**< FDB hash table memory configuration register, offset: 0x2024 */ 135 __I uint32_t FDBHTOR0; /**< FDB hash table operational register 0, offset: 0x2028 */ 136 __I uint32_t FDBHTOR1; /**< FDB hash table operational register 1, offset: 0x202C */ 137 uint8_t RESERVED_13[16]; 138 __I uint32_t IPMFHTCAPR; /**< IP multicast filter hash table capability register, offset: 0x2040 */ 139 __I uint32_t IPV4MFHTOR; /**< IPv4 multicast filter hash table operation register, offset: 0x2044 */ 140 } NETC_F2_Type, *NETC_F2_MemMapPtr; 141 142 /** Number of instances of the NETC_F2 module. */ 143 #define NETC_F2_INSTANCE_COUNT (1u) 144 145 /* NETC_F2 - Peripheral instance base addresses */ 146 /** Peripheral NETC__SW0_BASE base address */ 147 #define IP_NETC__SW0_BASE_BASE (0x74A00000u) 148 /** Peripheral NETC__SW0_BASE base pointer */ 149 #define IP_NETC__SW0_BASE ((NETC_F2_Type *)IP_NETC__SW0_BASE_BASE) 150 /** Array initializer of NETC_F2 peripheral base addresses */ 151 #define IP_NETC_F2_BASE_ADDRS { IP_NETC__SW0_BASE_BASE } 152 /** Array initializer of NETC_F2 peripheral base pointers */ 153 #define IP_NETC_F2_BASE_PTRS { IP_NETC__SW0_BASE } 154 155 /* ---------------------------------------------------------------------------- 156 -- NETC_F2 Register Masks 157 ---------------------------------------------------------------------------- */ 158 159 /*! 160 * @addtogroup NETC_F2_Register_Masks NETC_F2 Register Masks 161 * @{ 162 */ 163 164 /*! @name SCAPR0 - Switch capability register 0 */ 165 /*! @{ */ 166 167 #define NETC_F2_SCAPR0_NUM_PORT_MASK (0x1FU) 168 #define NETC_F2_SCAPR0_NUM_PORT_SHIFT (0U) 169 #define NETC_F2_SCAPR0_NUM_PORT_WIDTH (5U) 170 #define NETC_F2_SCAPR0_NUM_PORT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SCAPR0_NUM_PORT_SHIFT)) & NETC_F2_SCAPR0_NUM_PORT_MASK) 171 172 #define NETC_F2_SCAPR0_NUM_IPV_MASK (0x100U) 173 #define NETC_F2_SCAPR0_NUM_IPV_SHIFT (8U) 174 #define NETC_F2_SCAPR0_NUM_IPV_WIDTH (1U) 175 #define NETC_F2_SCAPR0_NUM_IPV(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SCAPR0_NUM_IPV_SHIFT)) & NETC_F2_SCAPR0_NUM_IPV_MASK) 176 177 #define NETC_F2_SCAPR0_NUM_MSIX_MASK (0xF0000U) 178 #define NETC_F2_SCAPR0_NUM_MSIX_SHIFT (16U) 179 #define NETC_F2_SCAPR0_NUM_MSIX_WIDTH (4U) 180 #define NETC_F2_SCAPR0_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SCAPR0_NUM_MSIX_SHIFT)) & NETC_F2_SCAPR0_NUM_MSIX_MASK) 181 182 #define NETC_F2_SCAPR0_NUM_PCPMP_MASK (0xF00000U) 183 #define NETC_F2_SCAPR0_NUM_PCPMP_SHIFT (20U) 184 #define NETC_F2_SCAPR0_NUM_PCPMP_WIDTH (4U) 185 #define NETC_F2_SCAPR0_NUM_PCPMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SCAPR0_NUM_PCPMP_SHIFT)) & NETC_F2_SCAPR0_NUM_PCPMP_MASK) 186 187 #define NETC_F2_SCAPR0_NUM_QVMP_MASK (0xF000000U) 188 #define NETC_F2_SCAPR0_NUM_QVMP_SHIFT (24U) 189 #define NETC_F2_SCAPR0_NUM_QVMP_WIDTH (4U) 190 #define NETC_F2_SCAPR0_NUM_QVMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SCAPR0_NUM_QVMP_SHIFT)) & NETC_F2_SCAPR0_NUM_QVMP_MASK) 191 /*! @} */ 192 193 /*! @name SCAPR1 - Switch capability register 1 */ 194 /*! @{ */ 195 196 #define NETC_F2_SCAPR1_FS_MASK (0x1U) 197 #define NETC_F2_SCAPR1_FS_SHIFT (0U) 198 #define NETC_F2_SCAPR1_FS_WIDTH (1U) 199 #define NETC_F2_SCAPR1_FS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SCAPR1_FS_SHIFT)) & NETC_F2_SCAPR1_FS_MASK) 200 201 #define NETC_F2_SCAPR1_CTF_MASK (0x4U) 202 #define NETC_F2_SCAPR1_CTF_SHIFT (2U) 203 #define NETC_F2_SCAPR1_CTF_WIDTH (1U) 204 #define NETC_F2_SCAPR1_CTF(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SCAPR1_CTF_SHIFT)) & NETC_F2_SCAPR1_CTF_MASK) 205 206 #define NETC_F2_SCAPR1_TIMCAP_MASK (0x8U) 207 #define NETC_F2_SCAPR1_TIMCAP_SHIFT (3U) 208 #define NETC_F2_SCAPR1_TIMCAP_WIDTH (1U) 209 #define NETC_F2_SCAPR1_TIMCAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SCAPR1_TIMCAP_SHIFT)) & NETC_F2_SCAPR1_TIMCAP_MASK) 210 211 #define NETC_F2_SCAPR1_IMIR_MASK (0x10U) 212 #define NETC_F2_SCAPR1_IMIR_SHIFT (4U) 213 #define NETC_F2_SCAPR1_IMIR_WIDTH (1U) 214 #define NETC_F2_SCAPR1_IMIR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SCAPR1_IMIR_SHIFT)) & NETC_F2_SCAPR1_IMIR_MASK) 215 216 #define NETC_F2_SCAPR1_SQ_TAGS_MASK (0x1F0000U) 217 #define NETC_F2_SCAPR1_SQ_TAGS_SHIFT (16U) 218 #define NETC_F2_SCAPR1_SQ_TAGS_WIDTH (5U) 219 #define NETC_F2_SCAPR1_SQ_TAGS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SCAPR1_SQ_TAGS_SHIFT)) & NETC_F2_SCAPR1_SQ_TAGS_MASK) 220 /*! @} */ 221 222 /*! @name BPCAPR - Buffer pool capability register */ 223 /*! @{ */ 224 225 #define NETC_F2_BPCAPR_NUM_BP_MASK (0xFFU) 226 #define NETC_F2_BPCAPR_NUM_BP_SHIFT (0U) 227 #define NETC_F2_BPCAPR_NUM_BP_WIDTH (8U) 228 #define NETC_F2_BPCAPR_NUM_BP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_BPCAPR_NUM_BP_SHIFT)) & NETC_F2_BPCAPR_NUM_BP_MASK) 229 230 #define NETC_F2_BPCAPR_NUM_SPB_MASK (0x1F0000U) 231 #define NETC_F2_BPCAPR_NUM_SPB_SHIFT (16U) 232 #define NETC_F2_BPCAPR_NUM_SPB_WIDTH (5U) 233 #define NETC_F2_BPCAPR_NUM_SPB(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_BPCAPR_NUM_SPB_SHIFT)) & NETC_F2_BPCAPR_NUM_SPB_MASK) 234 /*! @} */ 235 236 /*! @name FCAPR - Forwarding capability register */ 237 /*! @{ */ 238 239 #define NETC_F2_FCAPR_BR_MASK (0x1U) 240 #define NETC_F2_FCAPR_BR_SHIFT (0U) 241 #define NETC_F2_FCAPR_BR_WIDTH (1U) 242 #define NETC_F2_FCAPR_BR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_FCAPR_BR_SHIFT)) & NETC_F2_FCAPR_BR_MASK) 243 244 #define NETC_F2_FCAPR_SF_MASK (0x2U) 245 #define NETC_F2_FCAPR_SF_SHIFT (1U) 246 #define NETC_F2_FCAPR_SF_WIDTH (1U) 247 #define NETC_F2_FCAPR_SF(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_FCAPR_SF_SHIFT)) & NETC_F2_FCAPR_SF_MASK) 248 /*! @} */ 249 250 /*! @name SMBCAPR - Shared memory buffer capability register */ 251 /*! @{ */ 252 253 #define NETC_F2_SMBCAPR_NUM_WORDS_MASK (0xFFFFFFU) 254 #define NETC_F2_SMBCAPR_NUM_WORDS_SHIFT (0U) 255 #define NETC_F2_SMBCAPR_NUM_WORDS_WIDTH (24U) 256 #define NETC_F2_SMBCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SMBCAPR_NUM_WORDS_SHIFT)) & NETC_F2_SMBCAPR_NUM_WORDS_MASK) 257 258 #define NETC_F2_SMBCAPR_WORD_SIZE_MASK (0x30000000U) 259 #define NETC_F2_SMBCAPR_WORD_SIZE_SHIFT (28U) 260 #define NETC_F2_SMBCAPR_WORD_SIZE_WIDTH (2U) 261 #define NETC_F2_SMBCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SMBCAPR_WORD_SIZE_SHIFT)) & NETC_F2_SMBCAPR_WORD_SIZE_MASK) 262 263 #define NETC_F2_SMBCAPR_MLOC_MASK (0xC0000000U) 264 #define NETC_F2_SMBCAPR_MLOC_SHIFT (30U) 265 #define NETC_F2_SMBCAPR_MLOC_WIDTH (2U) 266 #define NETC_F2_SMBCAPR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SMBCAPR_MLOC_SHIFT)) & NETC_F2_SMBCAPR_MLOC_MASK) 267 /*! @} */ 268 269 /*! @name SMBOR0 - Shared memory buffer operational register 0 */ 270 /*! @{ */ 271 272 #define NETC_F2_SMBOR0_COUNT_MASK (0xFFFFFFU) 273 #define NETC_F2_SMBOR0_COUNT_SHIFT (0U) 274 #define NETC_F2_SMBOR0_COUNT_WIDTH (24U) 275 #define NETC_F2_SMBOR0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SMBOR0_COUNT_SHIFT)) & NETC_F2_SMBOR0_COUNT_MASK) 276 /*! @} */ 277 278 /*! @name SMBOR1 - Shared memory buffer operational register 1 */ 279 /*! @{ */ 280 281 #define NETC_F2_SMBOR1_WATERMARK_MASK (0xFFFFFFU) 282 #define NETC_F2_SMBOR1_WATERMARK_SHIFT (0U) 283 #define NETC_F2_SMBOR1_WATERMARK_WIDTH (24U) 284 #define NETC_F2_SMBOR1_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_SMBOR1_WATERMARK_SHIFT)) & NETC_F2_SMBOR1_WATERMARK_MASK) 285 /*! @} */ 286 287 /*! @name CCAR - Command cache attribute register */ 288 /*! @{ */ 289 290 #define NETC_F2_CCAR_CBD_WRCACHE_MASK (0xFU) 291 #define NETC_F2_CCAR_CBD_WRCACHE_SHIFT (0U) 292 #define NETC_F2_CCAR_CBD_WRCACHE_WIDTH (4U) 293 #define NETC_F2_CCAR_CBD_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CCAR_CBD_WRCACHE_SHIFT)) & NETC_F2_CCAR_CBD_WRCACHE_MASK) 294 295 #define NETC_F2_CCAR_CBD_WRDOMAIN_MASK (0x30U) 296 #define NETC_F2_CCAR_CBD_WRDOMAIN_SHIFT (4U) 297 #define NETC_F2_CCAR_CBD_WRDOMAIN_WIDTH (2U) 298 #define NETC_F2_CCAR_CBD_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CCAR_CBD_WRDOMAIN_SHIFT)) & NETC_F2_CCAR_CBD_WRDOMAIN_MASK) 299 300 #define NETC_F2_CCAR_CBD_WRSNP_MASK (0x40U) 301 #define NETC_F2_CCAR_CBD_WRSNP_SHIFT (6U) 302 #define NETC_F2_CCAR_CBD_WRSNP_WIDTH (1U) 303 #define NETC_F2_CCAR_CBD_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CCAR_CBD_WRSNP_SHIFT)) & NETC_F2_CCAR_CBD_WRSNP_MASK) 304 305 #define NETC_F2_CCAR_CWRCACHE_MASK (0xF00U) 306 #define NETC_F2_CCAR_CWRCACHE_SHIFT (8U) 307 #define NETC_F2_CCAR_CWRCACHE_WIDTH (4U) 308 #define NETC_F2_CCAR_CWRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CCAR_CWRCACHE_SHIFT)) & NETC_F2_CCAR_CWRCACHE_MASK) 309 310 #define NETC_F2_CCAR_CWRDOMAIN_MASK (0x3000U) 311 #define NETC_F2_CCAR_CWRDOMAIN_SHIFT (12U) 312 #define NETC_F2_CCAR_CWRDOMAIN_WIDTH (2U) 313 #define NETC_F2_CCAR_CWRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CCAR_CWRDOMAIN_SHIFT)) & NETC_F2_CCAR_CWRDOMAIN_MASK) 314 315 #define NETC_F2_CCAR_CWRSNP_MASK (0x4000U) 316 #define NETC_F2_CCAR_CWRSNP_SHIFT (14U) 317 #define NETC_F2_CCAR_CWRSNP_WIDTH (1U) 318 #define NETC_F2_CCAR_CWRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CCAR_CWRSNP_SHIFT)) & NETC_F2_CCAR_CWRSNP_MASK) 319 320 #define NETC_F2_CCAR_CBD_RDCACHE_MASK (0xF0000U) 321 #define NETC_F2_CCAR_CBD_RDCACHE_SHIFT (16U) 322 #define NETC_F2_CCAR_CBD_RDCACHE_WIDTH (4U) 323 #define NETC_F2_CCAR_CBD_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CCAR_CBD_RDCACHE_SHIFT)) & NETC_F2_CCAR_CBD_RDCACHE_MASK) 324 325 #define NETC_F2_CCAR_CBD_RDDOMAIN_MASK (0x300000U) 326 #define NETC_F2_CCAR_CBD_RDDOMAIN_SHIFT (20U) 327 #define NETC_F2_CCAR_CBD_RDDOMAIN_WIDTH (2U) 328 #define NETC_F2_CCAR_CBD_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CCAR_CBD_RDDOMAIN_SHIFT)) & NETC_F2_CCAR_CBD_RDDOMAIN_MASK) 329 330 #define NETC_F2_CCAR_CBD_RDSNP_MASK (0x400000U) 331 #define NETC_F2_CCAR_CBD_RDSNP_SHIFT (22U) 332 #define NETC_F2_CCAR_CBD_RDSNP_WIDTH (1U) 333 #define NETC_F2_CCAR_CBD_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CCAR_CBD_RDSNP_SHIFT)) & NETC_F2_CCAR_CBD_RDSNP_MASK) 334 335 #define NETC_F2_CCAR_CRDCACHE_MASK (0xF000000U) 336 #define NETC_F2_CCAR_CRDCACHE_SHIFT (24U) 337 #define NETC_F2_CCAR_CRDCACHE_WIDTH (4U) 338 #define NETC_F2_CCAR_CRDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CCAR_CRDCACHE_SHIFT)) & NETC_F2_CCAR_CRDCACHE_MASK) 339 340 #define NETC_F2_CCAR_CRDDOMAIN_MASK (0x30000000U) 341 #define NETC_F2_CCAR_CRDDOMAIN_SHIFT (28U) 342 #define NETC_F2_CCAR_CRDDOMAIN_WIDTH (2U) 343 #define NETC_F2_CCAR_CRDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CCAR_CRDDOMAIN_SHIFT)) & NETC_F2_CCAR_CRDDOMAIN_MASK) 344 345 #define NETC_F2_CCAR_CRDSNP_MASK (0x40000000U) 346 #define NETC_F2_CCAR_CRDSNP_SHIFT (30U) 347 #define NETC_F2_CCAR_CRDSNP_WIDTH (1U) 348 #define NETC_F2_CCAR_CRDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CCAR_CRDSNP_SHIFT)) & NETC_F2_CCAR_CRDSNP_MASK) 349 /*! @} */ 350 351 /*! @name MPCR - Management port configuration register */ 352 /*! @{ */ 353 354 #define NETC_F2_MPCR_PORT_MASK (0x1FU) 355 #define NETC_F2_MPCR_PORT_SHIFT (0U) 356 #define NETC_F2_MPCR_PORT_WIDTH (5U) 357 #define NETC_F2_MPCR_PORT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_MPCR_PORT_SHIFT)) & NETC_F2_MPCR_PORT_MASK) 358 /*! @} */ 359 360 /*! @name IMDCR0 - Ingress mirror destination configuration register 0 */ 361 /*! @{ */ 362 363 #define NETC_F2_IMDCR0_MIREN_MASK (0x1U) 364 #define NETC_F2_IMDCR0_MIREN_SHIFT (0U) 365 #define NETC_F2_IMDCR0_MIREN_WIDTH (1U) 366 #define NETC_F2_IMDCR0_MIREN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_IMDCR0_MIREN_SHIFT)) & NETC_F2_IMDCR0_MIREN_MASK) 367 368 #define NETC_F2_IMDCR0_MIRDEST_MASK (0x2U) 369 #define NETC_F2_IMDCR0_MIRDEST_SHIFT (1U) 370 #define NETC_F2_IMDCR0_MIRDEST_WIDTH (1U) 371 #define NETC_F2_IMDCR0_MIRDEST(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_IMDCR0_MIRDEST_SHIFT)) & NETC_F2_IMDCR0_MIRDEST_MASK) 372 373 #define NETC_F2_IMDCR0_IPV_MASK (0x1CU) 374 #define NETC_F2_IMDCR0_IPV_SHIFT (2U) 375 #define NETC_F2_IMDCR0_IPV_WIDTH (3U) 376 #define NETC_F2_IMDCR0_IPV(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_IMDCR0_IPV_SHIFT)) & NETC_F2_IMDCR0_IPV_MASK) 377 378 #define NETC_F2_IMDCR0_DR_MASK (0xC0U) 379 #define NETC_F2_IMDCR0_DR_SHIFT (6U) 380 #define NETC_F2_IMDCR0_DR_WIDTH (2U) 381 #define NETC_F2_IMDCR0_DR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_IMDCR0_DR_SHIFT)) & NETC_F2_IMDCR0_DR_MASK) 382 383 #define NETC_F2_IMDCR0_PORT_MASK (0x1F00U) 384 #define NETC_F2_IMDCR0_PORT_SHIFT (8U) 385 #define NETC_F2_IMDCR0_PORT_WIDTH (5U) 386 #define NETC_F2_IMDCR0_PORT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_IMDCR0_PORT_SHIFT)) & NETC_F2_IMDCR0_PORT_MASK) 387 /*! @} */ 388 389 /*! @name IMDCR1 - Ingress mirror destination configuration register 1 */ 390 /*! @{ */ 391 392 #define NETC_F2_IMDCR1_EFMEID_MASK (0xFFFFU) 393 #define NETC_F2_IMDCR1_EFMEID_SHIFT (0U) 394 #define NETC_F2_IMDCR1_EFMEID_WIDTH (16U) 395 #define NETC_F2_IMDCR1_EFMEID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_IMDCR1_EFMEID_SHIFT)) & NETC_F2_IMDCR1_EFMEID_MASK) 396 397 #define NETC_F2_IMDCR1_EFM_LEN_CHANGE_MASK (0x7F0000U) 398 #define NETC_F2_IMDCR1_EFM_LEN_CHANGE_SHIFT (16U) 399 #define NETC_F2_IMDCR1_EFM_LEN_CHANGE_WIDTH (7U) 400 #define NETC_F2_IMDCR1_EFM_LEN_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_IMDCR1_EFM_LEN_CHANGE_SHIFT)) & NETC_F2_IMDCR1_EFM_LEN_CHANGE_MASK) 401 /*! @} */ 402 403 /*! @name CTFCR - Cut-through forwarding count register */ 404 /*! @{ */ 405 406 #define NETC_F2_CTFCR_COUNT_MASK (0xFFFFFFFFU) 407 #define NETC_F2_CTFCR_COUNT_SHIFT (0U) 408 #define NETC_F2_CTFCR_COUNT_WIDTH (32U) 409 #define NETC_F2_CTFCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CTFCR_COUNT_SHIFT)) & NETC_F2_CTFCR_COUNT_MASK) 410 /*! @} */ 411 412 /*! @name CBDRMR - Command BDR 0 mode register..Command BDR 1 mode register */ 413 /*! @{ */ 414 415 #define NETC_F2_CBDRMR_EN_MASK (0x80000000U) 416 #define NETC_F2_CBDRMR_EN_SHIFT (31U) 417 #define NETC_F2_CBDRMR_EN_WIDTH (1U) 418 #define NETC_F2_CBDRMR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CBDRMR_EN_SHIFT)) & NETC_F2_CBDRMR_EN_MASK) 419 /*! @} */ 420 421 /*! @name CBDRSR - Command BDR 0 status register..Command BDR 1 status register */ 422 /*! @{ */ 423 424 #define NETC_F2_CBDRSR_BUSY_MASK (0x1U) 425 #define NETC_F2_CBDRSR_BUSY_SHIFT (0U) 426 #define NETC_F2_CBDRSR_BUSY_WIDTH (1U) 427 #define NETC_F2_CBDRSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CBDRSR_BUSY_SHIFT)) & NETC_F2_CBDRSR_BUSY_MASK) 428 /*! @} */ 429 430 /*! @name CBDRBAR0 - Command BDR base address register 0 */ 431 /*! @{ */ 432 433 #define NETC_F2_CBDRBAR0_ADDRL_MASK (0xFFFFFF80U) 434 #define NETC_F2_CBDRBAR0_ADDRL_SHIFT (7U) 435 #define NETC_F2_CBDRBAR0_ADDRL_WIDTH (25U) 436 #define NETC_F2_CBDRBAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CBDRBAR0_ADDRL_SHIFT)) & NETC_F2_CBDRBAR0_ADDRL_MASK) 437 /*! @} */ 438 439 /*! @name CBDRBAR1 - Command BDR 0 base address register 1..Command BDR 1 base address register 1 */ 440 /*! @{ */ 441 442 #define NETC_F2_CBDRBAR1_ADDRH_MASK (0xFFFFFFFFU) 443 #define NETC_F2_CBDRBAR1_ADDRH_SHIFT (0U) 444 #define NETC_F2_CBDRBAR1_ADDRH_WIDTH (32U) 445 #define NETC_F2_CBDRBAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CBDRBAR1_ADDRH_SHIFT)) & NETC_F2_CBDRBAR1_ADDRH_MASK) 446 /*! @} */ 447 448 /*! @name CBDRPIR - Command BDR 0 producer index register..Command BDR 1 producer index register */ 449 /*! @{ */ 450 451 #define NETC_F2_CBDRPIR_BDR_INDEX_MASK (0x3FFU) 452 #define NETC_F2_CBDRPIR_BDR_INDEX_SHIFT (0U) 453 #define NETC_F2_CBDRPIR_BDR_INDEX_WIDTH (10U) 454 #define NETC_F2_CBDRPIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CBDRPIR_BDR_INDEX_SHIFT)) & NETC_F2_CBDRPIR_BDR_INDEX_MASK) 455 /*! @} */ 456 457 /*! @name CBDRCIR - Command BDR 0 consumer index register..Command BDR 1 consumer index register */ 458 /*! @{ */ 459 460 #define NETC_F2_CBDRCIR_BDR_INDEX_MASK (0x3FFU) 461 #define NETC_F2_CBDRCIR_BDR_INDEX_SHIFT (0U) 462 #define NETC_F2_CBDRCIR_BDR_INDEX_WIDTH (10U) 463 #define NETC_F2_CBDRCIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CBDRCIR_BDR_INDEX_SHIFT)) & NETC_F2_CBDRCIR_BDR_INDEX_MASK) 464 /*! @} */ 465 466 /*! @name CBDRLENR - Command BDR 0 length register..Command BDR 1 length register */ 467 /*! @{ */ 468 469 #define NETC_F2_CBDRLENR_LENGTH_MASK (0x7F8U) 470 #define NETC_F2_CBDRLENR_LENGTH_SHIFT (3U) 471 #define NETC_F2_CBDRLENR_LENGTH_WIDTH (8U) 472 #define NETC_F2_CBDRLENR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CBDRLENR_LENGTH_SHIFT)) & NETC_F2_CBDRLENR_LENGTH_MASK) 473 /*! @} */ 474 475 /*! @name CBDRIER - Command BDR 0 interrupt enable register..Command BDR 1 interrupt enable register */ 476 /*! @{ */ 477 478 #define NETC_F2_CBDRIER_CBDCIE_MASK (0x1U) 479 #define NETC_F2_CBDRIER_CBDCIE_SHIFT (0U) 480 #define NETC_F2_CBDRIER_CBDCIE_WIDTH (1U) 481 #define NETC_F2_CBDRIER_CBDCIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CBDRIER_CBDCIE_SHIFT)) & NETC_F2_CBDRIER_CBDCIE_MASK) 482 /*! @} */ 483 484 /*! @name CBDRIDR - Command BDR 0 interrupt detect register..Command BDR 1 interrupt detect register */ 485 /*! @{ */ 486 487 #define NETC_F2_CBDRIDR_CBDC_MASK (0x1U) 488 #define NETC_F2_CBDRIDR_CBDC_SHIFT (0U) 489 #define NETC_F2_CBDRIDR_CBDC_WIDTH (1U) 490 #define NETC_F2_CBDRIDR_CBDC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CBDRIDR_CBDC_SHIFT)) & NETC_F2_CBDRIDR_CBDC_MASK) 491 /*! @} */ 492 493 /*! @name CBDRMSIVR - Command BDR 0 MSI-X vector register..Command BDR 1 MSI-X vector register */ 494 /*! @{ */ 495 496 #define NETC_F2_CBDRMSIVR_VECTOR_MASK (0xFU) 497 #define NETC_F2_CBDRMSIVR_VECTOR_SHIFT (0U) 498 #define NETC_F2_CBDRMSIVR_VECTOR_WIDTH (4U) 499 #define NETC_F2_CBDRMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_CBDRMSIVR_VECTOR_SHIFT)) & NETC_F2_CBDRMSIVR_VECTOR_MASK) 500 /*! @} */ 501 502 /*! @name QOSVLANMPR - QoS to VLAN mapping profile 0 register 0..QoS to VLAN mapping profile 1 register 3 */ 503 /*! @{ */ 504 505 #define NETC_F2_QOSVLANMPR_IPV0_DR0_MASK (0xFU) 506 #define NETC_F2_QOSVLANMPR_IPV0_DR0_SHIFT (0U) 507 #define NETC_F2_QOSVLANMPR_IPV0_DR0_WIDTH (4U) 508 #define NETC_F2_QOSVLANMPR_IPV0_DR0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV0_DR0_SHIFT)) & NETC_F2_QOSVLANMPR_IPV0_DR0_MASK) 509 510 #define NETC_F2_QOSVLANMPR_IPV2_DR0_MASK (0xFU) 511 #define NETC_F2_QOSVLANMPR_IPV2_DR0_SHIFT (0U) 512 #define NETC_F2_QOSVLANMPR_IPV2_DR0_WIDTH (4U) 513 #define NETC_F2_QOSVLANMPR_IPV2_DR0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV2_DR0_SHIFT)) & NETC_F2_QOSVLANMPR_IPV2_DR0_MASK) 514 515 #define NETC_F2_QOSVLANMPR_IPV4_DR0_MASK (0xFU) 516 #define NETC_F2_QOSVLANMPR_IPV4_DR0_SHIFT (0U) 517 #define NETC_F2_QOSVLANMPR_IPV4_DR0_WIDTH (4U) 518 #define NETC_F2_QOSVLANMPR_IPV4_DR0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV4_DR0_SHIFT)) & NETC_F2_QOSVLANMPR_IPV4_DR0_MASK) 519 520 #define NETC_F2_QOSVLANMPR_IPV6_DR0_MASK (0xFU) 521 #define NETC_F2_QOSVLANMPR_IPV6_DR0_SHIFT (0U) 522 #define NETC_F2_QOSVLANMPR_IPV6_DR0_WIDTH (4U) 523 #define NETC_F2_QOSVLANMPR_IPV6_DR0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV6_DR0_SHIFT)) & NETC_F2_QOSVLANMPR_IPV6_DR0_MASK) 524 525 #define NETC_F2_QOSVLANMPR_IPV0_DR1_MASK (0xF0U) 526 #define NETC_F2_QOSVLANMPR_IPV0_DR1_SHIFT (4U) 527 #define NETC_F2_QOSVLANMPR_IPV0_DR1_WIDTH (4U) 528 #define NETC_F2_QOSVLANMPR_IPV0_DR1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV0_DR1_SHIFT)) & NETC_F2_QOSVLANMPR_IPV0_DR1_MASK) 529 530 #define NETC_F2_QOSVLANMPR_IPV2_DR1_MASK (0xF0U) 531 #define NETC_F2_QOSVLANMPR_IPV2_DR1_SHIFT (4U) 532 #define NETC_F2_QOSVLANMPR_IPV2_DR1_WIDTH (4U) 533 #define NETC_F2_QOSVLANMPR_IPV2_DR1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV2_DR1_SHIFT)) & NETC_F2_QOSVLANMPR_IPV2_DR1_MASK) 534 535 #define NETC_F2_QOSVLANMPR_IPV4_DR1_MASK (0xF0U) 536 #define NETC_F2_QOSVLANMPR_IPV4_DR1_SHIFT (4U) 537 #define NETC_F2_QOSVLANMPR_IPV4_DR1_WIDTH (4U) 538 #define NETC_F2_QOSVLANMPR_IPV4_DR1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV4_DR1_SHIFT)) & NETC_F2_QOSVLANMPR_IPV4_DR1_MASK) 539 540 #define NETC_F2_QOSVLANMPR_IPV6_DR1_MASK (0xF0U) 541 #define NETC_F2_QOSVLANMPR_IPV6_DR1_SHIFT (4U) 542 #define NETC_F2_QOSVLANMPR_IPV6_DR1_WIDTH (4U) 543 #define NETC_F2_QOSVLANMPR_IPV6_DR1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV6_DR1_SHIFT)) & NETC_F2_QOSVLANMPR_IPV6_DR1_MASK) 544 545 #define NETC_F2_QOSVLANMPR_IPV0_DR2_MASK (0xF00U) 546 #define NETC_F2_QOSVLANMPR_IPV0_DR2_SHIFT (8U) 547 #define NETC_F2_QOSVLANMPR_IPV0_DR2_WIDTH (4U) 548 #define NETC_F2_QOSVLANMPR_IPV0_DR2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV0_DR2_SHIFT)) & NETC_F2_QOSVLANMPR_IPV0_DR2_MASK) 549 550 #define NETC_F2_QOSVLANMPR_IPV2_DR2_MASK (0xF00U) 551 #define NETC_F2_QOSVLANMPR_IPV2_DR2_SHIFT (8U) 552 #define NETC_F2_QOSVLANMPR_IPV2_DR2_WIDTH (4U) 553 #define NETC_F2_QOSVLANMPR_IPV2_DR2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV2_DR2_SHIFT)) & NETC_F2_QOSVLANMPR_IPV2_DR2_MASK) 554 555 #define NETC_F2_QOSVLANMPR_IPV4_DR2_MASK (0xF00U) 556 #define NETC_F2_QOSVLANMPR_IPV4_DR2_SHIFT (8U) 557 #define NETC_F2_QOSVLANMPR_IPV4_DR2_WIDTH (4U) 558 #define NETC_F2_QOSVLANMPR_IPV4_DR2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV4_DR2_SHIFT)) & NETC_F2_QOSVLANMPR_IPV4_DR2_MASK) 559 560 #define NETC_F2_QOSVLANMPR_IPV6_DR2_MASK (0xF00U) 561 #define NETC_F2_QOSVLANMPR_IPV6_DR2_SHIFT (8U) 562 #define NETC_F2_QOSVLANMPR_IPV6_DR2_WIDTH (4U) 563 #define NETC_F2_QOSVLANMPR_IPV6_DR2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV6_DR2_SHIFT)) & NETC_F2_QOSVLANMPR_IPV6_DR2_MASK) 564 565 #define NETC_F2_QOSVLANMPR_IPV0_DR3_MASK (0xF000U) 566 #define NETC_F2_QOSVLANMPR_IPV0_DR3_SHIFT (12U) 567 #define NETC_F2_QOSVLANMPR_IPV0_DR3_WIDTH (4U) 568 #define NETC_F2_QOSVLANMPR_IPV0_DR3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV0_DR3_SHIFT)) & NETC_F2_QOSVLANMPR_IPV0_DR3_MASK) 569 570 #define NETC_F2_QOSVLANMPR_IPV2_DR3_MASK (0xF000U) 571 #define NETC_F2_QOSVLANMPR_IPV2_DR3_SHIFT (12U) 572 #define NETC_F2_QOSVLANMPR_IPV2_DR3_WIDTH (4U) 573 #define NETC_F2_QOSVLANMPR_IPV2_DR3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV2_DR3_SHIFT)) & NETC_F2_QOSVLANMPR_IPV2_DR3_MASK) 574 575 #define NETC_F2_QOSVLANMPR_IPV4_DR3_MASK (0xF000U) 576 #define NETC_F2_QOSVLANMPR_IPV4_DR3_SHIFT (12U) 577 #define NETC_F2_QOSVLANMPR_IPV4_DR3_WIDTH (4U) 578 #define NETC_F2_QOSVLANMPR_IPV4_DR3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV4_DR3_SHIFT)) & NETC_F2_QOSVLANMPR_IPV4_DR3_MASK) 579 580 #define NETC_F2_QOSVLANMPR_IPV6_DR3_MASK (0xF000U) 581 #define NETC_F2_QOSVLANMPR_IPV6_DR3_SHIFT (12U) 582 #define NETC_F2_QOSVLANMPR_IPV6_DR3_WIDTH (4U) 583 #define NETC_F2_QOSVLANMPR_IPV6_DR3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV6_DR3_SHIFT)) & NETC_F2_QOSVLANMPR_IPV6_DR3_MASK) 584 585 #define NETC_F2_QOSVLANMPR_IPV1_DR0_MASK (0xF0000U) 586 #define NETC_F2_QOSVLANMPR_IPV1_DR0_SHIFT (16U) 587 #define NETC_F2_QOSVLANMPR_IPV1_DR0_WIDTH (4U) 588 #define NETC_F2_QOSVLANMPR_IPV1_DR0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV1_DR0_SHIFT)) & NETC_F2_QOSVLANMPR_IPV1_DR0_MASK) 589 590 #define NETC_F2_QOSVLANMPR_IPV3_DR0_MASK (0xF0000U) 591 #define NETC_F2_QOSVLANMPR_IPV3_DR0_SHIFT (16U) 592 #define NETC_F2_QOSVLANMPR_IPV3_DR0_WIDTH (4U) 593 #define NETC_F2_QOSVLANMPR_IPV3_DR0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV3_DR0_SHIFT)) & NETC_F2_QOSVLANMPR_IPV3_DR0_MASK) 594 595 #define NETC_F2_QOSVLANMPR_IPV5_DR0_MASK (0xF0000U) 596 #define NETC_F2_QOSVLANMPR_IPV5_DR0_SHIFT (16U) 597 #define NETC_F2_QOSVLANMPR_IPV5_DR0_WIDTH (4U) 598 #define NETC_F2_QOSVLANMPR_IPV5_DR0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV5_DR0_SHIFT)) & NETC_F2_QOSVLANMPR_IPV5_DR0_MASK) 599 600 #define NETC_F2_QOSVLANMPR_IPV7_DR0_MASK (0xF0000U) 601 #define NETC_F2_QOSVLANMPR_IPV7_DR0_SHIFT (16U) 602 #define NETC_F2_QOSVLANMPR_IPV7_DR0_WIDTH (4U) 603 #define NETC_F2_QOSVLANMPR_IPV7_DR0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV7_DR0_SHIFT)) & NETC_F2_QOSVLANMPR_IPV7_DR0_MASK) 604 605 #define NETC_F2_QOSVLANMPR_IPV1_DR1_MASK (0xF00000U) 606 #define NETC_F2_QOSVLANMPR_IPV1_DR1_SHIFT (20U) 607 #define NETC_F2_QOSVLANMPR_IPV1_DR1_WIDTH (4U) 608 #define NETC_F2_QOSVLANMPR_IPV1_DR1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV1_DR1_SHIFT)) & NETC_F2_QOSVLANMPR_IPV1_DR1_MASK) 609 610 #define NETC_F2_QOSVLANMPR_IPV3_DR1_MASK (0xF00000U) 611 #define NETC_F2_QOSVLANMPR_IPV3_DR1_SHIFT (20U) 612 #define NETC_F2_QOSVLANMPR_IPV3_DR1_WIDTH (4U) 613 #define NETC_F2_QOSVLANMPR_IPV3_DR1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV3_DR1_SHIFT)) & NETC_F2_QOSVLANMPR_IPV3_DR1_MASK) 614 615 #define NETC_F2_QOSVLANMPR_IPV5_DR1_MASK (0xF00000U) 616 #define NETC_F2_QOSVLANMPR_IPV5_DR1_SHIFT (20U) 617 #define NETC_F2_QOSVLANMPR_IPV5_DR1_WIDTH (4U) 618 #define NETC_F2_QOSVLANMPR_IPV5_DR1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV5_DR1_SHIFT)) & NETC_F2_QOSVLANMPR_IPV5_DR1_MASK) 619 620 #define NETC_F2_QOSVLANMPR_IPV7_DR1_MASK (0xF00000U) 621 #define NETC_F2_QOSVLANMPR_IPV7_DR1_SHIFT (20U) 622 #define NETC_F2_QOSVLANMPR_IPV7_DR1_WIDTH (4U) 623 #define NETC_F2_QOSVLANMPR_IPV7_DR1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV7_DR1_SHIFT)) & NETC_F2_QOSVLANMPR_IPV7_DR1_MASK) 624 625 #define NETC_F2_QOSVLANMPR_IPV1_DR2_MASK (0xF000000U) 626 #define NETC_F2_QOSVLANMPR_IPV1_DR2_SHIFT (24U) 627 #define NETC_F2_QOSVLANMPR_IPV1_DR2_WIDTH (4U) 628 #define NETC_F2_QOSVLANMPR_IPV1_DR2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV1_DR2_SHIFT)) & NETC_F2_QOSVLANMPR_IPV1_DR2_MASK) 629 630 #define NETC_F2_QOSVLANMPR_IPV3_DR2_MASK (0xF000000U) 631 #define NETC_F2_QOSVLANMPR_IPV3_DR2_SHIFT (24U) 632 #define NETC_F2_QOSVLANMPR_IPV3_DR2_WIDTH (4U) 633 #define NETC_F2_QOSVLANMPR_IPV3_DR2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV3_DR2_SHIFT)) & NETC_F2_QOSVLANMPR_IPV3_DR2_MASK) 634 635 #define NETC_F2_QOSVLANMPR_IPV5_DR2_MASK (0xF000000U) 636 #define NETC_F2_QOSVLANMPR_IPV5_DR2_SHIFT (24U) 637 #define NETC_F2_QOSVLANMPR_IPV5_DR2_WIDTH (4U) 638 #define NETC_F2_QOSVLANMPR_IPV5_DR2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV5_DR2_SHIFT)) & NETC_F2_QOSVLANMPR_IPV5_DR2_MASK) 639 640 #define NETC_F2_QOSVLANMPR_IPV7_DR2_MASK (0xF000000U) 641 #define NETC_F2_QOSVLANMPR_IPV7_DR2_SHIFT (24U) 642 #define NETC_F2_QOSVLANMPR_IPV7_DR2_WIDTH (4U) 643 #define NETC_F2_QOSVLANMPR_IPV7_DR2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV7_DR2_SHIFT)) & NETC_F2_QOSVLANMPR_IPV7_DR2_MASK) 644 645 #define NETC_F2_QOSVLANMPR_IPV1_DR3_MASK (0xF0000000U) 646 #define NETC_F2_QOSVLANMPR_IPV1_DR3_SHIFT (28U) 647 #define NETC_F2_QOSVLANMPR_IPV1_DR3_WIDTH (4U) 648 #define NETC_F2_QOSVLANMPR_IPV1_DR3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV1_DR3_SHIFT)) & NETC_F2_QOSVLANMPR_IPV1_DR3_MASK) 649 650 #define NETC_F2_QOSVLANMPR_IPV3_DR3_MASK (0xF0000000U) 651 #define NETC_F2_QOSVLANMPR_IPV3_DR3_SHIFT (28U) 652 #define NETC_F2_QOSVLANMPR_IPV3_DR3_WIDTH (4U) 653 #define NETC_F2_QOSVLANMPR_IPV3_DR3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV3_DR3_SHIFT)) & NETC_F2_QOSVLANMPR_IPV3_DR3_MASK) 654 655 #define NETC_F2_QOSVLANMPR_IPV5_DR3_MASK (0xF0000000U) 656 #define NETC_F2_QOSVLANMPR_IPV5_DR3_SHIFT (28U) 657 #define NETC_F2_QOSVLANMPR_IPV5_DR3_WIDTH (4U) 658 #define NETC_F2_QOSVLANMPR_IPV5_DR3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV5_DR3_SHIFT)) & NETC_F2_QOSVLANMPR_IPV5_DR3_MASK) 659 660 #define NETC_F2_QOSVLANMPR_IPV7_DR3_MASK (0xF0000000U) 661 #define NETC_F2_QOSVLANMPR_IPV7_DR3_SHIFT (28U) 662 #define NETC_F2_QOSVLANMPR_IPV7_DR3_WIDTH (4U) 663 #define NETC_F2_QOSVLANMPR_IPV7_DR3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_QOSVLANMPR_IPV7_DR3_SHIFT)) & NETC_F2_QOSVLANMPR_IPV7_DR3_MASK) 664 /*! @} */ 665 666 /*! @name PCP2PCPMPR - PCP to PCP mapping profile 0 register..PCP to PCP mapping profile 1 register */ 667 /*! @{ */ 668 669 #define NETC_F2_PCP2PCPMPR_PCP0_MASK (0x7U) 670 #define NETC_F2_PCP2PCPMPR_PCP0_SHIFT (0U) 671 #define NETC_F2_PCP2PCPMPR_PCP0_WIDTH (3U) 672 #define NETC_F2_PCP2PCPMPR_PCP0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_PCP2PCPMPR_PCP0_SHIFT)) & NETC_F2_PCP2PCPMPR_PCP0_MASK) 673 674 #define NETC_F2_PCP2PCPMPR_PCP1_MASK (0x70U) 675 #define NETC_F2_PCP2PCPMPR_PCP1_SHIFT (4U) 676 #define NETC_F2_PCP2PCPMPR_PCP1_WIDTH (3U) 677 #define NETC_F2_PCP2PCPMPR_PCP1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_PCP2PCPMPR_PCP1_SHIFT)) & NETC_F2_PCP2PCPMPR_PCP1_MASK) 678 679 #define NETC_F2_PCP2PCPMPR_PCP2_MASK (0x700U) 680 #define NETC_F2_PCP2PCPMPR_PCP2_SHIFT (8U) 681 #define NETC_F2_PCP2PCPMPR_PCP2_WIDTH (3U) 682 #define NETC_F2_PCP2PCPMPR_PCP2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_PCP2PCPMPR_PCP2_SHIFT)) & NETC_F2_PCP2PCPMPR_PCP2_MASK) 683 684 #define NETC_F2_PCP2PCPMPR_PCP3_MASK (0x7000U) 685 #define NETC_F2_PCP2PCPMPR_PCP3_SHIFT (12U) 686 #define NETC_F2_PCP2PCPMPR_PCP3_WIDTH (3U) 687 #define NETC_F2_PCP2PCPMPR_PCP3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_PCP2PCPMPR_PCP3_SHIFT)) & NETC_F2_PCP2PCPMPR_PCP3_MASK) 688 689 #define NETC_F2_PCP2PCPMPR_PCP4_MASK (0x70000U) 690 #define NETC_F2_PCP2PCPMPR_PCP4_SHIFT (16U) 691 #define NETC_F2_PCP2PCPMPR_PCP4_WIDTH (3U) 692 #define NETC_F2_PCP2PCPMPR_PCP4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_PCP2PCPMPR_PCP4_SHIFT)) & NETC_F2_PCP2PCPMPR_PCP4_MASK) 693 694 #define NETC_F2_PCP2PCPMPR_PCP5_MASK (0x700000U) 695 #define NETC_F2_PCP2PCPMPR_PCP5_SHIFT (20U) 696 #define NETC_F2_PCP2PCPMPR_PCP5_WIDTH (3U) 697 #define NETC_F2_PCP2PCPMPR_PCP5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_PCP2PCPMPR_PCP5_SHIFT)) & NETC_F2_PCP2PCPMPR_PCP5_MASK) 698 699 #define NETC_F2_PCP2PCPMPR_PCP6_MASK (0x7000000U) 700 #define NETC_F2_PCP2PCPMPR_PCP6_SHIFT (24U) 701 #define NETC_F2_PCP2PCPMPR_PCP6_WIDTH (3U) 702 #define NETC_F2_PCP2PCPMPR_PCP6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_PCP2PCPMPR_PCP6_SHIFT)) & NETC_F2_PCP2PCPMPR_PCP6_MASK) 703 704 #define NETC_F2_PCP2PCPMPR_PCP7_MASK (0x70000000U) 705 #define NETC_F2_PCP2PCPMPR_PCP7_SHIFT (28U) 706 #define NETC_F2_PCP2PCPMPR_PCP7_WIDTH (3U) 707 #define NETC_F2_PCP2PCPMPR_PCP7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_PCP2PCPMPR_PCP7_SHIFT)) & NETC_F2_PCP2PCPMPR_PCP7_MASK) 708 /*! @} */ 709 710 /*! @name BRCAPR - Bridge capability register */ 711 /*! @{ */ 712 713 #define NETC_F2_BRCAPR_IPV4MFLT_MASK (0x1U) 714 #define NETC_F2_BRCAPR_IPV4MFLT_SHIFT (0U) 715 #define NETC_F2_BRCAPR_IPV4MFLT_WIDTH (1U) 716 #define NETC_F2_BRCAPR_IPV4MFLT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_BRCAPR_IPV4MFLT_SHIFT)) & NETC_F2_BRCAPR_IPV4MFLT_MASK) 717 718 #define NETC_F2_BRCAPR_STAMVD_MASK (0x4U) 719 #define NETC_F2_BRCAPR_STAMVD_SHIFT (2U) 720 #define NETC_F2_BRCAPR_STAMVD_WIDTH (1U) 721 #define NETC_F2_BRCAPR_STAMVD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_BRCAPR_STAMVD_SHIFT)) & NETC_F2_BRCAPR_STAMVD_MASK) 722 723 #define NETC_F2_BRCAPR_STRMCTRL_MASK (0x8U) 724 #define NETC_F2_BRCAPR_STRMCTRL_SHIFT (3U) 725 #define NETC_F2_BRCAPR_STRMCTRL_WIDTH (1U) 726 #define NETC_F2_BRCAPR_STRMCTRL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_BRCAPR_STRMCTRL_SHIFT)) & NETC_F2_BRCAPR_STRMCTRL_MASK) 727 728 #define NETC_F2_BRCAPR_SRCPPRND_MASK (0x10U) 729 #define NETC_F2_BRCAPR_SRCPPRND_SHIFT (4U) 730 #define NETC_F2_BRCAPR_SRCPPRND_WIDTH (1U) 731 #define NETC_F2_BRCAPR_SRCPPRND(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_BRCAPR_SRCPPRND_SHIFT)) & NETC_F2_BRCAPR_SRCPPRND_MASK) 732 733 #define NETC_F2_BRCAPR_EVLANXLATE_MASK (0x20U) 734 #define NETC_F2_BRCAPR_EVLANXLATE_SHIFT (5U) 735 #define NETC_F2_BRCAPR_EVLANXLATE_WIDTH (1U) 736 #define NETC_F2_BRCAPR_EVLANXLATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_BRCAPR_EVLANXLATE_SHIFT)) & NETC_F2_BRCAPR_EVLANXLATE_MASK) 737 738 #define NETC_F2_BRCAPR_NUM_STG_MASK (0x3000U) 739 #define NETC_F2_BRCAPR_NUM_STG_SHIFT (12U) 740 #define NETC_F2_BRCAPR_NUM_STG_WIDTH (2U) 741 #define NETC_F2_BRCAPR_NUM_STG(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_BRCAPR_NUM_STG_SHIFT)) & NETC_F2_BRCAPR_NUM_STG_MASK) 742 /*! @} */ 743 744 /*! @name VFHTCAPR - VLAN filter hash table capability register */ 745 /*! @{ */ 746 747 #define NETC_F2_VFHTCAPR_ACCESS_METH_MASK (0xF00000U) 748 #define NETC_F2_VFHTCAPR_ACCESS_METH_SHIFT (20U) 749 #define NETC_F2_VFHTCAPR_ACCESS_METH_WIDTH (4U) 750 #define NETC_F2_VFHTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTCAPR_ACCESS_METH_SHIFT)) & NETC_F2_VFHTCAPR_ACCESS_METH_MASK) 751 /*! @} */ 752 753 /*! @name VFHTOR - VLAN filter hash table operational register */ 754 /*! @{ */ 755 756 #define NETC_F2_VFHTOR_NUM_ENTRIES_MASK (0xFFFU) 757 #define NETC_F2_VFHTOR_NUM_ENTRIES_SHIFT (0U) 758 #define NETC_F2_VFHTOR_NUM_ENTRIES_WIDTH (12U) 759 #define NETC_F2_VFHTOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTOR_NUM_ENTRIES_SHIFT)) & NETC_F2_VFHTOR_NUM_ENTRIES_MASK) 760 /*! @} */ 761 762 /*! @name VFHTDECR0 - VLAN Filter (hash) table default entry configuration registers 0 */ 763 /*! @{ */ 764 765 #define NETC_F2_VFHTDECR0_PORT0_MASK (0x1U) 766 #define NETC_F2_VFHTDECR0_PORT0_SHIFT (0U) 767 #define NETC_F2_VFHTDECR0_PORT0_WIDTH (1U) 768 #define NETC_F2_VFHTDECR0_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR0_PORT0_SHIFT)) & NETC_F2_VFHTDECR0_PORT0_MASK) 769 770 #define NETC_F2_VFHTDECR0_PORT1_MASK (0x2U) 771 #define NETC_F2_VFHTDECR0_PORT1_SHIFT (1U) 772 #define NETC_F2_VFHTDECR0_PORT1_WIDTH (1U) 773 #define NETC_F2_VFHTDECR0_PORT1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR0_PORT1_SHIFT)) & NETC_F2_VFHTDECR0_PORT1_MASK) 774 775 #define NETC_F2_VFHTDECR0_PORT2_MASK (0x4U) 776 #define NETC_F2_VFHTDECR0_PORT2_SHIFT (2U) 777 #define NETC_F2_VFHTDECR0_PORT2_WIDTH (1U) 778 #define NETC_F2_VFHTDECR0_PORT2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR0_PORT2_SHIFT)) & NETC_F2_VFHTDECR0_PORT2_MASK) 779 780 #define NETC_F2_VFHTDECR0_STG_ID_MASK (0xF000000U) 781 #define NETC_F2_VFHTDECR0_STG_ID_SHIFT (24U) 782 #define NETC_F2_VFHTDECR0_STG_ID_WIDTH (4U) 783 #define NETC_F2_VFHTDECR0_STG_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR0_STG_ID_SHIFT)) & NETC_F2_VFHTDECR0_STG_ID_MASK) 784 785 #define NETC_F2_VFHTDECR0_IPMFE_MASK (0x20000000U) 786 #define NETC_F2_VFHTDECR0_IPMFE_SHIFT (29U) 787 #define NETC_F2_VFHTDECR0_IPMFE_WIDTH (1U) 788 #define NETC_F2_VFHTDECR0_IPMFE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR0_IPMFE_SHIFT)) & NETC_F2_VFHTDECR0_IPMFE_MASK) 789 790 #define NETC_F2_VFHTDECR0_IPMFLE_MASK (0x40000000U) 791 #define NETC_F2_VFHTDECR0_IPMFLE_SHIFT (30U) 792 #define NETC_F2_VFHTDECR0_IPMFLE_WIDTH (1U) 793 #define NETC_F2_VFHTDECR0_IPMFLE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR0_IPMFLE_SHIFT)) & NETC_F2_VFHTDECR0_IPMFLE_MASK) 794 /*! @} */ 795 796 /*! @name VFHTDECR1 - VLAN filter hash table default entry configuration registers 1 */ 797 /*! @{ */ 798 799 #define NETC_F2_VFHTDECR1_FID_MASK (0xFFFU) 800 #define NETC_F2_VFHTDECR1_FID_SHIFT (0U) 801 #define NETC_F2_VFHTDECR1_FID_WIDTH (12U) 802 #define NETC_F2_VFHTDECR1_FID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR1_FID_SHIFT)) & NETC_F2_VFHTDECR1_FID_MASK) 803 804 #define NETC_F2_VFHTDECR1_VL_MODE_MASK (0x1000U) 805 #define NETC_F2_VFHTDECR1_VL_MODE_SHIFT (12U) 806 #define NETC_F2_VFHTDECR1_VL_MODE_WIDTH (1U) 807 #define NETC_F2_VFHTDECR1_VL_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR1_VL_MODE_SHIFT)) & NETC_F2_VFHTDECR1_VL_MODE_MASK) 808 809 #define NETC_F2_VFHTDECR1_BASE_ETEID_MASK (0xFFFF0000U) 810 #define NETC_F2_VFHTDECR1_BASE_ETEID_SHIFT (16U) 811 #define NETC_F2_VFHTDECR1_BASE_ETEID_WIDTH (16U) 812 #define NETC_F2_VFHTDECR1_BASE_ETEID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR1_BASE_ETEID_SHIFT)) & NETC_F2_VFHTDECR1_BASE_ETEID_MASK) 813 /*! @} */ 814 815 /*! @name VFHTDECR2 - VLAN filter hash table default entry configuration registers 2 */ 816 /*! @{ */ 817 818 #define NETC_F2_VFHTDECR2_ET_PORT0_MASK (0x1U) 819 #define NETC_F2_VFHTDECR2_ET_PORT0_SHIFT (0U) 820 #define NETC_F2_VFHTDECR2_ET_PORT0_WIDTH (1U) 821 #define NETC_F2_VFHTDECR2_ET_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR2_ET_PORT0_SHIFT)) & NETC_F2_VFHTDECR2_ET_PORT0_MASK) 822 823 #define NETC_F2_VFHTDECR2_ET_PORT1_MASK (0x2U) 824 #define NETC_F2_VFHTDECR2_ET_PORT1_SHIFT (1U) 825 #define NETC_F2_VFHTDECR2_ET_PORT1_WIDTH (1U) 826 #define NETC_F2_VFHTDECR2_ET_PORT1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR2_ET_PORT1_SHIFT)) & NETC_F2_VFHTDECR2_ET_PORT1_MASK) 827 828 #define NETC_F2_VFHTDECR2_ET_PORT2_MASK (0x4U) 829 #define NETC_F2_VFHTDECR2_ET_PORT2_SHIFT (2U) 830 #define NETC_F2_VFHTDECR2_ET_PORT2_WIDTH (1U) 831 #define NETC_F2_VFHTDECR2_ET_PORT2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR2_ET_PORT2_SHIFT)) & NETC_F2_VFHTDECR2_ET_PORT2_MASK) 832 833 #define NETC_F2_VFHTDECR2_MLO_MASK (0x7000000U) 834 #define NETC_F2_VFHTDECR2_MLO_SHIFT (24U) 835 #define NETC_F2_VFHTDECR2_MLO_WIDTH (3U) 836 #define NETC_F2_VFHTDECR2_MLO(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR2_MLO_SHIFT)) & NETC_F2_VFHTDECR2_MLO_MASK) 837 838 #define NETC_F2_VFHTDECR2_MFO_MASK (0x18000000U) 839 #define NETC_F2_VFHTDECR2_MFO_SHIFT (27U) 840 #define NETC_F2_VFHTDECR2_MFO_WIDTH (2U) 841 #define NETC_F2_VFHTDECR2_MFO(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_VFHTDECR2_MFO_SHIFT)) & NETC_F2_VFHTDECR2_MFO_MASK) 842 /*! @} */ 843 844 /*! @name FDBHTCAPR - FDB hash table capability register */ 845 /*! @{ */ 846 847 #define NETC_F2_FDBHTCAPR_NUM_GMAC_MASK (0x1FFU) 848 #define NETC_F2_FDBHTCAPR_NUM_GMAC_SHIFT (0U) 849 #define NETC_F2_FDBHTCAPR_NUM_GMAC_WIDTH (9U) 850 #define NETC_F2_FDBHTCAPR_NUM_GMAC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_FDBHTCAPR_NUM_GMAC_SHIFT)) & NETC_F2_FDBHTCAPR_NUM_GMAC_MASK) 851 852 #define NETC_F2_FDBHTCAPR_ACCESS_METH_MASK (0xF00000U) 853 #define NETC_F2_FDBHTCAPR_ACCESS_METH_SHIFT (20U) 854 #define NETC_F2_FDBHTCAPR_ACCESS_METH_WIDTH (4U) 855 #define NETC_F2_FDBHTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_FDBHTCAPR_ACCESS_METH_SHIFT)) & NETC_F2_FDBHTCAPR_ACCESS_METH_MASK) 856 /*! @} */ 857 858 /*! @name FDBHTMCR - FDB hash table memory configuration register */ 859 /*! @{ */ 860 861 #define NETC_F2_FDBHTMCR_DYN_LIMIT_MASK (0xFFFFU) 862 #define NETC_F2_FDBHTMCR_DYN_LIMIT_SHIFT (0U) 863 #define NETC_F2_FDBHTMCR_DYN_LIMIT_WIDTH (16U) 864 #define NETC_F2_FDBHTMCR_DYN_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_FDBHTMCR_DYN_LIMIT_SHIFT)) & NETC_F2_FDBHTMCR_DYN_LIMIT_MASK) 865 /*! @} */ 866 867 /*! @name FDBHTOR0 - FDB hash table operational register 0 */ 868 /*! @{ */ 869 870 #define NETC_F2_FDBHTOR0_STATIC_ENTRIES_MASK (0xFFFFU) 871 #define NETC_F2_FDBHTOR0_STATIC_ENTRIES_SHIFT (0U) 872 #define NETC_F2_FDBHTOR0_STATIC_ENTRIES_WIDTH (16U) 873 #define NETC_F2_FDBHTOR0_STATIC_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_FDBHTOR0_STATIC_ENTRIES_SHIFT)) & NETC_F2_FDBHTOR0_STATIC_ENTRIES_MASK) 874 875 #define NETC_F2_FDBHTOR0_NUM_GENTRIES_MASK (0x1FF0000U) 876 #define NETC_F2_FDBHTOR0_NUM_GENTRIES_SHIFT (16U) 877 #define NETC_F2_FDBHTOR0_NUM_GENTRIES_WIDTH (9U) 878 #define NETC_F2_FDBHTOR0_NUM_GENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_FDBHTOR0_NUM_GENTRIES_SHIFT)) & NETC_F2_FDBHTOR0_NUM_GENTRIES_MASK) 879 /*! @} */ 880 881 /*! @name FDBHTOR1 - FDB hash table operational register 1 */ 882 /*! @{ */ 883 884 #define NETC_F2_FDBHTOR1_DYN_ENTRIES_MASK (0xFFFFU) 885 #define NETC_F2_FDBHTOR1_DYN_ENTRIES_SHIFT (0U) 886 #define NETC_F2_FDBHTOR1_DYN_ENTRIES_WIDTH (16U) 887 #define NETC_F2_FDBHTOR1_DYN_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_FDBHTOR1_DYN_ENTRIES_SHIFT)) & NETC_F2_FDBHTOR1_DYN_ENTRIES_MASK) 888 889 #define NETC_F2_FDBHTOR1_HWM_DYN_ENTRIES_MASK (0xFFFF0000U) 890 #define NETC_F2_FDBHTOR1_HWM_DYN_ENTRIES_SHIFT (16U) 891 #define NETC_F2_FDBHTOR1_HWM_DYN_ENTRIES_WIDTH (16U) 892 #define NETC_F2_FDBHTOR1_HWM_DYN_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_FDBHTOR1_HWM_DYN_ENTRIES_SHIFT)) & NETC_F2_FDBHTOR1_HWM_DYN_ENTRIES_MASK) 893 /*! @} */ 894 895 /*! @name IPMFHTCAPR - IP multicast filter hash table capability register */ 896 /*! @{ */ 897 898 #define NETC_F2_IPMFHTCAPR_ACCESS_METH_MASK (0xF00000U) 899 #define NETC_F2_IPMFHTCAPR_ACCESS_METH_SHIFT (20U) 900 #define NETC_F2_IPMFHTCAPR_ACCESS_METH_WIDTH (4U) 901 #define NETC_F2_IPMFHTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_IPMFHTCAPR_ACCESS_METH_SHIFT)) & NETC_F2_IPMFHTCAPR_ACCESS_METH_MASK) 902 /*! @} */ 903 904 /*! @name IPV4MFHTOR - IPv4 multicast filter hash table operation register */ 905 /*! @{ */ 906 907 #define NETC_F2_IPV4MFHTOR_ASM_ENTRIES_MASK (0xFFFFU) 908 #define NETC_F2_IPV4MFHTOR_ASM_ENTRIES_SHIFT (0U) 909 #define NETC_F2_IPV4MFHTOR_ASM_ENTRIES_WIDTH (16U) 910 #define NETC_F2_IPV4MFHTOR_ASM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_IPV4MFHTOR_ASM_ENTRIES_SHIFT)) & NETC_F2_IPV4MFHTOR_ASM_ENTRIES_MASK) 911 912 #define NETC_F2_IPV4MFHTOR_SSM_ENTRIES_MASK (0xFFFF0000U) 913 #define NETC_F2_IPV4MFHTOR_SSM_ENTRIES_SHIFT (16U) 914 #define NETC_F2_IPV4MFHTOR_SSM_ENTRIES_WIDTH (16U) 915 #define NETC_F2_IPV4MFHTOR_SSM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_IPV4MFHTOR_SSM_ENTRIES_SHIFT)) & NETC_F2_IPV4MFHTOR_SSM_ENTRIES_MASK) 916 /*! @} */ 917 918 /*! 919 * @} 920 */ /* end of group NETC_F2_Register_Masks */ 921 922 /*! 923 * @} 924 */ /* end of group NETC_F2_Peripheral_Access_Layer */ 925 926 #endif /* #if !defined(S32Z2_NETC_F2_H_) */ 927
