1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_NETC_F1.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_NETC_F1 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_NETC_F1_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_NETC_F1_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- NETC_F1 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup NETC_F1_Peripheral_Access_Layer NETC_F1 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** NETC_F1 - Register Layout Typedef */ 72 typedef struct { 73 uint8_t RESERVED_0[7168]; 74 __IO uint32_t EMDIO_CFG; /**< External MDIO configuration register, offset: 0x1C00 */ 75 __IO uint32_t EMDIO_CTL; /**< External MDIO interface control register, offset: 0x1C04 */ 76 __IO uint32_t EMDIO_DATA; /**< External MDIO interface data register, offset: 0x1C08 */ 77 __IO uint32_t EMDIO_ADDR; /**< External MDIO register address register, offset: 0x1C0C */ 78 __I uint32_t EMDIO_STAT; /**< External MDIO status register, offset: 0x1C10 */ 79 uint8_t RESERVED_1[12]; 80 __IO uint32_t PHY_STATUS_CFG; /**< PHY status configuration register, offset: 0x1C20 */ 81 __IO uint32_t PHY_STATUS_CTL; /**< PHY status control register, offset: 0x1C24 */ 82 __I uint32_t PHY_STATUS_DATA; /**< PHY status data register, offset: 0x1C28 */ 83 __IO uint32_t PHY_STATUS_ADDR; /**< PHY status register address register, offset: 0x1C2C */ 84 __IO uint32_t PHY_STATUS_EVENT; /**< PHY status event register, offset: 0x1C30 */ 85 __IO uint32_t PHY_STATUS_MASK; /**< PHY status mask register, offset: 0x1C34 */ 86 uint8_t RESERVED_2[8]; 87 __I uint32_t MDIO_CFG; /**< MDIO configuration register, offset: 0x1C40 */ 88 } NETC_F1_Type, *NETC_F1_MemMapPtr; 89 90 /** Number of instances of the NETC_F1 module. */ 91 #define NETC_F1_INSTANCE_COUNT (1u) 92 93 /* NETC_F1 - Peripheral instance base addresses */ 94 /** Peripheral NETC__EMDIO_BASE base address */ 95 #define IP_NETC__EMDIO_BASE_BASE (0x74B60000u) 96 /** Peripheral NETC__EMDIO_BASE base pointer */ 97 #define IP_NETC__EMDIO_BASE ((NETC_F1_Type *)IP_NETC__EMDIO_BASE_BASE) 98 /** Array initializer of NETC_F1 peripheral base addresses */ 99 #define IP_NETC_F1_BASE_ADDRS { IP_NETC__EMDIO_BASE_BASE } 100 /** Array initializer of NETC_F1 peripheral base pointers */ 101 #define IP_NETC_F1_BASE_PTRS { IP_NETC__EMDIO_BASE } 102 103 /* ---------------------------------------------------------------------------- 104 -- NETC_F1 Register Masks 105 ---------------------------------------------------------------------------- */ 106 107 /*! 108 * @addtogroup NETC_F1_Register_Masks NETC_F1 Register Masks 109 * @{ 110 */ 111 112 /*! @name EMDIO_CFG - External MDIO configuration register */ 113 /*! @{ */ 114 115 #define NETC_F1_EMDIO_CFG_BSY2_MASK (0x1U) 116 #define NETC_F1_EMDIO_CFG_BSY2_SHIFT (0U) 117 #define NETC_F1_EMDIO_CFG_BSY2_WIDTH (1U) 118 #define NETC_F1_EMDIO_CFG_BSY2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_BSY2_SHIFT)) & NETC_F1_EMDIO_CFG_BSY2_MASK) 119 120 #define NETC_F1_EMDIO_CFG_MDIO_RD_ER_MASK (0x2U) 121 #define NETC_F1_EMDIO_CFG_MDIO_RD_ER_SHIFT (1U) 122 #define NETC_F1_EMDIO_CFG_MDIO_RD_ER_WIDTH (1U) 123 #define NETC_F1_EMDIO_CFG_MDIO_RD_ER(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_MDIO_RD_ER_SHIFT)) & NETC_F1_EMDIO_CFG_MDIO_RD_ER_MASK) 124 125 #define NETC_F1_EMDIO_CFG_MDIO_HOLD_MASK (0x1CU) 126 #define NETC_F1_EMDIO_CFG_MDIO_HOLD_SHIFT (2U) 127 #define NETC_F1_EMDIO_CFG_MDIO_HOLD_WIDTH (3U) 128 #define NETC_F1_EMDIO_CFG_MDIO_HOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_MDIO_HOLD_SHIFT)) & NETC_F1_EMDIO_CFG_MDIO_HOLD_MASK) 129 130 #define NETC_F1_EMDIO_CFG_PRE_DIS_MASK (0x20U) 131 #define NETC_F1_EMDIO_CFG_PRE_DIS_SHIFT (5U) 132 #define NETC_F1_EMDIO_CFG_PRE_DIS_WIDTH (1U) 133 #define NETC_F1_EMDIO_CFG_PRE_DIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_PRE_DIS_SHIFT)) & NETC_F1_EMDIO_CFG_PRE_DIS_MASK) 134 135 #define NETC_F1_EMDIO_CFG_ENC45_MASK (0x40U) 136 #define NETC_F1_EMDIO_CFG_ENC45_SHIFT (6U) 137 #define NETC_F1_EMDIO_CFG_ENC45_WIDTH (1U) 138 #define NETC_F1_EMDIO_CFG_ENC45(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_ENC45_SHIFT)) & NETC_F1_EMDIO_CFG_ENC45_MASK) 139 140 #define NETC_F1_EMDIO_CFG_MDIO_CLK_DIV_MASK (0xFF80U) 141 #define NETC_F1_EMDIO_CFG_MDIO_CLK_DIV_SHIFT (7U) 142 #define NETC_F1_EMDIO_CFG_MDIO_CLK_DIV_WIDTH (9U) 143 #define NETC_F1_EMDIO_CFG_MDIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_MDIO_CLK_DIV_SHIFT)) & NETC_F1_EMDIO_CFG_MDIO_CLK_DIV_MASK) 144 145 #define NETC_F1_EMDIO_CFG_WHOAMI_MASK (0x70000U) 146 #define NETC_F1_EMDIO_CFG_WHOAMI_SHIFT (16U) 147 #define NETC_F1_EMDIO_CFG_WHOAMI_WIDTH (3U) 148 #define NETC_F1_EMDIO_CFG_WHOAMI(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_WHOAMI_SHIFT)) & NETC_F1_EMDIO_CFG_WHOAMI_MASK) 149 150 #define NETC_F1_EMDIO_CFG_EHOLD_MASK (0x400000U) 151 #define NETC_F1_EMDIO_CFG_EHOLD_SHIFT (22U) 152 #define NETC_F1_EMDIO_CFG_EHOLD_WIDTH (1U) 153 #define NETC_F1_EMDIO_CFG_EHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_EHOLD_SHIFT)) & NETC_F1_EMDIO_CFG_EHOLD_MASK) 154 155 #define NETC_F1_EMDIO_CFG_NEG_MASK (0x800000U) 156 #define NETC_F1_EMDIO_CFG_NEG_SHIFT (23U) 157 #define NETC_F1_EMDIO_CFG_NEG_WIDTH (1U) 158 #define NETC_F1_EMDIO_CFG_NEG(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_NEG_SHIFT)) & NETC_F1_EMDIO_CFG_NEG_MASK) 159 160 #define NETC_F1_EMDIO_CFG_ADDR_ERR_MASK (0x10000000U) 161 #define NETC_F1_EMDIO_CFG_ADDR_ERR_SHIFT (28U) 162 #define NETC_F1_EMDIO_CFG_ADDR_ERR_WIDTH (1U) 163 #define NETC_F1_EMDIO_CFG_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_ADDR_ERR_SHIFT)) & NETC_F1_EMDIO_CFG_ADDR_ERR_MASK) 164 165 #define NETC_F1_EMDIO_CFG_CIM_MASK (0x20000000U) 166 #define NETC_F1_EMDIO_CFG_CIM_SHIFT (29U) 167 #define NETC_F1_EMDIO_CFG_CIM_WIDTH (1U) 168 #define NETC_F1_EMDIO_CFG_CIM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_CIM_SHIFT)) & NETC_F1_EMDIO_CFG_CIM_MASK) 169 170 #define NETC_F1_EMDIO_CFG_CMP_MASK (0x40000000U) 171 #define NETC_F1_EMDIO_CFG_CMP_SHIFT (30U) 172 #define NETC_F1_EMDIO_CFG_CMP_WIDTH (1U) 173 #define NETC_F1_EMDIO_CFG_CMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_CMP_SHIFT)) & NETC_F1_EMDIO_CFG_CMP_MASK) 174 175 #define NETC_F1_EMDIO_CFG_BSY1_MASK (0x80000000U) 176 #define NETC_F1_EMDIO_CFG_BSY1_SHIFT (31U) 177 #define NETC_F1_EMDIO_CFG_BSY1_WIDTH (1U) 178 #define NETC_F1_EMDIO_CFG_BSY1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CFG_BSY1_SHIFT)) & NETC_F1_EMDIO_CFG_BSY1_MASK) 179 /*! @} */ 180 181 /*! @name EMDIO_CTL - External MDIO interface control register */ 182 /*! @{ */ 183 184 #define NETC_F1_EMDIO_CTL_DEV_ADDR_MASK (0x1FU) 185 #define NETC_F1_EMDIO_CTL_DEV_ADDR_SHIFT (0U) 186 #define NETC_F1_EMDIO_CTL_DEV_ADDR_WIDTH (5U) 187 #define NETC_F1_EMDIO_CTL_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CTL_DEV_ADDR_SHIFT)) & NETC_F1_EMDIO_CTL_DEV_ADDR_MASK) 188 189 #define NETC_F1_EMDIO_CTL_PORT_ADDR_MASK (0x3E0U) 190 #define NETC_F1_EMDIO_CTL_PORT_ADDR_SHIFT (5U) 191 #define NETC_F1_EMDIO_CTL_PORT_ADDR_WIDTH (5U) 192 #define NETC_F1_EMDIO_CTL_PORT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CTL_PORT_ADDR_SHIFT)) & NETC_F1_EMDIO_CTL_PORT_ADDR_MASK) 193 194 #define NETC_F1_EMDIO_CTL_POST_INC_MASK (0x4000U) 195 #define NETC_F1_EMDIO_CTL_POST_INC_SHIFT (14U) 196 #define NETC_F1_EMDIO_CTL_POST_INC_WIDTH (1U) 197 #define NETC_F1_EMDIO_CTL_POST_INC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CTL_POST_INC_SHIFT)) & NETC_F1_EMDIO_CTL_POST_INC_MASK) 198 199 #define NETC_F1_EMDIO_CTL_READ_MASK (0x8000U) 200 #define NETC_F1_EMDIO_CTL_READ_SHIFT (15U) 201 #define NETC_F1_EMDIO_CTL_READ_WIDTH (1U) 202 #define NETC_F1_EMDIO_CTL_READ(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CTL_READ_SHIFT)) & NETC_F1_EMDIO_CTL_READ_MASK) 203 204 #define NETC_F1_EMDIO_CTL_BSY_MASK (0x80000000U) 205 #define NETC_F1_EMDIO_CTL_BSY_SHIFT (31U) 206 #define NETC_F1_EMDIO_CTL_BSY_WIDTH (1U) 207 #define NETC_F1_EMDIO_CTL_BSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_CTL_BSY_SHIFT)) & NETC_F1_EMDIO_CTL_BSY_MASK) 208 /*! @} */ 209 210 /*! @name EMDIO_DATA - External MDIO interface data register */ 211 /*! @{ */ 212 213 #define NETC_F1_EMDIO_DATA_MDIO_DATA_MASK (0xFFFFU) 214 #define NETC_F1_EMDIO_DATA_MDIO_DATA_SHIFT (0U) 215 #define NETC_F1_EMDIO_DATA_MDIO_DATA_WIDTH (16U) 216 #define NETC_F1_EMDIO_DATA_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_DATA_MDIO_DATA_SHIFT)) & NETC_F1_EMDIO_DATA_MDIO_DATA_MASK) 217 /*! @} */ 218 219 /*! @name EMDIO_ADDR - External MDIO register address register */ 220 /*! @{ */ 221 222 #define NETC_F1_EMDIO_ADDR_REGADDR_MASK (0xFFFFU) 223 #define NETC_F1_EMDIO_ADDR_REGADDR_SHIFT (0U) 224 #define NETC_F1_EMDIO_ADDR_REGADDR_WIDTH (16U) 225 #define NETC_F1_EMDIO_ADDR_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_ADDR_REGADDR_SHIFT)) & NETC_F1_EMDIO_ADDR_REGADDR_MASK) 226 /*! @} */ 227 228 /*! @name EMDIO_STAT - External MDIO status register */ 229 /*! @{ */ 230 231 #define NETC_F1_EMDIO_STAT_BSY_MASK (0x1U) 232 #define NETC_F1_EMDIO_STAT_BSY_SHIFT (0U) 233 #define NETC_F1_EMDIO_STAT_BSY_WIDTH (1U) 234 #define NETC_F1_EMDIO_STAT_BSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_STAT_BSY_SHIFT)) & NETC_F1_EMDIO_STAT_BSY_MASK) 235 236 #define NETC_F1_EMDIO_STAT_WHT_LIST_MASK (0x1F00U) 237 #define NETC_F1_EMDIO_STAT_WHT_LIST_SHIFT (8U) 238 #define NETC_F1_EMDIO_STAT_WHT_LIST_WIDTH (5U) 239 #define NETC_F1_EMDIO_STAT_WHT_LIST(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_STAT_WHT_LIST_SHIFT)) & NETC_F1_EMDIO_STAT_WHT_LIST_MASK) 240 241 #define NETC_F1_EMDIO_STAT_WHT_LIST_ENA_MASK (0x8000U) 242 #define NETC_F1_EMDIO_STAT_WHT_LIST_ENA_SHIFT (15U) 243 #define NETC_F1_EMDIO_STAT_WHT_LIST_ENA_WIDTH (1U) 244 #define NETC_F1_EMDIO_STAT_WHT_LIST_ENA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_STAT_WHT_LIST_ENA_SHIFT)) & NETC_F1_EMDIO_STAT_WHT_LIST_ENA_MASK) 245 246 #define NETC_F1_EMDIO_STAT_PORT_ID_MASK (0x70000U) 247 #define NETC_F1_EMDIO_STAT_PORT_ID_SHIFT (16U) 248 #define NETC_F1_EMDIO_STAT_PORT_ID_WIDTH (3U) 249 #define NETC_F1_EMDIO_STAT_PORT_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_STAT_PORT_ID_SHIFT)) & NETC_F1_EMDIO_STAT_PORT_ID_MASK) 250 251 #define NETC_F1_EMDIO_STAT_REQ_TYPE_MASK (0x80000U) 252 #define NETC_F1_EMDIO_STAT_REQ_TYPE_SHIFT (19U) 253 #define NETC_F1_EMDIO_STAT_REQ_TYPE_WIDTH (1U) 254 #define NETC_F1_EMDIO_STAT_REQ_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_EMDIO_STAT_REQ_TYPE_SHIFT)) & NETC_F1_EMDIO_STAT_REQ_TYPE_MASK) 255 /*! @} */ 256 257 /*! @name PHY_STATUS_CFG - PHY status configuration register */ 258 /*! @{ */ 259 260 #define NETC_F1_PHY_STATUS_CFG_BSY_MASK (0x1U) 261 #define NETC_F1_PHY_STATUS_CFG_BSY_SHIFT (0U) 262 #define NETC_F1_PHY_STATUS_CFG_BSY_WIDTH (1U) 263 #define NETC_F1_PHY_STATUS_CFG_BSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_PHY_STATUS_CFG_BSY_SHIFT)) & NETC_F1_PHY_STATUS_CFG_BSY_MASK) 264 265 #define NETC_F1_PHY_STATUS_CFG_MDIO_RD_ER_MASK (0x2U) 266 #define NETC_F1_PHY_STATUS_CFG_MDIO_RD_ER_SHIFT (1U) 267 #define NETC_F1_PHY_STATUS_CFG_MDIO_RD_ER_WIDTH (1U) 268 #define NETC_F1_PHY_STATUS_CFG_MDIO_RD_ER(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_PHY_STATUS_CFG_MDIO_RD_ER_SHIFT)) & NETC_F1_PHY_STATUS_CFG_MDIO_RD_ER_MASK) 269 270 #define NETC_F1_PHY_STATUS_CFG_STATUS_INTERVAL_MASK (0xFFFF0000U) 271 #define NETC_F1_PHY_STATUS_CFG_STATUS_INTERVAL_SHIFT (16U) 272 #define NETC_F1_PHY_STATUS_CFG_STATUS_INTERVAL_WIDTH (16U) 273 #define NETC_F1_PHY_STATUS_CFG_STATUS_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_PHY_STATUS_CFG_STATUS_INTERVAL_SHIFT)) & NETC_F1_PHY_STATUS_CFG_STATUS_INTERVAL_MASK) 274 /*! @} */ 275 276 /*! @name PHY_STATUS_CTL - PHY status control register */ 277 /*! @{ */ 278 279 #define NETC_F1_PHY_STATUS_CTL_DEV_ADDR_MASK (0x1FU) 280 #define NETC_F1_PHY_STATUS_CTL_DEV_ADDR_SHIFT (0U) 281 #define NETC_F1_PHY_STATUS_CTL_DEV_ADDR_WIDTH (5U) 282 #define NETC_F1_PHY_STATUS_CTL_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_PHY_STATUS_CTL_DEV_ADDR_SHIFT)) & NETC_F1_PHY_STATUS_CTL_DEV_ADDR_MASK) 283 284 #define NETC_F1_PHY_STATUS_CTL_PORT_ADDR_MASK (0x3E0U) 285 #define NETC_F1_PHY_STATUS_CTL_PORT_ADDR_SHIFT (5U) 286 #define NETC_F1_PHY_STATUS_CTL_PORT_ADDR_WIDTH (5U) 287 #define NETC_F1_PHY_STATUS_CTL_PORT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_PHY_STATUS_CTL_PORT_ADDR_SHIFT)) & NETC_F1_PHY_STATUS_CTL_PORT_ADDR_MASK) 288 /*! @} */ 289 290 /*! @name PHY_STATUS_DATA - PHY status data register */ 291 /*! @{ */ 292 293 #define NETC_F1_PHY_STATUS_DATA_MDIO_DATA_MASK (0xFFFFU) 294 #define NETC_F1_PHY_STATUS_DATA_MDIO_DATA_SHIFT (0U) 295 #define NETC_F1_PHY_STATUS_DATA_MDIO_DATA_WIDTH (16U) 296 #define NETC_F1_PHY_STATUS_DATA_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_PHY_STATUS_DATA_MDIO_DATA_SHIFT)) & NETC_F1_PHY_STATUS_DATA_MDIO_DATA_MASK) 297 298 #define NETC_F1_PHY_STATUS_DATA_CURR_CNT_MASK (0xFFFF0000U) 299 #define NETC_F1_PHY_STATUS_DATA_CURR_CNT_SHIFT (16U) 300 #define NETC_F1_PHY_STATUS_DATA_CURR_CNT_WIDTH (16U) 301 #define NETC_F1_PHY_STATUS_DATA_CURR_CNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_PHY_STATUS_DATA_CURR_CNT_SHIFT)) & NETC_F1_PHY_STATUS_DATA_CURR_CNT_MASK) 302 /*! @} */ 303 304 /*! @name PHY_STATUS_ADDR - PHY status register address register */ 305 /*! @{ */ 306 307 #define NETC_F1_PHY_STATUS_ADDR_REGADDR_MASK (0xFFFFU) 308 #define NETC_F1_PHY_STATUS_ADDR_REGADDR_SHIFT (0U) 309 #define NETC_F1_PHY_STATUS_ADDR_REGADDR_WIDTH (16U) 310 #define NETC_F1_PHY_STATUS_ADDR_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_PHY_STATUS_ADDR_REGADDR_SHIFT)) & NETC_F1_PHY_STATUS_ADDR_REGADDR_MASK) 311 /*! @} */ 312 313 /*! @name PHY_STATUS_EVENT - PHY status event register */ 314 /*! @{ */ 315 316 #define NETC_F1_PHY_STATUS_EVENT_STATUS_EVENT_HL_MASK (0xFFFFU) 317 #define NETC_F1_PHY_STATUS_EVENT_STATUS_EVENT_HL_SHIFT (0U) 318 #define NETC_F1_PHY_STATUS_EVENT_STATUS_EVENT_HL_WIDTH (16U) 319 #define NETC_F1_PHY_STATUS_EVENT_STATUS_EVENT_HL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_PHY_STATUS_EVENT_STATUS_EVENT_HL_SHIFT)) & NETC_F1_PHY_STATUS_EVENT_STATUS_EVENT_HL_MASK) 320 321 #define NETC_F1_PHY_STATUS_EVENT_STATUS_EVENT_LH_MASK (0xFFFF0000U) 322 #define NETC_F1_PHY_STATUS_EVENT_STATUS_EVENT_LH_SHIFT (16U) 323 #define NETC_F1_PHY_STATUS_EVENT_STATUS_EVENT_LH_WIDTH (16U) 324 #define NETC_F1_PHY_STATUS_EVENT_STATUS_EVENT_LH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_PHY_STATUS_EVENT_STATUS_EVENT_LH_SHIFT)) & NETC_F1_PHY_STATUS_EVENT_STATUS_EVENT_LH_MASK) 325 /*! @} */ 326 327 /*! @name PHY_STATUS_MASK - PHY status mask register */ 328 /*! @{ */ 329 330 #define NETC_F1_PHY_STATUS_MASK_STATUS_MASK_HL_MASK (0xFFFFU) 331 #define NETC_F1_PHY_STATUS_MASK_STATUS_MASK_HL_SHIFT (0U) 332 #define NETC_F1_PHY_STATUS_MASK_STATUS_MASK_HL_WIDTH (16U) 333 #define NETC_F1_PHY_STATUS_MASK_STATUS_MASK_HL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_PHY_STATUS_MASK_STATUS_MASK_HL_SHIFT)) & NETC_F1_PHY_STATUS_MASK_STATUS_MASK_HL_MASK) 334 335 #define NETC_F1_PHY_STATUS_MASK_STATUS_MASK_LH_MASK (0xFFFF0000U) 336 #define NETC_F1_PHY_STATUS_MASK_STATUS_MASK_LH_SHIFT (16U) 337 #define NETC_F1_PHY_STATUS_MASK_STATUS_MASK_LH_WIDTH (16U) 338 #define NETC_F1_PHY_STATUS_MASK_STATUS_MASK_LH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_PHY_STATUS_MASK_STATUS_MASK_LH_SHIFT)) & NETC_F1_PHY_STATUS_MASK_STATUS_MASK_LH_MASK) 339 /*! @} */ 340 341 /*! @name MDIO_CFG - MDIO configuration register */ 342 /*! @{ */ 343 344 #define NETC_F1_MDIO_CFG_MDIO_MODE_MASK (0x10U) 345 #define NETC_F1_MDIO_CFG_MDIO_MODE_SHIFT (4U) 346 #define NETC_F1_MDIO_CFG_MDIO_MODE_WIDTH (1U) 347 #define NETC_F1_MDIO_CFG_MDIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_MDIO_CFG_MDIO_MODE_SHIFT)) & NETC_F1_MDIO_CFG_MDIO_MODE_MASK) 348 349 #define NETC_F1_MDIO_CFG_MDC_MODE_MASK (0x20U) 350 #define NETC_F1_MDIO_CFG_MDC_MODE_SHIFT (5U) 351 #define NETC_F1_MDIO_CFG_MDC_MODE_WIDTH (1U) 352 #define NETC_F1_MDIO_CFG_MDC_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_MDIO_CFG_MDC_MODE_SHIFT)) & NETC_F1_MDIO_CFG_MDC_MODE_MASK) 353 /*! @} */ 354 355 /*! 356 * @} 357 */ /* end of group NETC_F1_Register_Masks */ 358 359 /*! 360 * @} 361 */ /* end of group NETC_F1_Peripheral_Access_Layer */ 362 363 #endif /* #if !defined(S32Z2_NETC_F1_H_) */ 364
