1 /* 2 * Copyright 2022-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NETC_ETH_IP_SA_INIT_PBCFG_H 8 #define NETC_ETH_IP_SA_INIT_PBCFG_H 9 10 #define NETC_ETH_IP_SA_INIT_PBCFG_VENDOR_ID 43 11 #define NETC_ETH_IP_SA_INIT_PBCFG_AR_RELEASE_MAJOR_VERSION 4 12 #define NETC_ETH_IP_SA_INIT_PBCFG_AR_RELEASE_MINOR_VERSION 7 13 #define NETC_ETH_IP_SA_INIT_PBCFG_AR_RELEASE_REVISION_VERSION 0 14 #define NETC_ETH_IP_SA_INIT_PBCFG_SW_MAJOR_VERSION 1 15 #define NETC_ETH_IP_SA_INIT_PBCFG_SW_MINOR_VERSION 0 16 #define NETC_ETH_IP_SA_INIT_PBCFG_SW_PATCH_VERSION 0 17 18 /* Not used but required to build the baremetal drivers */ 19 #define NETC_ETH_IP_CONFIG_SA_INIT_PB 20 21 /* Maximum number of TX descriptors */ 22 #define NETC_ETH_MAX_NUMBER_OF_TXBD CONFIG_ETH_NXP_S32_TX_RING_BUF_SIZE 23 24 #endif /* NETC_ETH_IP_SA_INIT_PBCFG_H */ 25
