1 /******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18
19 /********************************************************************************************************
20 * @file core.h
21 *
22 * @brief This is the header file for B91
23 *
24 * @author Driver Group
25 *
26 *******************************************************************************************************/
27 #ifndef CORE_H
28 #define CORE_H
29 #include "sys.h"
30
31 #define NDS_MIE 0x304
32 #define NDS_MILMB 0x7C0
33 #define NDS_MDLMB 0x7C1
34 #define NDS_MSTATUS 0x300
35
36 #define read_csr(var, csr) __asm__ volatile ("csrr %0, %1" : "=r" (var) : "i" (csr))
37 #define write_csr(csr, val) __asm__ volatile ("csrw %0, %1" :: "i" (csr), "r" (val))
38 #define set_csr(csr, bit) __asm__ volatile ("csrs %0, %1" :: "i" (csr), "r" (bit))
39 #define clear_csr(csr, bit) __asm__ volatile ("csrc %0, %1" :: "i" (csr), "r" (bit))
40
41 /*
42 * Inline nested interrupt entry/exit macros
43 */
44 /* Svae/Restore macro */
45 #define save_csr(r) long __##r; \
46 read_csr(__##r,r);
47 #define restore_csr(r) write_csr(r, __##r);
48 /* Support PowerBrake (Performance Throttling) feature */
49
50
51 #define save_mxstatus() save_csr(NDS_MXSTATUS)
52 #define restore_mxstatus() restore_csr(NDS_MXSTATUS)
53
54 /* Nested IRQ entry macro : Save CSRs and enable global interrupt. */
55 #define core_save_nested_context() \
56 save_csr(NDS_MEPC) \
57 save_csr(NDS_MSTATUS) \
58 save_mxstatus() \
59 set_csr(NDS_MSTATUS, 1<<3);
60
61 /* Nested IRQ exit macro : Restore CSRs */
62 #define core_restore_nested_context() \
63 clear_csr(NDS_MSTATUS, 1<<3); \
64 restore_csr(NDS_MSTATUS) \
65 restore_csr(NDS_MEPC) \
66 restore_mxstatus()
67
68 typedef enum{
69 FLD_FEATURE_PREEMPT_PRIORITY_INT_EN = BIT(0),
70 FLD_FEATURE_VECTOR_MODE_EN = BIT(1),
71 }
72 feature_e;
73
74
75 /**
76 * @brief Disable interrupts globally in the system.external, timer and software interrupts.
77 * @return r - the value of machine interrupt enable(MIE) register.
78 * @note this function must be used when the system wants to disable all the interrupt.
79 */
core_interrupt_disable(void)80 static inline unsigned int core_interrupt_disable(void){
81
82 unsigned int r;
83 read_csr (r, NDS_MIE);
84 clear_csr(NDS_MIE, BIT(3)| BIT(7)| BIT(11));
85 return r;
86 }
87
88
89 /**
90 * @brief restore interrupts globally in the system. external,timer and software interrupts.
91 * @param[in] en - the value of machine interrupt enable(MIE) register before disable.
92 * @return 0
93 * @note this function must be used when the system wants to restore all the interrupt.
94 */
core_restore_interrupt(unsigned int en)95 static inline unsigned int core_restore_interrupt(unsigned int en){
96
97 set_csr(NDS_MIE, en);
98 return 0;
99 }
100
101 /**
102 * @brief enable interrupts globally in the system.
103 * @return none
104 */
core_interrupt_enable(void)105 static inline void core_interrupt_enable(void)
106 {
107 set_csr(NDS_MSTATUS,1<<3);
108 set_csr(NDS_MIE,1<<11 | 1 << 7 | 1 << 3);
109
110 }
111 #endif
112
