1 /* 2 * Copyright (c) 2018-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <plat/arm/board/common/v2m_def.h> 11 #include <plat/arm/common/arm_def.h> 12 #include <plat/arm/css/common/css_def.h> 13 14 /* UART related constants */ 15 #define PLAT_ARM_BOOT_UART_BASE 0x2A400000 16 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000 17 18 /* IOFPGA UART0 */ 19 #define PLAT_ARM_RUN_UART_BASE 0x1C090000 20 #define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000 21 22 #define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000 23 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000 24 25 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 26 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 27 28 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 29 #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000) 30 31 #define MAX_IO_DEVICES U(3) 32 #define MAX_IO_HANDLES U(4) 33 34 #define PLAT_ARM_FLASH_IMAGE_BASE 0x18200000 35 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE 0x00800000 36 37 #define PLAT_ARM_NVM_BASE 0x18200000 38 #define PLAT_ARM_NVM_SIZE 0x00800000 39 40 #if defined NS_BL1U_BASE 41 # undef NS_BL1U_BASE 42 # define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x00800000)) 43 #endif 44 45 /* Non-volatile counters */ 46 #define SOC_TRUSTED_NVCTR_BASE 0x7fe70000 47 #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE) 48 #define TFW_NVCTR_SIZE U(4) 49 #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) 50 #define NTFW_CTR_SIZE U(4) 51 52 /* N1SDP remote chip at 4 TB offset */ 53 #define PLAT_ARM_REMOTE_CHIP_OFFSET (ULL(1) << 42) 54 55 #define N1SDP_REMOTE_DRAM1_BASE ARM_DRAM1_BASE + \ 56 PLAT_ARM_REMOTE_CHIP_OFFSET 57 #define N1SDP_REMOTE_DRAM1_SIZE ARM_DRAM1_SIZE 58 59 #define N1SDP_REMOTE_DRAM2_BASE PLAT_ARM_DRAM2_BASE + \ 60 PLAT_ARM_REMOTE_CHIP_OFFSET 61 #define N1SDP_REMOTE_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 62 63 /* 64 * N1SDP platform supports RDIMMs with ECC capability. To use the ECC 65 * capability, the entire DDR memory space has to be zeroed out before 66 * enabling the ECC bits in DMC620. To access the complete DDR memory 67 * along with remote chip's DDR memory, which is at 4 TB offset, physical 68 * and virtual address space limits are extended to 43-bits. 69 */ 70 #ifdef __aarch64__ 71 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) 72 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) 73 #else 74 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 75 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 76 #endif 77 78 #if CSS_USE_SCMI_SDS_DRIVER 79 #define N1SDP_SCMI_PAYLOAD_BASE 0x45400000 80 #else 81 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 82 #endif 83 84 /* 85 * Trusted SRAM in N1SDP is 512 KB but only the bottom 384 KB 86 * is used for trusted board boot flow. The top 128 KB is used 87 * to load AP-BL1 image. 88 */ 89 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00060000 /* 384 KB */ 90 91 /* 92 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 93 * plus a little space for growth. 94 */ 95 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 96 97 /* 98 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 99 */ 100 101 #if USE_ROMLIB 102 # define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 103 # define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 104 #else 105 # define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0) 106 # define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0) 107 #endif 108 109 /* 110 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 111 * little space for growth. 112 */ 113 #if TRUSTED_BOARD_BOOT 114 # define PLAT_ARM_MAX_BL2_SIZE 0x22000 115 #else 116 # define PLAT_ARM_MAX_BL2_SIZE 0x14000 117 #endif 118 119 #define PLAT_ARM_MAX_BL31_SIZE UL(0x40000) 120 121 #define PLAT_ARM_SPMC_BASE U(0x08000000) 122 #define PLAT_ARM_SPMC_SIZE UL(0x02000000) /* 32 MB */ 123 124 125 /******************************************************************************* 126 * N1SDP topology related constants 127 ******************************************************************************/ 128 #define N1SDP_MAX_CPUS_PER_CLUSTER U(2) 129 #define PLAT_ARM_CLUSTER_COUNT U(2) 130 #define PLAT_N1SDP_CHIP_COUNT U(2) 131 #define N1SDP_MAX_CLUSTERS_PER_CHIP U(2) 132 #define N1SDP_MAX_PE_PER_CPU U(1) 133 134 #define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \ 135 PLAT_ARM_CLUSTER_COUNT * \ 136 N1SDP_MAX_CPUS_PER_CLUSTER * \ 137 N1SDP_MAX_PE_PER_CPU) 138 139 /* System power domain level */ 140 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 141 142 /* 143 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 144 * plat_arm_mmap array defined for each BL stage. 145 */ 146 147 #ifdef IMAGE_BL1 148 # define PLAT_ARM_MMAP_ENTRIES U(6) 149 # define MAX_XLAT_TABLES U(5) 150 #endif 151 152 #ifdef IMAGE_BL2 153 # define PLAT_ARM_MMAP_ENTRIES U(11) 154 # define MAX_XLAT_TABLES U(10) 155 #endif 156 157 #ifdef IMAGE_BL31 158 # define PLAT_ARM_MMAP_ENTRIES U(12) 159 # define MAX_XLAT_TABLES U(12) 160 #endif 161 162 /* 163 * Size of cacheable stacks 164 */ 165 #if defined(IMAGE_BL1) 166 # if TRUSTED_BOARD_BOOT 167 # define PLATFORM_STACK_SIZE 0x1000 168 # else 169 # define PLATFORM_STACK_SIZE 0x440 170 # endif 171 #elif defined(IMAGE_BL2) 172 # if TRUSTED_BOARD_BOOT 173 # define PLATFORM_STACK_SIZE 0x1000 174 # else 175 # define PLATFORM_STACK_SIZE 0x400 176 # endif 177 #elif defined(IMAGE_BL2U) 178 # define PLATFORM_STACK_SIZE 0x400 179 #elif defined(IMAGE_BL31) 180 # if SPM_MM 181 # define PLATFORM_STACK_SIZE 0x500 182 # else 183 # define PLATFORM_STACK_SIZE 0x400 184 # endif 185 #elif defined(IMAGE_BL32) 186 # define PLATFORM_STACK_SIZE 0x440 187 #endif 188 189 #define PLAT_ARM_NSTIMER_FRAME_ID 0 190 #define PLAT_CSS_MHU_BASE 0x45000000 191 #define PLAT_MAX_PWR_LVL 2 192 193 /* Interrupt handling constants */ 194 #define N1SDP_IRQ_MMU_TCU1_EVENT_Q_SEC U(257) 195 #define N1SDP_IRQ_MMU_TCU1_CMD_SYNC_SEC U(258) 196 #define N1SDP_IRQ_MMU_TCU1_GLOBAL U(259) 197 #define N1SDP_IRQ_MMU_TCU2_EVENT_Q_SEC U(264) 198 #define N1SDP_IRQ_MMU_TCU2_CMD_SYNC_SEC U(265) 199 #define N1SDP_IRQ_MMU_TCU2_GLOBAL U(266) 200 #define N1SDP_IRQ_CLUSTER0_MHU U(349) 201 #define N1SDP_IRQ_CLUSTER1_MHU U(351) 202 #define N1SDP_IRQ_P0_REFCLK U(412) 203 #define N1SDP_IRQ_P1_REFCLK U(413) 204 205 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 206 ARM_G1S_IRQ_PROPS(grp), \ 207 INTR_PROP_DESC(CSS_IRQ_MHU, \ 208 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 209 INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, \ 210 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 211 INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, \ 212 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 213 INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU1_EVENT_Q_SEC, \ 214 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 215 INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU1_CMD_SYNC_SEC, \ 216 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 217 INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU1_GLOBAL, \ 218 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 219 INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU2_EVENT_Q_SEC, \ 220 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 221 INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU2_CMD_SYNC_SEC, \ 222 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 223 INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU2_GLOBAL, \ 224 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 225 INTR_PROP_DESC(N1SDP_IRQ_CLUSTER0_MHU, \ 226 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 227 INTR_PROP_DESC(N1SDP_IRQ_CLUSTER1_MHU, \ 228 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 229 INTR_PROP_DESC(N1SDP_IRQ_P0_REFCLK, \ 230 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 231 INTR_PROP_DESC(N1SDP_IRQ_P1_REFCLK, \ 232 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL) 233 234 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 235 236 237 #define N1SDP_DEVICE_BASE ULL(0x08000000) 238 #define N1SDP_DEVICE_SIZE ULL(0x48000000) 239 #define N1SDP_REMOTE_DEVICE_BASE N1SDP_DEVICE_BASE + \ 240 PLAT_ARM_REMOTE_CHIP_OFFSET 241 #define N1SDP_REMOTE_DEVICE_SIZE N1SDP_DEVICE_SIZE 242 243 /* Real base is 0x0. Changed to load BL1 at this address */ 244 # define PLAT_ARM_TRUSTED_ROM_BASE 0x04060000 245 # define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 /* 128KB */ 246 247 #define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \ 248 N1SDP_DEVICE_BASE, \ 249 N1SDP_DEVICE_SIZE, \ 250 MT_DEVICE | MT_RW | MT_SECURE) 251 252 #define ARM_MAP_DRAM1 MAP_REGION_FLAT( \ 253 ARM_DRAM1_BASE, \ 254 ARM_DRAM1_SIZE, \ 255 MT_MEMORY | MT_RW | MT_NS) 256 257 #define N1SDP_MAP_REMOTE_DEVICE MAP_REGION_FLAT( \ 258 N1SDP_REMOTE_DEVICE_BASE, \ 259 N1SDP_REMOTE_DEVICE_SIZE, \ 260 MT_DEVICE | MT_RW | MT_SECURE) 261 262 #define N1SDP_MAP_REMOTE_DRAM1 MAP_REGION_FLAT( \ 263 N1SDP_REMOTE_DRAM1_BASE, \ 264 N1SDP_REMOTE_DRAM1_SIZE, \ 265 MT_MEMORY | MT_RW | MT_NS) 266 267 #define N1SDP_MAP_REMOTE_DRAM2 MAP_REGION_FLAT( \ 268 N1SDP_REMOTE_DRAM2_BASE, \ 269 N1SDP_REMOTE_DRAM2_SIZE, \ 270 MT_MEMORY | MT_RW | MT_NS) 271 272 /* GIC related constants */ 273 #define PLAT_ARM_GICD_BASE 0x30000000 274 #define PLAT_ARM_GICC_BASE 0x2C000000 275 #define PLAT_ARM_GICR_BASE 0x300C0000 276 277 /* Platform ID address */ 278 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) 279 280 /* Secure Watchdog Constants */ 281 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 282 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 283 284 /* Number of SCMI channels on the platform */ 285 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 286 287 #endif /* PLATFORM_DEF_H */ 288
