1 /** 2 * @file skbd_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SKBD Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup skbd_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SKBD_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SKBD_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup skbd 67 * @defgroup skbd_registers SKBD_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SKBD Peripheral Module. 69 * @details Secure Keyboard 70 */ 71 72 /** 73 * @ingroup skbd_registers 74 * Structure type to access the SKBD Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl0; /**< <tt>\b 0x00:</tt> SKBD CTRL0 Register */ 78 __IO uint32_t ctrl1; /**< <tt>\b 0x04:</tt> SKBD CTRL1 Register */ 79 __I uint32_t status; /**< <tt>\b 0x08:</tt> SKBD STATUS Register */ 80 __IO uint32_t inten; /**< <tt>\b 0x0C:</tt> SKBD INTEN Register */ 81 __IO uint32_t intfl; /**< <tt>\b 0x10:</tt> SKBD INTFL Register */ 82 __I uint32_t evt[4]; /**< <tt>\b 0x14:</tt> SKBD EVT Register */ 83 __IO uint32_t gpio0; /**< <tt>\b 0x24:</tt> SKBD GPIO0 Register */ 84 __IO uint32_t gpio1; /**< <tt>\b 0x28:</tt> SKBD GPIO1 Register */ 85 } mxc_skbd_regs_t; 86 87 /* Register offsets for module SKBD */ 88 /** 89 * @ingroup skbd_registers 90 * @defgroup SKBD_Register_Offsets Register Offsets 91 * @brief SKBD Peripheral Register Offsets from the SKBD Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_SKBD_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from SKBD Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_SKBD_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from SKBD Base Address: <tt> 0x0004</tt> */ 96 #define MXC_R_SKBD_STATUS ((uint32_t)0x00000008UL) /**< Offset from SKBD Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_SKBD_INTEN ((uint32_t)0x0000000CUL) /**< Offset from SKBD Base Address: <tt> 0x000C</tt> */ 98 #define MXC_R_SKBD_INTFL ((uint32_t)0x00000010UL) /**< Offset from SKBD Base Address: <tt> 0x0010</tt> */ 99 #define MXC_R_SKBD_EVT ((uint32_t)0x00000014UL) /**< Offset from SKBD Base Address: <tt> 0x0014</tt> */ 100 #define MXC_R_SKBD_GPIO0 ((uint32_t)0x00000024UL) /**< Offset from SKBD Base Address: <tt> 0x0024</tt> */ 101 #define MXC_R_SKBD_GPIO1 ((uint32_t)0x00000028UL) /**< Offset from SKBD Base Address: <tt> 0x0028</tt> */ 102 /**@} end of group skbd_registers */ 103 104 /** 105 * @ingroup skbd_registers 106 * @defgroup SKBD_CTRL0 SKBD_CTRL0 107 * @brief Input Output Select Bits. Each bit of IOSEL selects the pin direction for the 108 * corresponding KBDIO pin. If IOSEL[0] = 1, KBDIO0 is an output. 109 * @{ 110 */ 111 #define MXC_F_SKBD_CTRL0_KBDIO0_POS 0 /**< CTRL0_KBDIO0 Position */ 112 #define MXC_F_SKBD_CTRL0_KBDIO0 ((uint32_t)(0x1UL << MXC_F_SKBD_CTRL0_KBDIO0_POS)) /**< CTRL0_KBDIO0 Mask */ 113 114 #define MXC_F_SKBD_CTRL0_KBDIO1_POS 1 /**< CTRL0_KBDIO1 Position */ 115 #define MXC_F_SKBD_CTRL0_KBDIO1 ((uint32_t)(0x1UL << MXC_F_SKBD_CTRL0_KBDIO1_POS)) /**< CTRL0_KBDIO1 Mask */ 116 117 #define MXC_F_SKBD_CTRL0_KBDIO2_POS 2 /**< CTRL0_KBDIO2 Position */ 118 #define MXC_F_SKBD_CTRL0_KBDIO2 ((uint32_t)(0x1UL << MXC_F_SKBD_CTRL0_KBDIO2_POS)) /**< CTRL0_KBDIO2 Mask */ 119 120 #define MXC_F_SKBD_CTRL0_KBDIO3_POS 3 /**< CTRL0_KBDIO3 Position */ 121 #define MXC_F_SKBD_CTRL0_KBDIO3 ((uint32_t)(0x1UL << MXC_F_SKBD_CTRL0_KBDIO3_POS)) /**< CTRL0_KBDIO3 Mask */ 122 123 #define MXC_F_SKBD_CTRL0_KBDIO4_POS 4 /**< CTRL0_KBDIO4 Position */ 124 #define MXC_F_SKBD_CTRL0_KBDIO4 ((uint32_t)(0x1UL << MXC_F_SKBD_CTRL0_KBDIO4_POS)) /**< CTRL0_KBDIO4 Mask */ 125 126 #define MXC_F_SKBD_CTRL0_KBDIO5_POS 5 /**< CTRL0_KBDIO5 Position */ 127 #define MXC_F_SKBD_CTRL0_KBDIO5 ((uint32_t)(0x1UL << MXC_F_SKBD_CTRL0_KBDIO5_POS)) /**< CTRL0_KBDIO5 Mask */ 128 129 #define MXC_F_SKBD_CTRL0_KBDIO6_POS 6 /**< CTRL0_KBDIO6 Position */ 130 #define MXC_F_SKBD_CTRL0_KBDIO6 ((uint32_t)(0x1UL << MXC_F_SKBD_CTRL0_KBDIO6_POS)) /**< CTRL0_KBDIO6 Mask */ 131 132 #define MXC_F_SKBD_CTRL0_KBDIO7_POS 7 /**< CTRL0_KBDIO7 Position */ 133 #define MXC_F_SKBD_CTRL0_KBDIO7 ((uint32_t)(0x1UL << MXC_F_SKBD_CTRL0_KBDIO7_POS)) /**< CTRL0_KBDIO7 Mask */ 134 135 #define MXC_F_SKBD_CTRL0_KBDIO8_POS 8 /**< CTRL0_KBDIO8 Position */ 136 #define MXC_F_SKBD_CTRL0_KBDIO8 ((uint32_t)(0x1UL << MXC_F_SKBD_CTRL0_KBDIO8_POS)) /**< CTRL0_KBDIO8 Mask */ 137 138 #define MXC_F_SKBD_CTRL0_KBDIO9_POS 9 /**< CTRL0_KBDIO9 Position */ 139 #define MXC_F_SKBD_CTRL0_KBDIO9 ((uint32_t)(0x1UL << MXC_F_SKBD_CTRL0_KBDIO9_POS)) /**< CTRL0_KBDIO9 Mask */ 140 141 /**@} end of group SKBD_CTRL0_Register */ 142 143 /** 144 * @ingroup skbd_registers 145 * @defgroup SKBD_CTRL1 SKBD_CTRL1 146 * @brief Control Register 1 147 * @{ 148 */ 149 #define MXC_F_SKBD_CTRL1_AUTOSCAN_EN_POS 0 /**< CTRL1_AUTOSCAN_EN Position */ 150 #define MXC_F_SKBD_CTRL1_AUTOSCAN_EN ((uint32_t)(0x1UL << MXC_F_SKBD_CTRL1_AUTOSCAN_EN_POS)) /**< CTRL1_AUTOSCAN_EN Mask */ 151 152 #define MXC_F_SKBD_CTRL1_AUTOCLEAR_POS 1 /**< CTRL1_AUTOCLEAR Position */ 153 #define MXC_F_SKBD_CTRL1_AUTOCLEAR ((uint32_t)(0x1UL << MXC_F_SKBD_CTRL1_AUTOCLEAR_POS)) /**< CTRL1_AUTOCLEAR Mask */ 154 155 #define MXC_F_SKBD_CTRL1_OUTNUM_POS 8 /**< CTRL1_OUTNUM Position */ 156 #define MXC_F_SKBD_CTRL1_OUTNUM ((uint32_t)(0xFUL << MXC_F_SKBD_CTRL1_OUTNUM_POS)) /**< CTRL1_OUTNUM Mask */ 157 158 #define MXC_F_SKBD_CTRL1_DBTM_POS 13 /**< CTRL1_DBTM Position */ 159 #define MXC_F_SKBD_CTRL1_DBTM ((uint32_t)(0x7UL << MXC_F_SKBD_CTRL1_DBTM_POS)) /**< CTRL1_DBTM Mask */ 160 #define MXC_V_SKBD_CTRL1_DBTM_TIME4MS ((uint32_t)0x0UL) /**< CTRL1_DBTM_TIME4MS Value */ 161 #define MXC_S_SKBD_CTRL1_DBTM_TIME4MS (MXC_V_SKBD_CTRL1_DBTM_TIME4MS << MXC_F_SKBD_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME4MS Setting */ 162 #define MXC_V_SKBD_CTRL1_DBTM_TIME5MS ((uint32_t)0x1UL) /**< CTRL1_DBTM_TIME5MS Value */ 163 #define MXC_S_SKBD_CTRL1_DBTM_TIME5MS (MXC_V_SKBD_CTRL1_DBTM_TIME5MS << MXC_F_SKBD_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME5MS Setting */ 164 #define MXC_V_SKBD_CTRL1_DBTM_TIME6MS ((uint32_t)0x2UL) /**< CTRL1_DBTM_TIME6MS Value */ 165 #define MXC_S_SKBD_CTRL1_DBTM_TIME6MS (MXC_V_SKBD_CTRL1_DBTM_TIME6MS << MXC_F_SKBD_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME6MS Setting */ 166 #define MXC_V_SKBD_CTRL1_DBTM_TIME7MS ((uint32_t)0x3UL) /**< CTRL1_DBTM_TIME7MS Value */ 167 #define MXC_S_SKBD_CTRL1_DBTM_TIME7MS (MXC_V_SKBD_CTRL1_DBTM_TIME7MS << MXC_F_SKBD_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME7MS Setting */ 168 #define MXC_V_SKBD_CTRL1_DBTM_TIME8MS ((uint32_t)0x4UL) /**< CTRL1_DBTM_TIME8MS Value */ 169 #define MXC_S_SKBD_CTRL1_DBTM_TIME8MS (MXC_V_SKBD_CTRL1_DBTM_TIME8MS << MXC_F_SKBD_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME8MS Setting */ 170 #define MXC_V_SKBD_CTRL1_DBTM_TIME10MS ((uint32_t)0x5UL) /**< CTRL1_DBTM_TIME10MS Value */ 171 #define MXC_S_SKBD_CTRL1_DBTM_TIME10MS (MXC_V_SKBD_CTRL1_DBTM_TIME10MS << MXC_F_SKBD_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME10MS Setting */ 172 #define MXC_V_SKBD_CTRL1_DBTM_TIME11MS ((uint32_t)0x6UL) /**< CTRL1_DBTM_TIME11MS Value */ 173 #define MXC_S_SKBD_CTRL1_DBTM_TIME11MS (MXC_V_SKBD_CTRL1_DBTM_TIME11MS << MXC_F_SKBD_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME11MS Setting */ 174 #define MXC_V_SKBD_CTRL1_DBTM_TIME12MS ((uint32_t)0x7UL) /**< CTRL1_DBTM_TIME12MS Value */ 175 #define MXC_S_SKBD_CTRL1_DBTM_TIME12MS (MXC_V_SKBD_CTRL1_DBTM_TIME12MS << MXC_F_SKBD_CTRL1_DBTM_POS) /**< CTRL1_DBTM_TIME12MS Setting */ 176 177 /**@} end of group SKBD_CTRL1_Register */ 178 179 /** 180 * @ingroup skbd_registers 181 * @defgroup SKBD_STATUS SKBD_STATUS 182 * @brief Status Register 183 * @{ 184 */ 185 #define MXC_F_SKBD_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ 186 #define MXC_F_SKBD_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_SKBD_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ 187 188 /**@} end of group SKBD_STATUS_Register */ 189 190 /** 191 * @ingroup skbd_registers 192 * @defgroup SKBD_INTEN SKBD_INTEN 193 * @brief Interrupt Enable Register 194 * @{ 195 */ 196 #define MXC_F_SKBD_INTEN_PUSH_POS 0 /**< INTEN_PUSH Position */ 197 #define MXC_F_SKBD_INTEN_PUSH ((uint32_t)(0x1UL << MXC_F_SKBD_INTEN_PUSH_POS)) /**< INTEN_PUSH Mask */ 198 199 #define MXC_F_SKBD_INTEN_RELEASE_POS 1 /**< INTEN_RELEASE Position */ 200 #define MXC_F_SKBD_INTEN_RELEASE ((uint32_t)(0x1UL << MXC_F_SKBD_INTEN_RELEASE_POS)) /**< INTEN_RELEASE Mask */ 201 202 #define MXC_F_SKBD_INTEN_OVERRUN_POS 2 /**< INTEN_OVERRUN Position */ 203 #define MXC_F_SKBD_INTEN_OVERRUN ((uint32_t)(0x1UL << MXC_F_SKBD_INTEN_OVERRUN_POS)) /**< INTEN_OVERRUN Mask */ 204 205 #define MXC_F_SKBD_INTEN_KBD_PINS_POS 3 /**< INTEN_KBD_PINS Position */ 206 #define MXC_F_SKBD_INTEN_KBD_PINS ((uint32_t)(0x1UL << MXC_F_SKBD_INTEN_KBD_PINS_POS)) /**< INTEN_KBD_PINS Mask */ 207 208 /**@} end of group SKBD_INTEN_Register */ 209 210 /** 211 * @ingroup skbd_registers 212 * @defgroup SKBD_INTFL SKBD_INTFL 213 * @brief Interrupt Status Register 214 * @{ 215 */ 216 #define MXC_F_SKBD_INTFL_PUSH_POS 0 /**< INTFL_PUSH Position */ 217 #define MXC_F_SKBD_INTFL_PUSH ((uint32_t)(0x1UL << MXC_F_SKBD_INTFL_PUSH_POS)) /**< INTFL_PUSH Mask */ 218 219 #define MXC_F_SKBD_INTFL_RELEASE_POS 1 /**< INTFL_RELEASE Position */ 220 #define MXC_F_SKBD_INTFL_RELEASE ((uint32_t)(0x1UL << MXC_F_SKBD_INTFL_RELEASE_POS)) /**< INTFL_RELEASE Mask */ 221 222 #define MXC_F_SKBD_INTFL_OVERRUN_POS 2 /**< INTFL_OVERRUN Position */ 223 #define MXC_F_SKBD_INTFL_OVERRUN ((uint32_t)(0x1UL << MXC_F_SKBD_INTFL_OVERRUN_POS)) /**< INTFL_OVERRUN Mask */ 224 225 /**@} end of group SKBD_INTFL_Register */ 226 227 /** 228 * @ingroup skbd_registers 229 * @defgroup SKBD_EVT SKBD_EVT 230 * @brief Key Register 231 * @{ 232 */ 233 #define MXC_F_SKBD_EVT_IOIN_POS 0 /**< EVT_IOIN Position */ 234 #define MXC_F_SKBD_EVT_IOIN ((uint32_t)(0x7UL << MXC_F_SKBD_EVT_IOIN_POS)) /**< EVT_IOIN Mask */ 235 236 #define MXC_F_SKBD_EVT_IOOUT_POS 5 /**< EVT_IOOUT Position */ 237 #define MXC_F_SKBD_EVT_IOOUT ((uint32_t)(0x7UL << MXC_F_SKBD_EVT_IOOUT_POS)) /**< EVT_IOOUT Mask */ 238 239 #define MXC_F_SKBD_EVT_PUSH_POS 10 /**< EVT_PUSH Position */ 240 #define MXC_F_SKBD_EVT_PUSH ((uint32_t)(0x1UL << MXC_F_SKBD_EVT_PUSH_POS)) /**< EVT_PUSH Mask */ 241 242 #define MXC_F_SKBD_EVT_READ_POS 11 /**< EVT_READ Position */ 243 #define MXC_F_SKBD_EVT_READ ((uint32_t)(0x1UL << MXC_F_SKBD_EVT_READ_POS)) /**< EVT_READ Mask */ 244 245 #define MXC_F_SKBD_EVT_NEXT_POS 12 /**< EVT_NEXT Position */ 246 #define MXC_F_SKBD_EVT_NEXT ((uint32_t)(0x1UL << MXC_F_SKBD_EVT_NEXT_POS)) /**< EVT_NEXT Mask */ 247 248 /**@} end of group SKBD_EVT_Register */ 249 250 /** 251 * @ingroup skbd_registers 252 * @defgroup SKBD_GPIO0 SKBD_GPIO0 253 * @brief General Purpose Register 0. 254 * @{ 255 */ 256 #define MXC_F_SKBD_GPIO0_ALL_POS 0 /**< GPIO0_ALL Position */ 257 #define MXC_F_SKBD_GPIO0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_SKBD_GPIO0_ALL_POS)) /**< GPIO0_ALL Mask */ 258 259 /**@} end of group SKBD_GPIO0_Register */ 260 261 /** 262 * @ingroup skbd_registers 263 * @defgroup SKBD_GPIO1 SKBD_GPIO1 264 * @brief General Purpose Register 1. 265 * @{ 266 */ 267 #define MXC_F_SKBD_GPIO1_ALL_POS 0 /**< GPIO1_ALL Position */ 268 #define MXC_F_SKBD_GPIO1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_SKBD_GPIO1_ALL_POS)) /**< GPIO1_ALL Mask */ 269 270 /**@} end of group SKBD_GPIO1_Register */ 271 272 #ifdef __cplusplus 273 } 274 #endif 275 276 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SKBD_REGS_H_ 277
