1 /** 2 * @file dma_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup dma_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_DMA_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_DMA_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup dma 67 * @defgroup dma_registers DMA_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. 69 * @details DMA Controller Fully programmable, chaining capable DMA channels. 70 */ 71 72 /** 73 * @ingroup dma_registers 74 * Structure type to access the DMA Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> DMA CTRL Register */ 78 __IO uint32_t status; /**< <tt>\b 0x004:</tt> DMA STATUS Register */ 79 __IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */ 80 __IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */ 81 __IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */ 82 __IO uint32_t srcrld; /**< <tt>\b 0x014:</tt> DMA SRCRLD Register */ 83 __IO uint32_t dstrld; /**< <tt>\b 0x018:</tt> DMA DSTRLD Register */ 84 __IO uint32_t cntrld; /**< <tt>\b 0x01C:</tt> DMA CNTRLD Register */ 85 } mxc_dma_ch_regs_t; 86 87 typedef struct { 88 __IO uint32_t inten; /**< <tt>\b 0x000:</tt> DMA INTEN Register */ 89 __I uint32_t intfl; /**< <tt>\b 0x004:</tt> DMA INTFL Register */ 90 __R uint32_t rsv_0x8_0xff[62]; 91 __IO mxc_dma_ch_regs_t ch[16]; /**< <tt>\b 0x100:</tt> DMA CH Register */ 92 } mxc_dma_regs_t; 93 94 /* Register offsets for module DMA */ 95 /** 96 * @ingroup dma_registers 97 * @defgroup DMA_Register_Offsets Register Offsets 98 * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. 99 * @{ 100 */ 101 #define MXC_R_DMA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ 102 #define MXC_R_DMA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ 103 #define MXC_R_DMA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0008</tt> */ 104 #define MXC_R_DMA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x000C</tt> */ 105 #define MXC_R_DMA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0010</tt> */ 106 #define MXC_R_DMA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0014</tt> */ 107 #define MXC_R_DMA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0018</tt> */ 108 #define MXC_R_DMA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x001C</tt> */ 109 #define MXC_R_DMA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ 110 #define MXC_R_DMA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ 111 #define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ 112 /**@} end of group dma_registers */ 113 114 /** 115 * @ingroup dma_registers 116 * @defgroup DMA_INTEN DMA_INTEN 117 * @brief DMA Interrupt Enable Register. 118 * @{ 119 */ 120 #define MXC_F_DMA_INTEN_CH0_POS 0 /**< INTEN_CH0 Position */ 121 #define MXC_F_DMA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */ 122 123 #define MXC_F_DMA_INTEN_CH1_POS 1 /**< INTEN_CH1 Position */ 124 #define MXC_F_DMA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */ 125 126 #define MXC_F_DMA_INTEN_CH2_POS 2 /**< INTEN_CH2 Position */ 127 #define MXC_F_DMA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */ 128 129 #define MXC_F_DMA_INTEN_CH3_POS 3 /**< INTEN_CH3 Position */ 130 #define MXC_F_DMA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */ 131 132 #define MXC_F_DMA_INTEN_CH4_POS 4 /**< INTEN_CH4 Position */ 133 #define MXC_F_DMA_INTEN_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH4_POS)) /**< INTEN_CH4 Mask */ 134 135 #define MXC_F_DMA_INTEN_CH5_POS 5 /**< INTEN_CH5 Position */ 136 #define MXC_F_DMA_INTEN_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH5_POS)) /**< INTEN_CH5 Mask */ 137 138 #define MXC_F_DMA_INTEN_CH6_POS 6 /**< INTEN_CH6 Position */ 139 #define MXC_F_DMA_INTEN_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH6_POS)) /**< INTEN_CH6 Mask */ 140 141 #define MXC_F_DMA_INTEN_CH7_POS 7 /**< INTEN_CH7 Position */ 142 #define MXC_F_DMA_INTEN_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH7_POS)) /**< INTEN_CH7 Mask */ 143 144 #define MXC_F_DMA_INTEN_CH8_POS 8 /**< INTEN_CH8 Position */ 145 #define MXC_F_DMA_INTEN_CH8 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH8_POS)) /**< INTEN_CH8 Mask */ 146 147 #define MXC_F_DMA_INTEN_CH9_POS 9 /**< INTEN_CH9 Position */ 148 #define MXC_F_DMA_INTEN_CH9 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH9_POS)) /**< INTEN_CH9 Mask */ 149 150 #define MXC_F_DMA_INTEN_CH10_POS 10 /**< INTEN_CH10 Position */ 151 #define MXC_F_DMA_INTEN_CH10 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH10_POS)) /**< INTEN_CH10 Mask */ 152 153 #define MXC_F_DMA_INTEN_CH11_POS 11 /**< INTEN_CH11 Position */ 154 #define MXC_F_DMA_INTEN_CH11 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH11_POS)) /**< INTEN_CH11 Mask */ 155 156 #define MXC_F_DMA_INTEN_CH12_POS 12 /**< INTEN_CH12 Position */ 157 #define MXC_F_DMA_INTEN_CH12 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH12_POS)) /**< INTEN_CH12 Mask */ 158 159 #define MXC_F_DMA_INTEN_CH13_POS 13 /**< INTEN_CH13 Position */ 160 #define MXC_F_DMA_INTEN_CH13 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH13_POS)) /**< INTEN_CH13 Mask */ 161 162 #define MXC_F_DMA_INTEN_CH14_POS 14 /**< INTEN_CH14 Position */ 163 #define MXC_F_DMA_INTEN_CH14 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH14_POS)) /**< INTEN_CH14 Mask */ 164 165 #define MXC_F_DMA_INTEN_CH15_POS 15 /**< INTEN_CH15 Position */ 166 #define MXC_F_DMA_INTEN_CH15 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH15_POS)) /**< INTEN_CH15 Mask */ 167 168 /**@} end of group DMA_INTEN_Register */ 169 170 /** 171 * @ingroup dma_registers 172 * @defgroup DMA_INTFL DMA_INTFL 173 * @brief DMA Interrupt Flag Register. 174 * @{ 175 */ 176 #define MXC_F_DMA_INTFL_CH0_POS 0 /**< INTFL_CH0 Position */ 177 #define MXC_F_DMA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */ 178 179 #define MXC_F_DMA_INTFL_CH1_POS 1 /**< INTFL_CH1 Position */ 180 #define MXC_F_DMA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */ 181 182 #define MXC_F_DMA_INTFL_CH2_POS 2 /**< INTFL_CH2 Position */ 183 #define MXC_F_DMA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */ 184 185 #define MXC_F_DMA_INTFL_CH3_POS 3 /**< INTFL_CH3 Position */ 186 #define MXC_F_DMA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */ 187 188 #define MXC_F_DMA_INTFL_CH4_POS 4 /**< INTFL_CH4 Position */ 189 #define MXC_F_DMA_INTFL_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH4_POS)) /**< INTFL_CH4 Mask */ 190 191 #define MXC_F_DMA_INTFL_CH5_POS 5 /**< INTFL_CH5 Position */ 192 #define MXC_F_DMA_INTFL_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH5_POS)) /**< INTFL_CH5 Mask */ 193 194 #define MXC_F_DMA_INTFL_CH6_POS 6 /**< INTFL_CH6 Position */ 195 #define MXC_F_DMA_INTFL_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH6_POS)) /**< INTFL_CH6 Mask */ 196 197 #define MXC_F_DMA_INTFL_CH7_POS 7 /**< INTFL_CH7 Position */ 198 #define MXC_F_DMA_INTFL_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH7_POS)) /**< INTFL_CH7 Mask */ 199 200 #define MXC_F_DMA_INTFL_CH8_POS 8 /**< INTFL_CH8 Position */ 201 #define MXC_F_DMA_INTFL_CH8 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH8_POS)) /**< INTFL_CH8 Mask */ 202 203 #define MXC_F_DMA_INTFL_CH9_POS 9 /**< INTFL_CH9 Position */ 204 #define MXC_F_DMA_INTFL_CH9 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH9_POS)) /**< INTFL_CH9 Mask */ 205 206 #define MXC_F_DMA_INTFL_CH10_POS 10 /**< INTFL_CH10 Position */ 207 #define MXC_F_DMA_INTFL_CH10 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH10_POS)) /**< INTFL_CH10 Mask */ 208 209 #define MXC_F_DMA_INTFL_CH11_POS 11 /**< INTFL_CH11 Position */ 210 #define MXC_F_DMA_INTFL_CH11 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH11_POS)) /**< INTFL_CH11 Mask */ 211 212 #define MXC_F_DMA_INTFL_CH12_POS 12 /**< INTFL_CH12 Position */ 213 #define MXC_F_DMA_INTFL_CH12 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH12_POS)) /**< INTFL_CH12 Mask */ 214 215 #define MXC_F_DMA_INTFL_CH13_POS 13 /**< INTFL_CH13 Position */ 216 #define MXC_F_DMA_INTFL_CH13 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH13_POS)) /**< INTFL_CH13 Mask */ 217 218 #define MXC_F_DMA_INTFL_CH14_POS 14 /**< INTFL_CH14 Position */ 219 #define MXC_F_DMA_INTFL_CH14 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH14_POS)) /**< INTFL_CH14 Mask */ 220 221 #define MXC_F_DMA_INTFL_CH15_POS 15 /**< INTFL_CH15 Position */ 222 #define MXC_F_DMA_INTFL_CH15 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH15_POS)) /**< INTFL_CH15 Mask */ 223 224 /**@} end of group DMA_INTFL_Register */ 225 226 /** 227 * @ingroup dma_registers 228 * @defgroup DMA_CTRL DMA_CTRL 229 * @brief DMA Channel Control Register. 230 * @{ 231 */ 232 #define MXC_F_DMA_CTRL_EN_POS 0 /**< CTRL_EN Position */ 233 #define MXC_F_DMA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS)) /**< CTRL_EN Mask */ 234 235 #define MXC_F_DMA_CTRL_RLDEN_POS 1 /**< CTRL_RLDEN Position */ 236 #define MXC_F_DMA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */ 237 238 #define MXC_F_DMA_CTRL_PRI_POS 2 /**< CTRL_PRI Position */ 239 #define MXC_F_DMA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */ 240 #define MXC_V_DMA_CTRL_PRI_HIGH ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */ 241 #define MXC_S_DMA_CTRL_PRI_HIGH (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */ 242 #define MXC_V_DMA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */ 243 #define MXC_S_DMA_CTRL_PRI_MEDHIGH (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */ 244 #define MXC_V_DMA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */ 245 #define MXC_S_DMA_CTRL_PRI_MEDLOW (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */ 246 #define MXC_V_DMA_CTRL_PRI_LOW ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */ 247 #define MXC_S_DMA_CTRL_PRI_LOW (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */ 248 249 #define MXC_F_DMA_CTRL_REQUEST_POS 4 /**< CTRL_REQUEST Position */ 250 #define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */ 251 #define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */ 252 #define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */ 253 #define MXC_V_DMA_CTRL_REQUEST_SPI0RX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI0RX Value */ 254 #define MXC_S_DMA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */ 255 #define MXC_V_DMA_CTRL_REQUEST_SPI1RX ((uint32_t)0x2UL) /**< CTRL_REQUEST_SPI1RX Value */ 256 #define MXC_S_DMA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */ 257 #define MXC_V_DMA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */ 258 #define MXC_S_DMA_CTRL_REQUEST_UART0RX (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */ 259 #define MXC_V_DMA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */ 260 #define MXC_S_DMA_CTRL_REQUEST_UART1RX (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */ 261 #define MXC_V_DMA_CTRL_REQUEST_SC0RX ((uint32_t)0x6UL) /**< CTRL_REQUEST_SC0RX Value */ 262 #define MXC_S_DMA_CTRL_REQUEST_SC0RX (MXC_V_DMA_CTRL_REQUEST_SC0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SC0RX Setting */ 263 #define MXC_V_DMA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */ 264 #define MXC_S_DMA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */ 265 #define MXC_V_DMA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */ 266 #define MXC_S_DMA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */ 267 #define MXC_V_DMA_CTRL_REQUEST_ADC ((uint32_t)0x9UL) /**< CTRL_REQUEST_ADC Value */ 268 #define MXC_S_DMA_CTRL_REQUEST_ADC (MXC_V_DMA_CTRL_REQUEST_ADC << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_ADC Setting */ 269 #define MXC_V_DMA_CTRL_REQUEST_MSRADC ((uint32_t)0xBUL) /**< CTRL_REQUEST_MSRADC Value */ 270 #define MXC_S_DMA_CTRL_REQUEST_MSRADC (MXC_V_DMA_CTRL_REQUEST_MSRADC << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MSRADC Setting */ 271 #define MXC_V_DMA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */ 272 #define MXC_S_DMA_CTRL_REQUEST_UART2RX (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */ 273 #define MXC_V_DMA_CTRL_REQUEST_SPI3RX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI3RX Value */ 274 #define MXC_S_DMA_CTRL_REQUEST_SPI3RX (MXC_V_DMA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3RX Setting */ 275 #define MXC_V_DMA_CTRL_REQUEST_USBRXEP1 ((uint32_t)0x11UL) /**< CTRL_REQUEST_USBRXEP1 Value */ 276 #define MXC_S_DMA_CTRL_REQUEST_USBRXEP1 (MXC_V_DMA_CTRL_REQUEST_USBRXEP1 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP1 Setting */ 277 #define MXC_V_DMA_CTRL_REQUEST_USBRXEP2 ((uint32_t)0x12UL) /**< CTRL_REQUEST_USBRXEP2 Value */ 278 #define MXC_S_DMA_CTRL_REQUEST_USBRXEP2 (MXC_V_DMA_CTRL_REQUEST_USBRXEP2 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP2 Setting */ 279 #define MXC_V_DMA_CTRL_REQUEST_USBRXEP3 ((uint32_t)0x13UL) /**< CTRL_REQUEST_USBRXEP3 Value */ 280 #define MXC_S_DMA_CTRL_REQUEST_USBRXEP3 (MXC_V_DMA_CTRL_REQUEST_USBRXEP3 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP3 Setting */ 281 #define MXC_V_DMA_CTRL_REQUEST_USBRXEP4 ((uint32_t)0x14UL) /**< CTRL_REQUEST_USBRXEP4 Value */ 282 #define MXC_S_DMA_CTRL_REQUEST_USBRXEP4 (MXC_V_DMA_CTRL_REQUEST_USBRXEP4 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP4 Setting */ 283 #define MXC_V_DMA_CTRL_REQUEST_USBRXEP5 ((uint32_t)0x15UL) /**< CTRL_REQUEST_USBRXEP5 Value */ 284 #define MXC_S_DMA_CTRL_REQUEST_USBRXEP5 (MXC_V_DMA_CTRL_REQUEST_USBRXEP5 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP5 Setting */ 285 #define MXC_V_DMA_CTRL_REQUEST_USBRXEP6 ((uint32_t)0x16UL) /**< CTRL_REQUEST_USBRXEP6 Value */ 286 #define MXC_S_DMA_CTRL_REQUEST_USBRXEP6 (MXC_V_DMA_CTRL_REQUEST_USBRXEP6 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP6 Setting */ 287 #define MXC_V_DMA_CTRL_REQUEST_USBRXEP7 ((uint32_t)0x17UL) /**< CTRL_REQUEST_USBRXEP7 Value */ 288 #define MXC_S_DMA_CTRL_REQUEST_USBRXEP7 (MXC_V_DMA_CTRL_REQUEST_USBRXEP7 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP7 Setting */ 289 #define MXC_V_DMA_CTRL_REQUEST_USBRXEP8 ((uint32_t)0x18UL) /**< CTRL_REQUEST_USBRXEP8 Value */ 290 #define MXC_S_DMA_CTRL_REQUEST_USBRXEP8 (MXC_V_DMA_CTRL_REQUEST_USBRXEP8 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP8 Setting */ 291 #define MXC_V_DMA_CTRL_REQUEST_USBRXEP9 ((uint32_t)0x19UL) /**< CTRL_REQUEST_USBRXEP9 Value */ 292 #define MXC_S_DMA_CTRL_REQUEST_USBRXEP9 (MXC_V_DMA_CTRL_REQUEST_USBRXEP9 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP9 Setting */ 293 #define MXC_V_DMA_CTRL_REQUEST_USBRXEP10 ((uint32_t)0x1AUL) /**< CTRL_REQUEST_USBRXEP10 Value */ 294 #define MXC_S_DMA_CTRL_REQUEST_USBRXEP10 (MXC_V_DMA_CTRL_REQUEST_USBRXEP10 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP10 Setting */ 295 #define MXC_V_DMA_CTRL_REQUEST_USBRXEP11 ((uint32_t)0x1BUL) /**< CTRL_REQUEST_USBRXEP11 Value */ 296 #define MXC_S_DMA_CTRL_REQUEST_USBRXEP11 (MXC_V_DMA_CTRL_REQUEST_USBRXEP11 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP11 Setting */ 297 #define MXC_V_DMA_CTRL_REQUEST_UART3RX ((uint32_t)0x1CUL) /**< CTRL_REQUEST_UART3RX Value */ 298 #define MXC_S_DMA_CTRL_REQUEST_UART3RX (MXC_V_DMA_CTRL_REQUEST_UART3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3RX Setting */ 299 #define MXC_V_DMA_CTRL_REQUEST_SPI0TX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI0TX Value */ 300 #define MXC_S_DMA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */ 301 #define MXC_V_DMA_CTRL_REQUEST_SPI1TX ((uint32_t)0x22UL) /**< CTRL_REQUEST_SPI1TX Value */ 302 #define MXC_S_DMA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */ 303 #define MXC_V_DMA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */ 304 #define MXC_S_DMA_CTRL_REQUEST_UART0TX (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */ 305 #define MXC_V_DMA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */ 306 #define MXC_S_DMA_CTRL_REQUEST_UART1TX (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */ 307 #define MXC_V_DMA_CTRL_REQUEST_SC0TX ((uint32_t)0x26UL) /**< CTRL_REQUEST_SC0TX Value */ 308 #define MXC_S_DMA_CTRL_REQUEST_SC0TX (MXC_V_DMA_CTRL_REQUEST_SC0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SC0TX Setting */ 309 #define MXC_V_DMA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */ 310 #define MXC_S_DMA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */ 311 #define MXC_V_DMA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */ 312 #define MXC_S_DMA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */ 313 #define MXC_V_DMA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */ 314 #define MXC_S_DMA_CTRL_REQUEST_UART2TX (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */ 315 #define MXC_V_DMA_CTRL_REQUEST_SPI3TX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI3TX Value */ 316 #define MXC_S_DMA_CTRL_REQUEST_SPI3TX (MXC_V_DMA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3TX Setting */ 317 #define MXC_V_DMA_CTRL_REQUEST_USBTXEP1 ((uint32_t)0x31UL) /**< CTRL_REQUEST_USBTXEP1 Value */ 318 #define MXC_S_DMA_CTRL_REQUEST_USBTXEP1 (MXC_V_DMA_CTRL_REQUEST_USBTXEP1 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP1 Setting */ 319 #define MXC_V_DMA_CTRL_REQUEST_USBTXEP2 ((uint32_t)0x32UL) /**< CTRL_REQUEST_USBTXEP2 Value */ 320 #define MXC_S_DMA_CTRL_REQUEST_USBTXEP2 (MXC_V_DMA_CTRL_REQUEST_USBTXEP2 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP2 Setting */ 321 #define MXC_V_DMA_CTRL_REQUEST_USBTXEP3 ((uint32_t)0x33UL) /**< CTRL_REQUEST_USBTXEP3 Value */ 322 #define MXC_S_DMA_CTRL_REQUEST_USBTXEP3 (MXC_V_DMA_CTRL_REQUEST_USBTXEP3 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP3 Setting */ 323 #define MXC_V_DMA_CTRL_REQUEST_USBTXEP4 ((uint32_t)0x34UL) /**< CTRL_REQUEST_USBTXEP4 Value */ 324 #define MXC_S_DMA_CTRL_REQUEST_USBTXEP4 (MXC_V_DMA_CTRL_REQUEST_USBTXEP4 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP4 Setting */ 325 #define MXC_V_DMA_CTRL_REQUEST_USBTXEP5 ((uint32_t)0x35UL) /**< CTRL_REQUEST_USBTXEP5 Value */ 326 #define MXC_S_DMA_CTRL_REQUEST_USBTXEP5 (MXC_V_DMA_CTRL_REQUEST_USBTXEP5 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP5 Setting */ 327 #define MXC_V_DMA_CTRL_REQUEST_USBTXEP6 ((uint32_t)0x36UL) /**< CTRL_REQUEST_USBTXEP6 Value */ 328 #define MXC_S_DMA_CTRL_REQUEST_USBTXEP6 (MXC_V_DMA_CTRL_REQUEST_USBTXEP6 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP6 Setting */ 329 #define MXC_V_DMA_CTRL_REQUEST_USBTXEP7 ((uint32_t)0x37UL) /**< CTRL_REQUEST_USBTXEP7 Value */ 330 #define MXC_S_DMA_CTRL_REQUEST_USBTXEP7 (MXC_V_DMA_CTRL_REQUEST_USBTXEP7 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP7 Setting */ 331 #define MXC_V_DMA_CTRL_REQUEST_USBTXEP8 ((uint32_t)0x38UL) /**< CTRL_REQUEST_USBTXEP8 Value */ 332 #define MXC_S_DMA_CTRL_REQUEST_USBTXEP8 (MXC_V_DMA_CTRL_REQUEST_USBTXEP8 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP8 Setting */ 333 #define MXC_V_DMA_CTRL_REQUEST_USBTXEP9 ((uint32_t)0x39UL) /**< CTRL_REQUEST_USBTXEP9 Value */ 334 #define MXC_S_DMA_CTRL_REQUEST_USBTXEP9 (MXC_V_DMA_CTRL_REQUEST_USBTXEP9 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP9 Setting */ 335 #define MXC_V_DMA_CTRL_REQUEST_USBTXEP10 ((uint32_t)0x3AUL) /**< CTRL_REQUEST_USBTXEP10 Value */ 336 #define MXC_S_DMA_CTRL_REQUEST_USBTXEP10 (MXC_V_DMA_CTRL_REQUEST_USBTXEP10 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP10 Setting */ 337 #define MXC_V_DMA_CTRL_REQUEST_USBTXEP11 ((uint32_t)0x3BUL) /**< CTRL_REQUEST_USBTXEP11 Value */ 338 #define MXC_S_DMA_CTRL_REQUEST_USBTXEP11 (MXC_V_DMA_CTRL_REQUEST_USBTXEP11 << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP11 Setting */ 339 #define MXC_V_DMA_CTRL_REQUEST_UART3TX ((uint32_t)0x3CUL) /**< CTRL_REQUEST_UART3TX Value */ 340 #define MXC_S_DMA_CTRL_REQUEST_UART3TX (MXC_V_DMA_CTRL_REQUEST_UART3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3TX Setting */ 341 342 #define MXC_F_DMA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */ 343 #define MXC_F_DMA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */ 344 345 #define MXC_F_DMA_CTRL_TO_PER_POS 11 /**< CTRL_TO_PER Position */ 346 #define MXC_F_DMA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */ 347 #define MXC_V_DMA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */ 348 #define MXC_S_DMA_CTRL_TO_PER_TO4 (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */ 349 #define MXC_V_DMA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */ 350 #define MXC_S_DMA_CTRL_TO_PER_TO8 (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */ 351 #define MXC_V_DMA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */ 352 #define MXC_S_DMA_CTRL_TO_PER_TO16 (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */ 353 #define MXC_V_DMA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */ 354 #define MXC_S_DMA_CTRL_TO_PER_TO32 (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */ 355 #define MXC_V_DMA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */ 356 #define MXC_S_DMA_CTRL_TO_PER_TO64 (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */ 357 #define MXC_V_DMA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */ 358 #define MXC_S_DMA_CTRL_TO_PER_TO128 (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */ 359 #define MXC_V_DMA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */ 360 #define MXC_S_DMA_CTRL_TO_PER_TO256 (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */ 361 #define MXC_V_DMA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */ 362 #define MXC_S_DMA_CTRL_TO_PER_TO512 (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */ 363 364 #define MXC_F_DMA_CTRL_TO_CLKDIV_POS 14 /**< CTRL_TO_CLKDIV Position */ 365 #define MXC_F_DMA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */ 366 #define MXC_V_DMA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */ 367 #define MXC_S_DMA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */ 368 #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */ 369 #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */ 370 #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */ 371 #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */ 372 #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */ 373 #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */ 374 375 #define MXC_F_DMA_CTRL_SRCWD_POS 16 /**< CTRL_SRCWD Position */ 376 #define MXC_F_DMA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */ 377 #define MXC_V_DMA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */ 378 #define MXC_S_DMA_CTRL_SRCWD_BYTE (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */ 379 #define MXC_V_DMA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */ 380 #define MXC_S_DMA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */ 381 #define MXC_V_DMA_CTRL_SRCWD_WORD ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */ 382 #define MXC_S_DMA_CTRL_SRCWD_WORD (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */ 383 384 #define MXC_F_DMA_CTRL_SRCINC_POS 18 /**< CTRL_SRCINC Position */ 385 #define MXC_F_DMA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */ 386 387 #define MXC_F_DMA_CTRL_DSTWD_POS 20 /**< CTRL_DSTWD Position */ 388 #define MXC_F_DMA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */ 389 #define MXC_V_DMA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */ 390 #define MXC_S_DMA_CTRL_DSTWD_BYTE (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */ 391 #define MXC_V_DMA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */ 392 #define MXC_S_DMA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */ 393 #define MXC_V_DMA_CTRL_DSTWD_WORD ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */ 394 #define MXC_S_DMA_CTRL_DSTWD_WORD (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */ 395 396 #define MXC_F_DMA_CTRL_DSTINC_POS 22 /**< CTRL_DSTINC Position */ 397 #define MXC_F_DMA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */ 398 399 #define MXC_F_DMA_CTRL_BURST_SIZE_POS 24 /**< CTRL_BURST_SIZE Position */ 400 #define MXC_F_DMA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */ 401 402 #define MXC_F_DMA_CTRL_DIS_IE_POS 30 /**< CTRL_DIS_IE Position */ 403 #define MXC_F_DMA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */ 404 405 #define MXC_F_DMA_CTRL_CTZ_IE_POS 31 /**< CTRL_CTZ_IE Position */ 406 #define MXC_F_DMA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */ 407 408 /**@} end of group DMA_CTRL_Register */ 409 410 /** 411 * @ingroup dma_registers 412 * @defgroup DMA_STATUS DMA_STATUS 413 * @brief DMA Channel Status Register. 414 * @{ 415 */ 416 #define MXC_F_DMA_STATUS_STATUS_POS 0 /**< STATUS_STATUS Position */ 417 #define MXC_F_DMA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ 418 419 #define MXC_F_DMA_STATUS_IPEND_POS 1 /**< STATUS_IPEND Position */ 420 #define MXC_F_DMA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */ 421 422 #define MXC_F_DMA_STATUS_CTZ_IF_POS 2 /**< STATUS_CTZ_IF Position */ 423 #define MXC_F_DMA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */ 424 425 #define MXC_F_DMA_STATUS_RLD_IF_POS 3 /**< STATUS_RLD_IF Position */ 426 #define MXC_F_DMA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */ 427 428 #define MXC_F_DMA_STATUS_BUS_ERR_POS 4 /**< STATUS_BUS_ERR Position */ 429 #define MXC_F_DMA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */ 430 431 #define MXC_F_DMA_STATUS_TO_IF_POS 6 /**< STATUS_TO_IF Position */ 432 #define MXC_F_DMA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */ 433 434 /**@} end of group DMA_STATUS_Register */ 435 436 /** 437 * @ingroup dma_registers 438 * @defgroup DMA_SRC DMA_SRC 439 * @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 440 * 4, depending on the data width of each AHB cycle. For peripheral transfers, some 441 * or all of the actual address bits are fixed. If SRCINC=0, this register remains 442 * constant. In the case where a count-to-zero condition occurs while RLDEN=1, the 443 * register is reloaded with the contents of DMA_SRC_RLD. 444 * @{ 445 */ 446 #define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ 447 #define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ 448 449 /**@} end of group DMA_SRC_Register */ 450 451 /** 452 * @ingroup dma_registers 453 * @defgroup DMA_DST DMA_DST 454 * @brief Destination Device Address. For peripheral transfers, some or all of the actual 455 * address bits are fixed. If DSTINC=1, this register is incremented on every AHB 456 * write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the 457 * data width of each AHB cycle. In the case where a count-to-zero condition occurs 458 * while RLDEN=1, the register is reloaded with DMA_DST_RLD. 459 * @{ 460 */ 461 #define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */ 462 #define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */ 463 464 /**@} end of group DMA_DST_Register */ 465 466 /** 467 * @ingroup dma_registers 468 * @defgroup DMA_CNT DMA_CNT 469 * @brief DMA Counter. The user loads this register with the number of bytes to transfer. 470 * This counter decreases on every AHB cycle into the DMA FIFO. The decrement will 471 * be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter 472 * reaches 0, a count-to-zero condition is triggered. 473 * @{ 474 */ 475 #define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ 476 #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ 477 478 /**@} end of group DMA_CNT_Register */ 479 480 /** 481 * @ingroup dma_registers 482 * @defgroup DMA_SRCRLD DMA_SRCRLD 483 * @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC 484 * upon a count-to-zero condition. 485 * @{ 486 */ 487 #define MXC_F_DMA_SRCRLD_ADDR_POS 0 /**< SRCRLD_ADDR Position */ 488 #define MXC_F_DMA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */ 489 490 /**@} end of group DMA_SRCRLD_Register */ 491 492 /** 493 * @ingroup dma_registers 494 * @defgroup DMA_DSTRLD DMA_DSTRLD 495 * @brief Destination Address Reload Value. The value of this register is loaded into 496 * DMA0_DST upon a count-to-zero condition. 497 * @{ 498 */ 499 #define MXC_F_DMA_DSTRLD_ADDR_POS 0 /**< DSTRLD_ADDR Position */ 500 #define MXC_F_DMA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */ 501 502 /**@} end of group DMA_DSTRLD_Register */ 503 504 /** 505 * @ingroup dma_registers 506 * @defgroup DMA_CNTRLD DMA_CNTRLD 507 * @brief DMA Channel Count Reload Register. 508 * @{ 509 */ 510 #define MXC_F_DMA_CNTRLD_CNT_POS 0 /**< CNTRLD_CNT Position */ 511 #define MXC_F_DMA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */ 512 513 #define MXC_F_DMA_CNTRLD_EN_POS 31 /**< CNTRLD_EN Position */ 514 #define MXC_F_DMA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */ 515 516 /**@} end of group DMA_CNTRLD_Register */ 517 518 #ifdef __cplusplus 519 } 520 #endif 521 522 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_DMA_REGS_H_ 523
