1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 /**
22 * @file mxc_sys.h
23 * @brief System level header file.
24 */
25
26 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32690_MXC_SYS_H_
27 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32690_MXC_SYS_H_
28
29 #include "mxc_device.h"
30 #include "lpgcr_regs.h"
31 #include "gcr_regs.h"
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 /**
38 * @defgroup mxc_sys System Configuration (MXC_SYS)
39 * @ingroup syscfg
40 * @details API for system configuration including clock source selection and entering critical sections of code.
41 * @{
42 */
43
44 /** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */
45 typedef enum {
46 MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */
47 MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */
48 MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */
49 MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, /**< Reset GPIO1 */
50 MXC_SYS_RESET0_GPIO2 = MXC_F_GCR_RST0_GPIO2_POS, /**< Reset GPIO2 */
51 MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TMR0 */
52 MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, /**< Reset TMR1 */
53 MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, /**< Reset TMR2 */
54 MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, /**< Reset TMR3 */
55 MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */
56 MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */
57 MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */
58 MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */
59 MXC_SYS_RESET0_SPI2 = MXC_F_GCR_RST0_SPI2_POS, /**< Reset SPI2 */
60 MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */
61 MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */
62 MXC_SYS_RESET0_CRYPTO = MXC_F_GCR_RST0_CRYPTO_POS, /**< Reset CRYPTO */
63 MXC_SYS_RESET0_CAN0 = MXC_F_GCR_RST0_CAN0_POS, /**< Reset CAN0 */
64 MXC_SYS_RESET0_CAN1 = MXC_F_GCR_RST0_CAN1_POS, /**< Reset CAN1 */
65 MXC_SYS_RESET0_HPB = MXC_F_GCR_RST0_HPB_POS, /**< Reset HPB */
66 MXC_SYS_RESET0_SMPHR = MXC_F_GCR_RST0_SMPHR_POS, /**< Reset SMPHR */
67 MXC_SYS_RESET0_USB = MXC_F_GCR_RST0_USB_POS, /**< Reset USB */
68 MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */
69 MXC_SYS_RESET0_ADC = MXC_F_GCR_RST0_ADC_POS, /**< Reset ADC */
70 MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */
71 MXC_SYS_RESET0_SOFT = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */
72 MXC_SYS_RESET0_PERIPH = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */
73 MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */
74 /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
75 MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */
76 MXC_SYS_RESET1_PT = (MXC_F_GCR_RST1_PT_POS + 32), /**< Reset PT */
77 MXC_SYS_RESET1_SPIXIP = (MXC_F_GCR_RST1_SPIXIP + 32), /**< Reset SPIXIP */
78 MXC_SYS_RESET1_SPIXIPM = (MXC_F_GCR_RST1_SPIXIPM + 32), /**< Reset SPIXIPM */
79 MXC_SYS_RESET1_OWM = (MXC_F_GCR_RST1_OWM_POS + 32), /**< Reset OWM */
80 MXC_SYS_RESET1_SPI3 = (MXC_F_GCR_RST1_SPI3_POS + 32), /**< Reset SPI3 */
81 MXC_SYS_RESET1_SPI4 = (MXC_F_GCR_RST1_SPI4_POS + 32), /**< Reset SPI4 */
82 MXC_SYS_RESET1_SMPHR = (MXC_F_GCR_RST1_SMPHR_POS + 32), /**< Reset SMPHR */
83 MXC_SYS_RESET1_BTLE = (MXC_F_GCR_RST1_BTLE_POS + 32), /**< Reset BTLE */
84 MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset I2C2 */
85 MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset I2S*/
86 MXC_SYS_RESET1_PUF = (MXC_F_GCR_RST1_PUF_POS + 32), /**< Reset PUF */
87 MXC_SYS_RESET1_CPU1 = (MXC_F_GCR_RST1_CPU1_POS + 32), /**< Reset CPU1 */
88 /* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */
89 MXC_SYS_RESET_GPIO3 = (MXC_F_LPGCR_RST_GPIO3_POS + 64), /**< Reset GPIO3 */
90 MXC_SYS_RESET_WDT1 = (MXC_F_LPGCR_RST_WDT1_POS + 64), /**< Reset WDT1 */
91 MXC_SYS_RESET_TMR4 = (MXC_F_LPGCR_RST_TMR4_POS + 64), /**< Reset TMR4 */
92 MXC_SYS_RESET_TMR5 = (MXC_F_LPGCR_RST_TMR5_POS + 64), /**< Reset TMR5 */
93 MXC_SYS_RESET_UART3 = (MXC_F_LPGCR_RST_UART3_POS + 64), /**< Reset UART3 */
94 MXC_SYS_RESET_LPCOMP = (MXC_F_LPGCR_RST_LPCOMP_POS + 64), /**< Reset LPCOMP */
95 } mxc_sys_reset_t;
96
97 /** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */
98 typedef enum {
99 MXC_SYS_PERIPH_CLOCK_GPIO0 =
100 MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
101 MXC_SYS_PERIPH_CLOCK_GPIO1 =
102 MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */
103 MXC_SYS_PERIPH_CLOCK_GPIO2 =
104 MXC_F_GCR_PCLKDIS0_GPIO2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO2 clock */
105 MXC_SYS_PERIPH_CLOCK_USB =
106 MXC_F_GCR_PCLKDIS0_USB_POS, /**< Disable MXC_F_GCR_PCLKDIS0_USB clock */
107 MXC_SYS_PERIPH_CLOCK_DMA =
108 MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
109 MXC_SYS_PERIPH_CLOCK_SPI0 =
110 MXC_F_GCR_PCLKDIS0_SPI0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */
111 MXC_SYS_PERIPH_CLOCK_SPI1 =
112 MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
113 MXC_SYS_PERIPH_CLOCK_SPI2 =
114 MXC_F_GCR_PCLKDIS0_SPI2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI2 clock */
115 MXC_SYS_PERIPH_CLOCK_UART0 =
116 MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
117 MXC_SYS_PERIPH_CLOCK_UART1 =
118 MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
119 MXC_SYS_PERIPH_CLOCK_I2C0 =
120 MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
121 MXC_SYS_PERIPH_CLOCK_CRYPTO =
122 MXC_F_GCR_PCLKDIS0_CRYPTO_POS, /**< Disable MXC_F_GCR_PCLKDIS0_CRYPTO clock */
123 MXC_SYS_PERIPH_CLOCK_TMR0 =
124 MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR0 clock */
125 MXC_SYS_PERIPH_CLOCK_TMR1 =
126 MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR1 clock */
127 MXC_SYS_PERIPH_CLOCK_TMR2 =
128 MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR2 clock */
129 MXC_SYS_PERIPH_CLOCK_TMR3 =
130 MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */
131 MXC_SYS_PERIPH_CLOCK_ADC =
132 MXC_F_GCR_PCLKDIS0_ADC_POS, /**< Disable MXC_F_GCR_PCLKDIS0_ADC clock */
133 MXC_SYS_PERIPH_CLOCK_I2C1 =
134 MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
135 MXC_SYS_PERIPH_CLOCK_PT = MXC_F_GCR_PCLKDIS0_PT_POS, /**< Disable MXC_F_GCR_PCLKDIS0_PT clock */
136 MXC_SYS_PERIPH_CLOCK_SPIXIP =
137 MXC_F_GCR_PCLKDIS0_SPIXIP_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPIXIP clock */
138 MXC_SYS_PERIPH_CLOCK_SPIXIPC =
139 MXC_F_GCR_PCLKDIS0_SPIXIPC_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPIXIPC clock */
140 /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
141 MXC_SYS_PERIPH_CLOCK_BTLE =
142 (MXC_F_GCR_PCLKDIS1_BTLE_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_BTLE clock */
143 MXC_SYS_PERIPH_CLOCK_UART2 =
144 (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */
145 MXC_SYS_PERIPH_CLOCK_TRNG =
146 (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */
147 MXC_SYS_PERIPH_CLOCK_PUF =
148 (MXC_F_GCR_PCLKDIS1_PUF_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_PUF clock */
149 MXC_SYS_PERIPH_CLOCK_SMPHR =
150 (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SMPHR clock */
151 MXC_SYS_PERIPH_CLOCK_HPB =
152 (MXC_F_GCR_PCLKDIS1_HPB_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_HPB clock */
153 MXC_SYS_PERIPH_CLOCK_SYSCACHE =
154 (MXC_F_GCR_PCLKDIS1_SYSCACHE_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SYSCACHE clock */
155 MXC_SYS_PERIPH_CLOCK_CAN0 =
156 (MXC_F_GCR_PCLKDIS1_CAN0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CAN0 clock */
157 MXC_SYS_PERIPH_CLOCK_OWIRE =
158 (MXC_F_GCR_PCLKDIS1_OWM_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_OWM clock */
159 MXC_SYS_PERIPH_CLOCK_SPI3 =
160 (MXC_F_GCR_PCLKDIS1_SPI3_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SPI3 clock */
161 MXC_SYS_PERIPH_CLOCK_SPI4 =
162 (MXC_F_GCR_PCLKDIS1_SPI4_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SPI4 clock */
163 MXC_SYS_PERIPH_CLOCK_CAN1 =
164 (MXC_F_GCR_PCLKDIS1_CAN1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CAN1 clock */
165 MXC_SYS_PERIPH_CLOCK_I2S =
166 (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
167 MXC_SYS_PERIPH_CLOCK_I2C2 =
168 (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */
169 MXC_SYS_PERIPH_CLOCK_WDT0 =
170 (MXC_F_GCR_PCLKDIS1_WDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */
171 MXC_SYS_PERIPH_CLOCK_CPU1 =
172 (MXC_F_GCR_PCLKDIS1_CPU1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CPU1 clock */
173 /* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */
174 MXC_SYS_PERIPH_CLOCK_GPIO3 =
175 (MXC_F_LPGCR_PCLKDIS_GPIO3_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_GPIO3 clock */
176 MXC_SYS_PERIPH_CLOCK_WDT1 =
177 (MXC_F_LPGCR_PCLKDIS_WDT1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_WDT2 clock */
178 MXC_SYS_PERIPH_CLOCK_TMR4 =
179 (MXC_F_LPGCR_PCLKDIS_TMR4_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */
180 MXC_SYS_PERIPH_CLOCK_TMR5 =
181 (MXC_F_LPGCR_PCLKDIS_TMR5_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */
182 MXC_SYS_PERIPH_CLOCK_UART3 =
183 (MXC_F_LPGCR_PCLKDIS_UART3_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */
184 MXC_SYS_PERIPH_CLOCK_LPCOMP =
185 (MXC_F_LPGCR_PCLKDIS_LPCOMP_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_LPCOMP clock */
186 } mxc_sys_periph_clock_t;
187
188 /** @brief Enumeration to select System Clock source */
189 typedef enum {
190 MXC_SYS_CLOCK_IPO =
191 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO, /**< Select the Internal Primary Oscillator (IPO) */
192 MXC_SYS_CLOCK_ERFO =
193 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO, /**< Select the External RF Crystal Oscillator */
194 MXC_SYS_CLOCK_IBRO =
195 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO, /**< Select the Internal Baud Rate Oscillator (IBRO) */
196 MXC_SYS_CLOCK_ISO =
197 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO, /**< Select the Internal Secondary Oscillator (ISO) */
198 MXC_SYS_CLOCK_INRO =
199 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, /**< Select the Internal Nanoring Oscillator (INRO) */
200 MXC_SYS_CLOCK_ERTCO =
201 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO, /**< Select the External RTC Crystal Oscillator */
202 MXC_SYS_CLOCK_EXTCLK =
203 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK /**< Use the external system clock input */
204 } mxc_sys_system_clock_t;
205
206 typedef enum {
207 MXC_SYS_CLOCK_DIV_1 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1,
208 MXC_SYS_CLOCK_DIV_2 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2,
209 MXC_SYS_CLOCK_DIV_4 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4,
210 MXC_SYS_CLOCK_DIV_8 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8,
211 MXC_SYS_CLOCK_DIV_16 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16,
212 MXC_SYS_CLOCK_DIV_32 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32,
213 MXC_SYS_CLOCK_DIV_64 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64,
214 MXC_SYS_CLOCK_DIV_128 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128
215 } mxc_sys_system_clock_div_t;
216
217 #define MXC_SYS_USN_CHECKSUM_LEN 16 // Length of the USN + padding for checksum compute
218 #define MXC_SYS_USN_CSUM_FIELD_LEN 2 // Size of the checksum field in the USN
219 #define MXC_SYS_USN_LEN 13 // Size of the USN including the checksum
220
221 /***** Function Prototypes *****/
222
223 typedef struct {
224 int ie_status;
225 int in_critical;
226 } mxc_crit_state_t;
227
228 static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 };
229
_mxc_crit_get_state(void)230 static inline void _mxc_crit_get_state(void)
231 {
232 #ifndef __riscv
233 /*
234 On ARM M the 0th bit of the Priority Mask register indicates
235 whether interrupts are enabled or not.
236
237 0 = enabled
238 1 = disabled
239 */
240 uint32_t primask = __get_PRIMASK();
241 _state.ie_status = (primask == 0);
242 #else
243 /*
244 On RISC-V bit position 3 (Machine Interrupt Enable) of the
245 mstatus register indicates whether interrupts are enabled.
246
247 0 = disabled
248 1 = enabled
249 */
250 uint32_t mstatus = get_mstatus();
251 _state.ie_status = ((mstatus & (1 << 3)) != 0);
252 #endif
253 }
254
255 /**
256 * @brief Enter a critical section of code that cannot be interrupted. Call @ref MXC_SYS_Crit_Exit to exit the critical section.
257 * @details Ex:
258 * @code
259 * MXC_SYS_Crit_Enter();
260 * printf("Hello critical section!\n");
261 * MXC_SYS_Crit_Exit();
262 * @endcode
263 * The @ref MXC_CRITICAL macro is also provided as a convencience macro for wrapping a code section in this way.
264 * @returns None
265 */
MXC_SYS_Crit_Enter(void)266 static inline void MXC_SYS_Crit_Enter(void)
267 {
268 _mxc_crit_get_state();
269 if (_state.ie_status)
270 __disable_irq();
271 _state.in_critical = 1;
272 }
273
274 /**
275 * @brief Exit a critical section of code from @ref MXC_SYS_Crit_Enter
276 * @returns None
277 */
MXC_SYS_Crit_Exit(void)278 static inline void MXC_SYS_Crit_Exit(void)
279 {
280 if (_state.ie_status) {
281 __enable_irq();
282 }
283 _state.in_critical = 0;
284 _mxc_crit_get_state();
285 /*
286 ^ Reset the state again to prevent edge case
287 where interrupts get disabled, then Crit_Exit() gets
288 called, which would inadvertently re-enable interrupts
289 from old state.
290 */
291 }
292
293 /**
294 * @brief Polls whether code is currently executing from a critical section.
295 * @returns 1 if code is currently in a critical section (interrupts are disabled).
296 * 0 if code is not in a critical section.
297 */
MXC_SYS_In_Crit_Section(void)298 static inline int MXC_SYS_In_Crit_Section(void)
299 {
300 return _state.in_critical;
301 }
302
303 // clang-format off
304 /**
305 * @brief Macro for wrapping a section of code to make it critical (interrupts disabled). Note: this macro
306 * does not support nesting.
307 * @details
308 * Ex:
309 * \code
310 * MXC_CRITICAL(
311 * printf("Hello critical section!\n");
312 * )
313 * \endcode
314 * This macro places a call to @ref MXC_SYS_Crit_Enter before the code, and a call to @ref MXC_SYS_Crit_Exit after.
315 * @param code The code section to wrap.
316 */
317 #define MXC_CRITICAL(code) {\
318 MXC_SYS_Crit_Enter();\
319 code;\
320 MXC_SYS_Crit_Exit();\
321 }
322 // clang-format on
323
324 /**
325 * @brief Reads the device USN and verifies the checksum.
326 * @param usn Pointer to store the USN. Array must be at least MXC_SYS_USN_LEN bytes long.
327 * @param checksum Optional pointer to store the AES checksum. If not NULL, checksum is verified with AES engine.
328 * @returns E_NO_ERROR if everything is successful.
329 */
330 int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum);
331
332 /**
333 * @brief Determines if the selected peripheral clock is enabled.
334 * @param clock Enumeration for desired clock.
335 * @returns 0 is the clock is disabled, non 0 if the clock is enabled.
336 */
337 int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock);
338
339 /**
340 * @brief Disables the selected peripheral clock.
341 * @param clock Enumeration for desired clock.
342 */
343 void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock);
344
345 /**
346 * @brief Enables the selected peripheral clock.
347 * @param clock Enumeration for desired clock.
348 */
349 void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock);
350
351 /**
352 * @brief Enables the 32kHz oscillator
353 * @param mxc_sys_cfg Not used, may be NULL.
354 */
355 void MXC_SYS_RTCClockEnable(void);
356
357 /**
358 * @brief Disables the 32kHz oscillator
359 * @returns E_NO_ERROR if everything is successful
360 */
361 int MXC_SYS_RTCClockDisable(void);
362
363 /**
364 * @brief Enable System Clock Source without switching to it
365 * @param clock The clock to enable
366 * @return E_NO_ERROR if everything is successful
367 */
368 int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock);
369
370 /**
371 * @brief Disable System Clock Source
372 * @param clock The clock to disable
373 * @return E_NO_ERROR if everything is successful
374 */
375 int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock);
376
377 /**
378 * @brief Select the system clock.
379 * @param clock Enumeration for desired clock. Note: If using the external clock input be sure to define EXTCLK_FREQ correctly.
380 * The default EXTCLK_FREQ value is defined in the system_max78002.h file and can be overridden at compile time.
381 * @returns E_NO_ERROR if everything is successful.
382 */
383 int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock);
384
385 /**
386 * @brief Set the system clock divider.
387 * @param div Enumeration for desired clock divider.
388 */
389 void MXC_SYS_SetClockDiv(mxc_sys_system_clock_div_t div);
390
391 /**
392 * @brief Get the system clock divider.
393 * @returns System clock divider.
394 */
395 mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void);
396
397 /**
398 * @brief Wait for a clock to enable with timeout
399 * @param ready The clock to wait for
400 * @return E_NO_ERROR if ready, E_TIME_OUT if timeout
401 */
402 int MXC_SYS_Clock_Timeout(uint32_t ready);
403 /**
404 * @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register.
405 * @param Enumeration for what to reset. Can reset multiple items at once.
406 */
407 void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset);
408
409 /**
410 * @brief Setup and run RISCV core
411 */
412 void MXC_SYS_RISCVRun(void);
413
414 /**
415 * @brief Shutdown the RISCV core
416 */
417 void MXC_SYS_RISCVShutdown(void);
418
419 /**
420 * @brief Returns the clock rate (in Hz) of the Risc-V core.
421 */
422 uint32_t MXC_SYS_RiscVClockRate(void);
423
424 /**
425 * @brief This function PERMANENTLY locks the Debug Access Port.
426 *
427 * @warning After executing this function you will never be able
428 * to reprogram the target micro.
429 */
430 int MXC_SYS_LockDAP_Permanent(void);
431
432 #ifdef __cplusplus
433 }
434 #endif
435
436 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32690_MXC_SYS_H_
437
