1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 /**
22 * @file mxc_sys.h
23 * @brief System level header file.
24 */
25
26 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32665_MXC_SYS_H_
27 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32665_MXC_SYS_H_
28
29 #include "mxc_device.h"
30 #include "gcr_regs.h"
31
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35
36 /**
37 * @defgroup mxc_sys System Configuration (MXC_SYS)
38 * @ingroup syscfg
39 * @details API for system configuration including clock source selection and entering critical sections of code.
40 * @{
41 */
42
43 /** @brief System reset0 and reset1 enumeration. Used in SYS_PeriphReset0 function */
44 typedef enum {
45 MXC_SYS_RESET_DMA0 = MXC_F_GCR_RSTR0_DMA_POS, /**< Reset DMA */
46 MXC_SYS_RESET_WDT0 = MXC_F_GCR_RSTR0_WDT0_POS, /**< Reset WDT */
47 MXC_SYS_RESET_GPIO0 = MXC_F_GCR_RSTR0_GPIO0_POS, /**< Reset GPIO0 */
48 MXC_SYS_RESET_GPIO1 = MXC_F_GCR_RSTR0_GPIO1_POS, /**< Reset GPIO1 */
49 MXC_SYS_RESET_TIMER0 = MXC_F_GCR_RSTR0_TIMER0_POS, /**< Reset TIMER0 */
50 MXC_SYS_RESET_TIMER1 = MXC_F_GCR_RSTR0_TIMER1_POS, /**< Reset TIMER1 */
51 MXC_SYS_RESET_TIMER2 = MXC_F_GCR_RSTR0_TIMER2_POS, /**< Reset TIMER2 */
52 MXC_SYS_RESET_TIMER3 = MXC_F_GCR_RSTR0_TIMER3_POS, /**< Reset TIMER3 */
53 MXC_SYS_RESET_TIMER4 = MXC_F_GCR_RSTR0_TIMER4_POS, /**< Reset TIMER4 */
54 MXC_SYS_RESET_TIMER5 = MXC_F_GCR_RSTR0_TIMER5_POS, /**< Reset TIMER5 */
55 MXC_SYS_RESET_UART0 = MXC_F_GCR_RSTR0_UART0_POS, /**< Reset UART0 */
56 MXC_SYS_RESET_UART1 = MXC_F_GCR_RSTR0_UART1_POS, /**< Reset UART1 */
57 MXC_SYS_RESET_SPI1 = MXC_F_GCR_RSTR0_SPI1_POS, /**< Reset SPI0 */
58 MXC_SYS_RESET_SPI2 = MXC_F_GCR_RSTR0_SPI2_POS, /**< Reset SPI1 */
59 MXC_SYS_RESET_I2C0 = MXC_F_GCR_RSTR0_I2C0_POS, /**< Reset I2C0 */
60 MXC_SYS_RESET_RTC = MXC_F_GCR_RSTR0_RTC_POS, /**< Reset RTC */
61 MXC_SYS_RESET_CRYPTO = MXC_F_GCR_RSTR0_CRYPTO_POS, /**< Reset CRYPTO */
62 MXC_SYS_RESET_SMPHR = MXC_F_GCR_RSTR0_SMPHR_POS, /**< Reset SMPHR */
63 MXC_SYS_RESET_USB = MXC_F_GCR_RSTR0_USB_POS, /**< Reset USB */
64 // MXC_SYS_RESET_TRNG = MXC_F_GCR_RSTR0_TRNG_POS, /**< Reset TRNG */
65 MXC_SYS_RESET_ADC = MXC_F_GCR_RSTR0_ADC_POS, /**< Reset ADC */
66 MXC_SYS_RESET_DMA1 = MXC_F_GCR_RSTR0_DMA1_POS, /**< Reset DMA1 */
67 MXC_SYS_RESET_UART2 = MXC_F_GCR_RSTR0_UART2_POS, /**< Reset UART2 */
68 MXC_SYS_RESET_SRST = MXC_F_GCR_RSTR0_SRST_POS, /**< Soft reset */
69 MXC_SYS_RESET_PRST = MXC_F_GCR_RSTR0_PRST_POS, /**< Peripheral reset */
70 MXC_SYS_RESET_SYSTEM = MXC_F_GCR_RSTR0_SYSTEM_POS, /**< System reset */
71 /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
72 MXC_SYS_RESET_I2C1 = (MXC_F_GCR_RSTR1_I2C1_POS + 32), /**< Reset I2C1 */
73 MXC_SYS_RESET_PT = (MXC_F_GCR_RSTR1_PT_POS + 32), /**< Reset PT */
74 MXC_SYS_RESET_SPIXIP = (MXC_F_GCR_RSTR1_SPIXIP_POS + 32), /**< Reset SPIXIP */
75 MXC_SYS_RESET_XSPIM = (MXC_F_GCR_RSTR1_XSPIM_POS + 32), /**< Reset XSPIM */
76 MXC_SYS_RESET_SDHC = (MXC_F_GCR_RSTR1_SDHC_POS + 32), /**< Reset SDHC */
77 MXC_SYS_RESET_OWIRE = (MXC_F_GCR_RSTR1_OWIRE_POS + 32), /**< Reset OWIRE */
78 MXC_SYS_RESET_WDT1 = (MXC_F_GCR_RSTR1_WDT1_POS + 32), /**< Reset WDT1 */
79 MXC_SYS_RESET_SPI0 = (MXC_F_GCR_RSTR1_SPI0_POS + 32), /**< Reset SPI2 */
80 MXC_SYS_RESET_SPIXMEM = (MXC_F_GCR_RSTR1_SPIXMEM_POS + 32), /**< Reset SPIXMEM */
81 MXC_SYS_RESET_SEMA = (MXC_F_GCR_RSTR1_SMPHR_POS + 32), /**< Reset SEMA */
82 MXC_SYS_RESET_WDT2 = (MXC_F_GCR_RSTR1_WDT2_POS + 32), /**< Reset WDT1 */
83 MXC_SYS_RESET_BTLE = (MXC_F_GCR_RSTR1_BTLE_POS + 32), /**< Reset BTLE */
84 MXC_SYS_RESET_AUDIO = (MXC_F_GCR_RSTR1_AUDIO_POS + 32), /**< Reset BTLE */
85 MXC_SYS_RESET_RPU = (MXC_F_GCR_RSTR1_RPU_POS + 32), /**< Reset BTLE */
86 MXC_SYS_RESET_I2C2 = (MXC_F_GCR_RSTR1_I2C2_POS + 32), /**< Reset BTLE */
87 MXC_SYS_RESET_HTMR0 = (MXC_F_GCR_RSTR1_HTMR0_POS + 32), /**< Reset HTMR0 */
88 MXC_SYS_RESET_HTMR1 = (MXC_F_GCR_RSTR1_HTMR1_POS + 32), /**< Reset HTMR1 */
89 MXC_SYS_RESET_DVS = (MXC_F_GCR_RSTR1_DVS_POS + 32), /**< Reset DVS */
90 MXC_SYS_RESET_SIMO = (MXC_F_GCR_RSTR1_SIMO_POS + 32), /**< Reset SIMO */
91 } mxc_sys_reset_t;
92
93 /** @brief System clock disable enumeration. Used in SYS_ClockDisable and SYS_ClockEnable functions */
94 typedef enum {
95 MXC_SYS_PERIPH_CLOCK_GPIO0 =
96 MXC_F_GCR_PERCKCN0_GPIO0D_POS, /**< Disable MXC_F_GCR_PERCKCN0_GPIO0D clock */
97 MXC_SYS_PERIPH_CLOCK_GPIO1 =
98 MXC_F_GCR_PERCKCN0_GPIO1D_POS, /**< Disable MXC_F_GCR_PERCKCN0_GPIO1D clock */
99 MXC_SYS_PERIPH_CLOCK_USB =
100 MXC_F_GCR_PERCKCN0_USBD_POS, /**< Disable MXC_F_GCR_PERCKCN0_USBD clock */
101 MXC_SYS_PERIPH_CLOCK_DMA =
102 MXC_F_GCR_PERCKCN0_DMAD_POS, /**< Disable MXC_F_GCR_PERCKCN0_DMAD clock */
103 MXC_SYS_PERIPH_CLOCK_SPI1 =
104 MXC_F_GCR_PERCKCN0_SPI1D_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPI1D clock */
105 MXC_SYS_PERIPH_CLOCK_SPI2 =
106 MXC_F_GCR_PERCKCN0_SPI2D_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPI2D clock */
107 MXC_SYS_PERIPH_CLOCK_UART0 =
108 MXC_F_GCR_PERCKCN0_UART0D_POS, /**< Disable MXC_F_GCR_PERCKCN0_UART0D clock */
109 MXC_SYS_PERIPH_CLOCK_UART1 =
110 MXC_F_GCR_PERCKCN0_UART1D_POS, /**< Disable MXC_F_GCR_PERCKCN0_UART1D clock */
111 MXC_SYS_PERIPH_CLOCK_I2C0 =
112 MXC_F_GCR_PERCKCN0_I2C0D_POS, /**< Disable MXC_F_GCR_PERCKCN0_I2C0D clock */
113 MXC_SYS_PERIPH_CLOCK_TPU =
114 MXC_F_GCR_PERCKCN0_CRYPTOD_POS, /**< Disable MXC_F_GCR_PERCKCN0_CRYPTOD clock */
115 MXC_SYS_PERIPH_CLOCK_T0 =
116 MXC_F_GCR_PERCKCN0_TIMER0D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T0D clock */
117 MXC_SYS_PERIPH_CLOCK_T1 =
118 MXC_F_GCR_PERCKCN0_TIMER1D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T1D clock */
119 MXC_SYS_PERIPH_CLOCK_T2 =
120 MXC_F_GCR_PERCKCN0_TIMER2D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T2D clock */
121 MXC_SYS_PERIPH_CLOCK_T3 =
122 MXC_F_GCR_PERCKCN0_TIMER3D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T3D clock */
123 MXC_SYS_PERIPH_CLOCK_T4 =
124 MXC_F_GCR_PERCKCN0_TIMER4D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T4D clock */
125 MXC_SYS_PERIPH_CLOCK_T5 =
126 MXC_F_GCR_PERCKCN0_TIMER5D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T5D clock */
127 MXC_SYS_PERIPH_CLOCK_ADC =
128 MXC_F_GCR_PERCKCN0_ADCD_POS, /**< Disable MXC_F_GCR_PERCKCN0_ADCD clock */
129 MXC_SYS_PERIPH_CLOCK_I2C1 =
130 MXC_F_GCR_PERCKCN0_I2C1D_POS, /**< Disable MXC_F_GCR_PERCKCN0_I2C1D clock */
131 MXC_SYS_PERIPH_CLOCK_PT =
132 MXC_F_GCR_PERCKCN0_PTD_POS, /**< Disable MXC_F_GCR_PERCKCN0_PTD clock */
133 MXC_SYS_PERIPH_CLOCK_SPIXIP =
134 MXC_F_GCR_PERCKCN0_SPIXIPD_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPIXIPD clock */
135 MXC_SYS_PERIPH_CLOCK_SPIXFC =
136 MXC_F_GCR_PERCKCN0_SPIMD_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPIMD clock */
137 /* PERCKCN1 Below this line we add 32 to separate PERCKCN0 and PERCKCN1 */
138 MXC_SYS_PERIPH_CLOCK_BTLE = (MXC_F_GCR_PERCKCN1_BTLED_POS + 32),
139 MXC_SYS_PERIPH_CLOCK_UART2 =
140 (MXC_F_GCR_PERCKCN1_UART2D_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_UART2D clock */
141 MXC_SYS_PERIPH_CLOCK_TRNG =
142 (MXC_F_GCR_PERCKCN1_TRNGD_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_TRNGD clock */
143 MXC_SYS_PERIPH_CLOCK_SCACHE =
144 (MXC_F_GCR_PERCKCN1_SCACHED_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_SCACHED clock */
145 MXC_SYS_PERIPH_CLOCK_SDMA =
146 (MXC_F_GCR_PERCKCN1_SDMAD_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_SDMAD clock */
147 MXC_SYS_PERIPH_CLOCK_SMPHR =
148 (MXC_F_GCR_PERCKCN1_SMPHRD_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_SMPHRD clock */
149 MXC_SYS_PERIPH_CLOCK_SDHC =
150 (MXC_F_GCR_PERCKCN1_SDHCD_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_SDHCD clock */
151 MXC_SYS_PERIPH_CLOCK_ICACHEXIP =
152 (MXC_F_GCR_PERCKCN1_ICACHEXIPD_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_ICACHEXIPD clock */
153 MXC_SYS_PERIPH_CLOCK_OWIRE =
154 (MXC_F_GCR_PERCKCN1_OWIRED_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_OWIRED clock */
155 MXC_SYS_PERIPH_CLOCK_SPI0 =
156 (MXC_F_GCR_PERCKCN1_SPI0D_POS + 32), /**<Disable QSPI Clock (API Calls QSPI SPI0) */
157 MXC_SYS_PERIPH_CLOCK_SPIXIPD =
158 (MXC_F_GCR_PERCKCN1_SPIXIPDD_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_SPIXIPDD clock */
159 MXC_SYS_PERIPH_CLOCK_DMA1 =
160 (MXC_F_GCR_PERCKCN1_DMA1D_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_DMA1D clock */
161 MXC_SYS_PERIPH_CLOCK_AUDIO =
162 (MXC_F_GCR_PERCKCN1_AUDIOD_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_AUDIOD clock */
163 MXC_SYS_PERIPH_CLOCK_I2C2 =
164 (MXC_F_GCR_PERCKCN1_I2C2D_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_I2C2D clock */
165 MXC_SYS_PERIPH_CLOCK_HTMR0 =
166 (MXC_F_GCR_PERCKCN1_HTMR0D_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_HTMR0D clock */
167 MXC_SYS_PERIPH_CLOCK_HTMR1 =
168 (MXC_F_GCR_PERCKCN1_HTMR1D_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_HTMR1D clock */
169 MXC_SYS_PERIPH_CLOCK_WDT0 =
170 (MXC_F_GCR_PERCKCN1_WDT0D_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_WTD0D clock */
171 MXC_SYS_PERIPH_CLOCK_WDT1 =
172 (MXC_F_GCR_PERCKCN1_WDT1D_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_WTD1D clock */
173 MXC_SYS_PERIPH_CLOCK_WDT2 =
174 (MXC_F_GCR_PERCKCN1_WDT2D_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_WTD2D clock */
175 MXC_SYS_PERIPH_CLOCK_CPU1 =
176 (MXC_F_GCR_PERCKCN1_CPU1D_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_CPU1D clock */
177 } mxc_sys_periph_clock_t;
178
179 typedef enum {
180 MXC_SYS_SYSTEM_DIV_1 = MXC_S_GCR_CLKCN_PSC_DIV1,
181 MXC_SYS_SYSTEM_DIV_2 = MXC_S_GCR_CLKCN_PSC_DIV2,
182 MXC_SYS_SYSTEM_DIV_4 = MXC_S_GCR_CLKCN_PSC_DIV4,
183 MXC_SYS_SYSTEM_DIV_8 = MXC_S_GCR_CLKCN_PSC_DIV8,
184 MXC_SYS_SYSTEM_DIV_16 = MXC_S_GCR_CLKCN_PSC_DIV16,
185 MXC_SYS_SYSTEM_DIV_32 = MXC_S_GCR_CLKCN_PSC_DIV32,
186 MXC_SYS_SYSTEM_DIV_64 = MXC_S_GCR_CLKCN_PSC_DIV64,
187 MXC_SYS_SYSTEM_DIV_128 = MXC_S_GCR_CLKCN_PSC_DIV128,
188 } mxc_sys_system_div_t;
189
190 typedef enum {
191 MXC_SYS_CLOCK_HIRC96 = MXC_V_GCR_CLKCN_CLKSEL_HIRC96,
192 MXC_SYS_CLOCK_HIRC8 = MXC_V_GCR_CLKCN_CLKSEL_HIRC8,
193 MXC_SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC,
194 MXC_SYS_CLOCK_XTAL32M = MXC_V_GCR_CLKCN_CLKSEL_XTAL32M,
195 MXC_SYS_CLOCK_LIRC8K = MXC_V_GCR_CLKCN_CLKSEL_LIRC8,
196 MXC_SYS_CLOCK_XTAL32K = MXC_V_GCR_CLKCN_CLKSEL_XTAL32K,
197 } mxc_sys_system_clock_t;
198
199 #define MXC_SYS_SCACHE_CLK 1 // Enable SCACHE CLK
200 #define MXC_SYS_CTB_CLK 1 // Enable CTB CLK
201
202 #define MXC_SYS_USN_CHECKSUM_LEN 16 // Length of the USN + padding for checksum compute
203 #define MXC_SYS_USN_CSUM_FIELD_LEN 2 // Size of the checksum field in the USN
204 #define MXC_SYS_USN_LEN 13 // Size of the USN including the checksum
205
206 /***** Function Prototypes *****/
207
208 typedef struct {
209 int ie_status;
210 int in_critical;
211 } mxc_crit_state_t;
212
213 static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 };
214
_mxc_crit_get_state(void)215 static inline void _mxc_crit_get_state(void)
216 {
217 #ifndef __riscv
218 /*
219 On ARM M the 0th bit of the Priority Mask register indicates
220 whether interrupts are enabled or not.
221
222 0 = enabled
223 1 = disabled
224 */
225 uint32_t primask = __get_PRIMASK();
226 _state.ie_status = (primask == 0);
227 #else
228 /*
229 On RISC-V bit position 3 (Machine Interrupt Enable) of the
230 mstatus register indicates whether interrupts are enabled.
231
232 0 = disabled
233 1 = enabled
234 */
235 uint32_t mstatus = get_mstatus();
236 _state.ie_status = ((mstatus & (1 << 3)) != 0);
237 #endif
238 }
239
240 /**
241 * @brief Enter a critical section of code that cannot be interrupted. Call @ref MXC_SYS_Crit_Exit to exit the critical section.
242 * @details Ex:
243 * @code
244 * MXC_SYS_Crit_Enter();
245 * printf("Hello critical section!\n");
246 * MXC_SYS_Crit_Exit();
247 * @endcode
248 * The @ref MXC_CRITICAL macro is also provided as a convencience macro for wrapping a code section in this way.
249 * @returns None
250 */
MXC_SYS_Crit_Enter(void)251 static inline void MXC_SYS_Crit_Enter(void)
252 {
253 _mxc_crit_get_state();
254 if (_state.ie_status)
255 __disable_irq();
256 _state.in_critical = 1;
257 }
258
259 /**
260 * @brief Exit a critical section of code from @ref MXC_SYS_Crit_Enter
261 * @returns None
262 */
MXC_SYS_Crit_Exit(void)263 static inline void MXC_SYS_Crit_Exit(void)
264 {
265 if (_state.ie_status) {
266 __enable_irq();
267 }
268 _state.in_critical = 0;
269 _mxc_crit_get_state();
270 /*
271 ^ Reset the state again to prevent edge case
272 where interrupts get disabled, then Crit_Exit() gets
273 called, which would inadvertently re-enable interrupts
274 from old state.
275 */
276 }
277
278 /**
279 * @brief Polls whether code is currently executing from a critical section.
280 * @returns 1 if code is currently in a critical section (interrupts are disabled).
281 * 0 if code is not in a critical section.
282 */
MXC_SYS_In_Crit_Section(void)283 static inline int MXC_SYS_In_Crit_Section(void)
284 {
285 return _state.in_critical;
286 }
287
288 // clang-format off
289 /**
290 * @brief Macro for wrapping a section of code to make it critical (interrupts disabled). Note: this macro
291 * does not support nesting.
292 * @details
293 * Ex:
294 * \code
295 * MXC_CRITICAL(
296 * printf("Hello critical section!\n");
297 * )
298 * \endcode
299 * This macro places a call to @ref MXC_SYS_Crit_Enter before the code, and a call to @ref MXC_SYS_Crit_Exit after.
300 * @param code The code section to wrap.
301 */
302 #define MXC_CRITICAL(code) {\
303 MXC_SYS_Crit_Enter();\
304 code;\
305 MXC_SYS_Crit_Exit();\
306 }
307 // clang-format on
308
309 /**
310 * @brief Reads the device USN and verifies the checksum.
311 * @param usn Pointer to store the USN. Array must be at least MXC_SYS_USN_LEN bytes long.
312 * @param checksum Optional pointer to store the AES checksum. If not NULL, checksum is verified with AES engine.
313 * @returns E_NO_ERROR if everything is successful.
314 */
315 int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum);
316
317 /**
318 * @brief Determines if the selected peripheral clock is enabled.
319 * @param clock Enumeration for desired clock.
320 * @returns 0 is the clock is disabled, non 0 if the clock is enabled.
321 */
322 int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock);
323
324 /**
325 * @brief Disables the selected peripheral clock.
326 * @param clock Enumeration for desired clock.
327 */
328 void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock);
329
330 /**
331 * @brief Enables the selected peripheral clock.
332 * @param clock Enumeration for desired clock.
333 */
334 void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock);
335
336 /**
337 * @brief Enables the 32kHz oscillator
338 * @param mxc_sys_cfg Not used, may be NULL.
339 */
340 void MXC_SYS_RTCClockEnable(void);
341
342 /**
343 * @brief Disables the 32kHz oscillator
344 * @returns E_NO_ERROR if everything is successful
345 */
346 int MXC_SYS_RTCClockDisable(void);
347
348 /**
349 * @brief Enable System Clock Source without switching to it
350 * @param clock The clock to enable
351 * @return E_NO_ERROR if everything is successful
352 */
353 int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock);
354
355 /**
356 * @brief Disable System Clock Source
357 * @param clock The clock to disable
358 * @return E_NO_ERROR if everything is successful
359 */
360 int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock);
361
362 /**
363 * @brief Select the system clock.
364 * @param clock Enumeration for desired clock.
365 * @param tmr Optional tmr pointer for timeout. NULL if undesired.
366 * @returns E_NO_ERROR if everything is successful.
367 */
368 int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock);
369
370 /**
371 * @brief Select the system clock divider.
372 * @param clock Enumeration for desired system clock divider.
373 */
374 void MXC_SYS_Clock_Div(mxc_sys_system_div_t div);
375
376 /**
377 * @brief Wait for a clock to enable with timeout
378 * @param ready The clock to wait for
379 * @return E_NO_ERROR if ready, E_TIME_OUT if timeout
380 */
381 int MXC_SYS_Clock_Timeout(uint32_t ready);
382
383 /**
384 * @brief Reset the peripherals and/or CPU in the RST0 or RST1 register.
385 * @param Enumeration for what to reset. Can reset multiple items at once.
386 */
387 void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset);
388
389 /**
390 * @brief Get the revision of the chip
391 * @returns the chip revision
392 */
393 uint8_t MXC_SYS_GetRev(void);
394
395 /**
396 * @brief This function PERMANENTLY locks the Debug Access Port.
397 *
398 * @warning After executing this function you will never be able
399 * to reprogram the target micro.
400 */
401 int MXC_SYS_LockDAP_Permanent(void);
402
403 #ifdef __cplusplus
404 }
405 #endif
406
407 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32665_MXC_SYS_H_
408
