1 /**
2 * @file mxc_sys.h
3 * @brief System level header file.
4 */
5
6 /******************************************************************************
7 *
8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
9 * Analog Devices, Inc.),
10 * Copyright (C) 2023-2024 Analog Devices, Inc.
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *
24 ******************************************************************************/
25
26 /* Define to prevent redundant inclusion */
27 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32650_MXC_SYS_H_
28 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32650_MXC_SYS_H_
29
30 /* **** Includes **** */
31 #include "mxc_device.h"
32 #include "uart_regs.h"
33 #include "i2c_regs.h"
34 #include "pt_regs.h"
35 #include "ptg_regs.h"
36 #include "gcr_regs.h"
37 #include "tmr_regs.h"
38 #include "gpio.h"
39 #include "spimss_regs.h"
40 #include "sdhc_regs.h"
41 #include "spixfc_regs.h"
42 #include "spi_regs.h"
43 #include "wdt_regs.h"
44 #include "dma.h"
45
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49
50 /**
51 * @defgroup mxc_sys System Configuration (MXC_SYS)
52 * @ingroup syscfg
53 * @details API for system configuration including clock source selection and entering critical sections of code.
54 * @{
55 */
56
57 #if defined(__CC_ARM) /* Suppressing the warning: "enum value is out of range of int" for Keil */
58 #pragma push
59 #pragma diag_suppress 66
60 #endif /* __CC_ARM */
61 /** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */
62 typedef enum {
63 MXC_SYS_RESET_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */
64 MXC_SYS_RESET_WDT = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */
65 MXC_SYS_RESET_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */
66 MXC_SYS_RESET_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, /**< Reset GPIO1 */
67 MXC_SYS_RESET_GPIO2 = MXC_F_GCR_RST0_GPIO2_POS, /**< Reset GPIO2 */
68 MXC_SYS_RESET_TIMER0 = MXC_F_GCR_RST0_TIMER0_POS, /**< Reset TIMER0 */
69 MXC_SYS_RESET_TIMER1 = MXC_F_GCR_RST0_TIMER1_POS, /**< Reset TIMER1 */
70 MXC_SYS_RESET_TIMER2 = MXC_F_GCR_RST0_TIMER2_POS, /**< Reset TIMER2 */
71 MXC_SYS_RESET_TIMER3 = MXC_F_GCR_RST0_TIMER3_POS, /**< Reset TIMER3 */
72 MXC_SYS_RESET_TIMER4 = MXC_F_GCR_RST0_TIMER4_POS, /**< Reset TIMER4 */
73 MXC_SYS_RESET_TIMER5 = MXC_F_GCR_RST0_TIMER5_POS, /**< Reset TIMER5 */
74 MXC_SYS_RESET_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */
75 MXC_SYS_RESET_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */
76 MXC_SYS_RESET_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */
77 MXC_SYS_RESET_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */
78 MXC_SYS_RESET_SPI2 = MXC_F_GCR_RST0_SPI2_POS, /**< Reset SPI2 */
79 MXC_SYS_RESET_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */
80 MXC_SYS_RESET_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */
81 MXC_SYS_RESET_TPU = MXC_F_GCR_RST0_TPU_POS, /**< Reset TPU */
82 MXC_SYS_RESET_HBC = MXC_F_GCR_RST0_HBC_POS, /**< Reset HBC */
83 MXC_SYS_RESET_USB = MXC_F_GCR_RST0_USB_POS, /**< Reset USB */
84 MXC_SYS_RESET_TFT = MXC_F_GCR_RST0_TFT_POS, /**< Reset TRNG */
85 MXC_SYS_RESET_ADC = MXC_F_GCR_RST0_ADC_POS, /**< Reset ADC */
86 MXC_SYS_RESET_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */
87 MXC_SYS_RESET_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */
88 MXC_SYS_RESET_PRST = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */
89 MXC_SYS_RESET_SYSTEM = MXC_F_GCR_RST0_SYS_POS, /**< System reset */
90 /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
91 MXC_SYS_RESET_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */
92 MXC_SYS_RESET_PT = (MXC_F_GCR_RST1_PT_POS + 32), /**< Reset PT */
93 MXC_SYS_RESET_SPIXIP = (MXC_F_GCR_RST1_SPIXIP_POS + 32), /**< Reset SPIXIP */
94 MXC_SYS_RESET_XSPIM = (MXC_F_GCR_RST1_XSPIM_POS + 32), /**< Reset XSPIM */
95 MXC_SYS_RESET_GPIO3 = (MXC_F_GCR_RST1_GPIO3_POS + 32), /**< Reset GPIO3 */
96 MXC_SYS_RESET_SDHC = (MXC_F_GCR_RST1_SDHC_POS + 32), /**< Reset SDHC */
97 MXC_SYS_RESET_OWIRE = (MXC_F_GCR_RST1_OWIRE_POS + 32), /**< Reset OWIRE */
98 MXC_SYS_RESET_WDT1 = (MXC_F_GCR_RST1_WDT1_POS + 32), /**< Reset WDT1 */
99 MXC_SYS_RESET_SPI3 = (MXC_F_GCR_RST1_SPI3_POS + 32), /**< Reset SPI3 */
100 MXC_SYS_RESET_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset I2S */
101 MXC_SYS_RESET_XIPR = (MXC_F_GCR_RST1_XIPR_POS + 32), /**< Reset SPIXMEM */
102 MXC_SYS_RESET_SEMA = (MXC_F_GCR_RST1_SEMA_POS + 32), /**< Reset SMPHR */
103 } mxc_sys_reset_t;
104
105 /** @brief System clock disable enumeration. Used in SYS_ClockDisable and SYS_ClockEnable functions */
106 typedef enum {
107 MXC_SYS_PERIPH_CLOCK_GPIO0 =
108 MXC_F_GCR_PCLK_DIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PERCKCN0_GPIO0D clock */
109 MXC_SYS_PERIPH_CLOCK_GPIO1 =
110 MXC_F_GCR_PCLK_DIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PERCKCN0_GPIO1D clock */
111 MXC_SYS_PERIPH_CLOCK_GPIO2 =
112 MXC_F_GCR_PCLK_DIS0_GPIO2_POS, /**< Disable MXC_F_GCR_PERCKCN0_GPIO2D clock */
113 MXC_SYS_PERIPH_CLOCK_USB =
114 MXC_F_GCR_PCLK_DIS0_USB_POS, /**< Disable MXC_F_GCR_PERCKCN0_USBD clock */
115 MXC_SYS_PERIPH_CLOCK_TFT =
116 MXC_F_GCR_PCLK_DIS0_TFT_POS, /**< Disable MXC_F_GCR_PERCKCN0_CLCD clock */
117 MXC_SYS_PERIPH_CLOCK_DMA =
118 MXC_F_GCR_PCLK_DIS0_DMA_POS, /**< Disable MXC_F_GCR_PERCKCN0_DMAD clock */
119 MXC_SYS_PERIPH_CLOCK_SPI0 =
120 MXC_F_GCR_PCLK_DIS0_SPI0_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPI0D clock */
121 MXC_SYS_PERIPH_CLOCK_SPI1 =
122 MXC_F_GCR_PCLK_DIS0_SPI1_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPI1D clock */
123 MXC_SYS_PERIPH_CLOCK_SPI2 =
124 MXC_F_GCR_PCLK_DIS0_SPI2_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPI2D clock */
125 MXC_SYS_PERIPH_CLOCK_UART0 =
126 MXC_F_GCR_PCLK_DIS0_UART0_POS, /**< Disable MXC_F_GCR_PERCKCN0_UART0D clock */
127 MXC_SYS_PERIPH_CLOCK_UART1 =
128 MXC_F_GCR_PCLK_DIS0_UART1_POS, /**< Disable MXC_F_GCR_PERCKCN0_UART1D clock */
129 MXC_SYS_PERIPH_CLOCK_I2C0 =
130 MXC_F_GCR_PCLK_DIS0_I2C0_POS, /**< Disable MXC_F_GCR_PERCKCN0_I2C0D clock */
131 MXC_SYS_PERIPH_CLOCK_TPU =
132 MXC_F_GCR_PCLK_DIS0_TPU_POS, /**< Disable MXC_F_GCR_PERCKCN0_TPUD clock */
133 MXC_SYS_PERIPH_CLOCK_TIMER0 =
134 MXC_F_GCR_PCLK_DIS0_TIMER0_POS, /**< Disable MXC_F_GCR_PERCKCN0_T0D clock */
135 MXC_SYS_PERIPH_CLOCK_TIMER1 =
136 MXC_F_GCR_PCLK_DIS0_TIMER1_POS, /**< Disable MXC_F_GCR_PERCKCN0_T1D clock */
137 MXC_SYS_PERIPH_CLOCK_TIMER2 =
138 MXC_F_GCR_PCLK_DIS0_TIMER2_POS, /**< Disable MXC_F_GCR_PERCKCN0_T2D clock */
139 MXC_SYS_PERIPH_CLOCK_TIMER3 =
140 MXC_F_GCR_PCLK_DIS0_TIMER3_POS, /**< Disable MXC_F_GCR_PERCKCN0_T3D clock */
141 MXC_SYS_PERIPH_CLOCK_TIMER4 =
142 MXC_F_GCR_PCLK_DIS0_TIMER4_POS, /**< Disable MXC_F_GCR_PERCKCN0_T4D clock */
143 MXC_SYS_PERIPH_CLOCK_TIMER5 =
144 MXC_F_GCR_PCLK_DIS0_TIMER5_POS, /**< Disable MXC_F_GCR_PERCKCN0_T5D clock */
145 MXC_SYS_PERIPH_CLOCK_ADC =
146 MXC_F_GCR_PCLK_DIS0_ADC_POS, /**< Disable MXC_F_GCR_PERCKCN0_ADCD clock */
147 MXC_SYS_PERIPH_CLOCK_I2C1 =
148 MXC_F_GCR_PCLK_DIS0_I2C1_POS, /**< Disable MXC_F_GCR_PERCKCN0_I2C1D clock */
149 MXC_SYS_PERIPH_CLOCK_PT =
150 MXC_F_GCR_PCLK_DIS0_PT_POS, /**< Disable MXC_F_GCR_PERCKCN0_PTD clock */
151 MXC_SYS_PERIPH_CLOCK_SPIXIPF =
152 MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPIXIPD clock */
153 MXC_SYS_PERIPH_CLOCK_SPIXIPM =
154 MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPIMD clock */
155 /* PERCKCN1 Below this line we add 32 to separate PERCKCN0 and PERCKCN1 */
156 MXC_SYS_PERIPH_CLOCK_UART2 =
157 (MXC_F_GCR_PCLK_DIS1_UART2_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_UART2D clock */
158 MXC_SYS_PERIPH_CLOCK_TRNG =
159 (MXC_F_GCR_PCLK_DIS1_TRNG_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_TRNGD clock */
160 MXC_SYS_PERIPH_CLOCK_FLC =
161 (MXC_F_GCR_PCLK_DIS1_SFLC_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_FLCD clock */
162 MXC_SYS_PERIPH_CLOCK_HBC =
163 (MXC_F_GCR_PCLK_DIS1_HBC_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_HBCD clock */
164 MXC_SYS_PERIPH_CLOCK_GPIO3 =
165 (MXC_F_GCR_PCLK_DIS1_GPIO3_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_GPIO3D clock */
166 MXC_SYS_PERIPH_CLOCK_SCACHE =
167 (MXC_F_GCR_PCLK_DIS1_SCACHE_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_SCACHED clock */
168 MXC_SYS_PERIPH_CLOCK_SDMA =
169 (MXC_F_GCR_PCLK_DIS1_SDMA_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_SDMAD clock */
170 MXC_SYS_PERIPH_CLOCK_SEMA =
171 (MXC_F_GCR_PCLK_DIS1_SEMA_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_SMPHRD clock */
172 MXC_SYS_PERIPH_CLOCK_SDHC =
173 (MXC_F_GCR_PCLK_DIS1_SDHC_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_SDHCD clock */
174 MXC_SYS_PERIPH_CLOCK_ICACHE =
175 (MXC_F_GCR_PCLK_DIS1_ICACHE_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_ICACHED clock */
176 MXC_SYS_PERIPH_CLOCK_ICACHEXIP = (MXC_F_GCR_PCLK_DIS1_ICACHEXIPF_POS +
177 32), /**<Disable MXC_F_GCR_PERCKCN1_ICACHEXIPD clock */
178 MXC_SYS_PERIPH_CLOCK_OWIRE =
179 (MXC_F_GCR_PCLK_DIS1_OW_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_OWIRED clock */
180 MXC_SYS_PERIPH_CLOCK_SPI3 =
181 (MXC_F_GCR_PCLK_DIS1_SPI3_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_SPI3D clock */
182 MXC_SYS_PERIPH_CLOCK_I2S =
183 (MXC_F_GCR_PCLK_DIS1_I2S_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_I2SD clock */
184 MXC_SYS_PERIPH_CLOCK_SPIXIPR =
185 (MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_SPIXIPDD clock */
186 } mxc_sys_periph_clock_t;
187
188 typedef enum {
189 MXC_SYS_CLOCK_CRYPTO = MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_CRYPTO,
190 MXC_SYS_CLOCK_NANORING = MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_NANORING,
191 MXC_SYS_CLOCK_HIRC96 = MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96,
192 MXC_SYS_CLOCK_HIRC8 = MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8,
193 MXC_SYS_CLOCK_HFXIN = MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HFXIN,
194 MXC_SYS_CLOCK_X32K = MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_X32K,
195 } mxc_sys_system_clock_t;
196
197 typedef enum {
198 MXC_SYS_SYSTEM_DIV_1 = MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1,
199 MXC_SYS_SYSTEM_DIV_2 = MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2,
200 MXC_SYS_SYSTEM_DIV_4 = MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4,
201 MXC_SYS_SYSTEM_DIV_8 = MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8,
202 MXC_SYS_SYSTEM_DIV_16 = MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16,
203 MXC_SYS_SYSTEM_DIV_32 = MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32,
204 MXC_SYS_SYSTEM_DIV_64 = MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64,
205 MXC_SYS_SYSTEM_DIV_128 = MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128,
206 } mxc_sys_system_div_t;
207
208 typedef struct {
209 uint8_t scache_flag;
210 uint8_t crypto_flag;
211 } mxc_sys_spid_cfg_t;
212
213 /** @brief Enable control */
214 typedef enum { Disable, Enable } mxc_sys_control_t;
215
216 typedef void *mxc_sys_cfg_t;
217
218 /** @brief System Cache System Configuration Object */
219 typedef mxc_sys_cfg_t mxc_sys_cfg_scache_t;
220
221 /** @brief USB High Speed System Configuration Object */
222 typedef mxc_sys_cfg_t mxc_sys_cfg_usbhs_t;
223
224 #if defined(__CC_ARM) /* Restore the warning: "enum is out of int range" for Keil */
225 #pragma pop
226 #endif /* __CC_ARM */
227
228 #define MXC_SYS_SCACHE_CLK 1 // Enable SCACHE CLK
229 #define MXC_SYS_TPU_CLK 1 // Enable TPU CLK
230 #define MXC_SYS_USN_LEN 13 // Size of the USN
231
232 /***** Function Prototypes *****/
233
234 typedef struct {
235 int ie_status;
236 int in_critical;
237 } mxc_crit_state_t;
238
239 static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 };
240
_mxc_crit_get_state(void)241 static inline void _mxc_crit_get_state(void)
242 {
243 #ifndef __riscv
244 /*
245 On ARM M the 0th bit of the Priority Mask register indicates
246 whether interrupts are enabled or not.
247
248 0 = enabled
249 1 = disabled
250 */
251 uint32_t primask = __get_PRIMASK();
252 _state.ie_status = (primask == 0);
253 #else
254 /*
255 On RISC-V bit position 3 (Machine Interrupt Enable) of the
256 mstatus register indicates whether interrupts are enabled.
257
258 0 = disabled
259 1 = enabled
260 */
261 uint32_t mstatus = get_mstatus();
262 _state.ie_status = ((mstatus & (1 << 3)) != 0);
263 #endif
264 }
265
266 /**
267 * @brief Enter a critical section of code that cannot be interrupted. Call @ref MXC_SYS_Crit_Exit to exit the critical section.
268 * @details Ex:
269 * @code
270 * MXC_SYS_Crit_Enter();
271 * printf("Hello critical section!\n");
272 * MXC_SYS_Crit_Exit();
273 * @endcode
274 * The @ref MXC_CRITICAL macro is also provided as a convencience macro for wrapping a code section in this way.
275 * @returns None
276 */
MXC_SYS_Crit_Enter(void)277 static inline void MXC_SYS_Crit_Enter(void)
278 {
279 _mxc_crit_get_state();
280 if (_state.ie_status)
281 __disable_irq();
282 _state.in_critical = 1;
283 }
284
285 /**
286 * @brief Exit a critical section of code from @ref MXC_SYS_Crit_Enter
287 * @returns None
288 */
MXC_SYS_Crit_Exit(void)289 static inline void MXC_SYS_Crit_Exit(void)
290 {
291 if (_state.ie_status) {
292 __enable_irq();
293 }
294 _state.in_critical = 0;
295 _mxc_crit_get_state();
296 /*
297 ^ Reset the state again to prevent edge case
298 where interrupts get disabled, then Crit_Exit() gets
299 called, which would inadvertently re-enable interrupts
300 from old state.
301 */
302 }
303
304 /**
305 * @brief Polls whether code is currently executing from a critical section.
306 * @returns 1 if code is currently in a critical section (interrupts are disabled).
307 * 0 if code is not in a critical section.
308 */
MXC_SYS_In_Crit_Section(void)309 static inline int MXC_SYS_In_Crit_Section(void)
310 {
311 return _state.in_critical;
312 }
313
314 // clang-format off
315 /**
316 * @brief Macro for wrapping a section of code to make it critical (interrupts disabled). Note: this macro
317 * does not support nesting.
318 * @details
319 * Ex:
320 * \code
321 * MXC_CRITICAL(
322 * printf("Hello critical section!\n");
323 * )
324 * \endcode
325 * This macro places a call to @ref MXC_SYS_Crit_Enter before the code, and a call to @ref MXC_SYS_Crit_Exit after.
326 * @param code The code section to wrap.
327 */
328 #define MXC_CRITICAL(code) {\
329 MXC_SYS_Crit_Enter();\
330 code;\
331 MXC_SYS_Crit_Exit();\
332 }
333 // clang-format on
334
335 /**
336 * @brief Determines if the selected peripheral clock is enabled.
337 * @param clock Enumeration for desired clock.
338 * @returns 0 is the clock is disabled, non 0 if the clock is enabled.
339 */
340 int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock);
341
342 /**
343 * @brief Disables the selected peripheral clock.
344 * @param clock Enumeration for desired clock.
345 * @returns #E_NO_ERROR if everything is successful.
346 */
347 int MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock);
348
349 /**
350 * @brief Enables the selected peripheral clock.
351 * @param clock Enumeration for desired clock.
352 * @returns #E_NO_ERROR if everything is successful.
353 */
354 int MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock);
355
356 /**
357 * @brief Enables the external 32k oscillator.
358 * @param rtc rtc system configuration settings. NULL if undesired.
359 * @returns #E_NO_ERROR if everything is successful.
360 */
361 int MXC_SYS_RTCClockEnable(void);
362
363 /**
364 * @brief Disables the external 32k oscillator.
365 *
366 * @returns #E_NO_ERROR if everything is successful.
367 */
368 int MXC_SYS_RTCClockDisable(void);
369
370 /**
371 * @brief Enable System Clock Source without switching to it
372 * @param clock The clock to enable
373 * @return E_NO_ERROR if everything is successful
374 */
375 int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock);
376
377 /**
378 * @brief Disable System Clock Source
379 * @param clock The clock to disable
380 * @return E_NO_ERROR if everything is successful
381 */
382 int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock);
383
384 /**
385 * @brief Select the system clock.
386 * @param clock Enumeration for desired clock.
387 * @returns #E_NO_ERROR if everything is successful.
388 */
389 int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock);
390
391 /**
392 * @brief Select the system clock divider.
393 * @param clock Enumeration for desired system clock divider.
394 */
395 void MXC_SYS_Clock_Div(mxc_sys_system_div_t div);
396
397 /**
398 * @brief Wait for a clock to enable with timeout
399 * @param ready The clock to wait for
400 * @return E_NO_ERROR if ready, E_TIME_OUT if timeout
401 */
402 int MXC_SYS_Clock_Timeout(uint32_t ready);
403
404 /**
405 * @brief Reset the peripherals and/or CPU in the rstr0 register.
406 * @param reset Enumeration for what to reset. Can reset multiple items at once.
407 * @returns #E_NO_ERROR if everything is successful.
408 */
409 int MXC_SYS_Reset_Periph(mxc_sys_reset_t reset);
410
411 /**
412 * @brief Get the revision of the chip
413 * @returns the chip revision
414 */
415 uint8_t MXC_SYS_GetRev(void);
416
417 /**
418 * @brief Get the USN of the chip
419 * @param serialNumber buffer to store the USN
420 * @param len length of the USN buffer
421 * @returns #E_NO_ERROR if everything is successful.
422 */
423 int MXC_SYS_GetUSN(uint8_t *serialNumber, int len);
424
425 /**
426 * @brief System level initialization for SCHACE module.
427 * @param sys_cfg System configuration object
428 * @returns #E_NO_ERROR if everything is successful.
429 */
430 int MXC_SYS_SCACHE_Init(const mxc_sys_cfg_scache_t *sys_cfg);
431
432 /**
433 * @brief System level Shutdown for SCACHE module.
434 * @returns #E_NO_ERROR if everything is successful.
435 */
436 int MXC_SYS_SCACHE_Shutdown(void);
437
438 /**
439 * @brief System-level initialization for the USBHS module
440 * @param sys_cfg System configuration object
441 * @returns E_NO_ERROR upon success, or appropriate failure code
442 */
443 int MXC_SYS_USBHS_Init(const mxc_sys_cfg_usbhs_t *sys_cfg);
444
445 /**
446 * @brief System-level shutdown for the USBHS module
447 * @returns #E_NO_ERROR upon success, or appropriate failure code
448 */
449 int MXC_SYS_USBHS_Shutdown(void);
450
451 /**
452 * @brief System Tick Configuration Helper
453 *
454 * The function enables selection of the external clock source for
455 * the System Tick Timer. It initializes the System Timer and its
456 * interrupt, and starts the System Tick Timer. Counter is in free
457 * running mode to generate periodic interrupts.
458 *
459 * @param ticks Number of ticks between two interrupts.
460 * @param clk_src Selects between default SystemClock or External Clock.
461 * - 0 Use external clock source
462 * - 1 SystemClock
463 * @param tmr Optional tmr pointer for timeout. NULL if undesired.
464 * @return #E_NO_ERROR Function succeeded.
465 * @return #E_INVALID Invalid reload value requested.
466 *
467 */
468 int MXC_SYS_SysTick_Config(uint32_t ticks, int clk_src, mxc_tmr_regs_t *tmr);
469
470 /**
471 * @brief Disable System Tick timer
472 * @returns #E_NO_ERROR if everything is successful.
473 */
474 int MXC_SYS_SysTick_Disable(void);
475
476 /**
477 * @brief Delay a requested number of SysTick Timer Ticks.
478 * @param ticks Number of System Ticks to delay.
479 * @note This delay function is based on the clock used for the SysTick
480 * timer if the SysTick timer is enabled. If the SysTick timer is
481 * not enabled, the current SysTick registers are saved and the
482 * timer will use the SystemClock as the source for the delay. The
483 * delay is measured in clock ticks and is not based on the SysTick
484 * interval.
485 * @return #E_NO_ERROR if everything is successful
486 */
487 int MXC_SYS_SysTick_Delay(uint32_t ticks);
488
489 /**
490 * @brief Get the frequency of the SysTick Timer
491 * @return frequency in Hz
492 */
493 uint32_t MXC_SYS_SysTick_GetFreq(void);
494
495 /**
496 * @brief Delay a requested number of microseconds.
497 * @param us Number of microseconds to delay.
498 * @note Calls SYS_SysTick_Delay().
499 * @returns #E_NO_ERROR if everything is successful.
500 */
501 int MXC_SYS_SysTick_DelayUs(uint32_t us);
502
503 /**
504 * @brief This function PERMANENTLY locks the Debug Access Port.
505 *
506 * @warning After executing this function you will never be able
507 * to reprogram the target micro.
508 */
509 int MXC_SYS_LockDAP_Permanent(void);
510
511 /**@} end of group mxc_sys */
512
513 #ifdef __cplusplus
514 }
515 #endif
516
517 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32650_MXC_SYS_H_
518
