1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 /**
22 * @file mxc_sys.h
23 * @ingroup mxc_sys
24 * @brief System level header file.
25 */
26
27 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78002_MXC_SYS_H_
28 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78002_MXC_SYS_H_
29
30 #include "mxc_device.h"
31 #include "lpgcr_regs.h"
32 #include "gcr_regs.h"
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 /**
39 * @defgroup mxc_sys System Configuration (MXC_SYS)
40 * @ingroup syscfg
41 * @details API for system configuration including clock source selection and entering critical sections of code.
42 * @{
43 */
44
45 /** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */
46 typedef enum {
47 MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */
48 MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */
49 MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */
50 MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, /**< Reset GPIO1 */
51 MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TMR0 */
52 MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, /**< Reset TMR1 */
53 MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, /**< Reset TMR2 */
54 MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, /**< Reset TMR3 */
55 MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */
56 MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */
57 MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */
58 MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */
59 MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */
60 MXC_SYS_RESET0_SMPHR = MXC_F_GCR_RST0_SMPHR_POS, /**< Reset SMPHR */
61 MXC_SYS_RESET0_USB = MXC_F_GCR_RST0_USB, /**< Reset USB */
62 MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */
63 MXC_SYS_RESET0_CNN = MXC_F_GCR_RST0_CNN_POS, /**< Reset CNN */
64 MXC_SYS_RESET0_ADC = MXC_F_GCR_RST0_ADC_POS, /**< Reset ADC */
65 MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */
66 MXC_SYS_RESET0_SOFT = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */
67 MXC_SYS_RESET0_PERIPH = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */
68 MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */
69 /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
70 MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */
71 MXC_SYS_RESET1_PT = (MXC_F_GCR_RST1_PT_POS + 32), /**< Reset PT */
72 MXC_SYS_RESET1_OWM = (MXC_F_GCR_RST1_OWM_POS + 32), /**< Reset OWM */
73 MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset CRC */
74 MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset AES */
75 MXC_SYS_RESET1_SDHC = (MXC_F_GCR_RST1_SDHC_POS + 32), /**< Reset SDHC */
76 MXC_SYS_RESET1_SMPHR = (MXC_F_GCR_RST1_SMPHR_POS + 32), /**< Reset SMPHR */
77 MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset I2C2 */
78 MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset I2S*/
79 MXC_SYS_RESET1_DVS = (MXC_F_GCR_RST1_DVS_POS + 32), /**< Reset DVS */
80 MXC_SYS_RESET1_SIMO = (MXC_F_GCR_RST1_SIMO_POS + 32), /**< Reset SIMO */
81 MXC_SYS_RESET1_SPI0 = (MXC_F_GCR_RST1_SPI0_POS + 32), /**< Reset SPI0 */
82 MXC_SYS_RESET1_CSI2 = (MXC_F_GCR_RST1_CSI2_POS + 32), /**< Reset CSI2 */
83 MXC_SYS_RESET1_CPU1 = (MXC_F_GCR_RST1_CPU1_POS + 32), /**< Reset CPU1 */
84 /* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */
85 MXC_SYS_RESET_GPIO2 = (MXC_F_LPGCR_RST_GPIO2_POS + 64), /**< Reset GPIO2 */
86 MXC_SYS_RESET_WDT1 = (MXC_F_LPGCR_RST_WDT1_POS + 64), /**< Reset WDT1 */
87 MXC_SYS_RESET_TMR4 = (MXC_F_LPGCR_RST_TMR4_POS + 64), /**< Reset TMR4 */
88 MXC_SYS_RESET_TMR5 = (MXC_F_LPGCR_RST_TMR5_POS + 64), /**< Reset TMR5 */
89 MXC_SYS_RESET_UART3 = (MXC_F_LPGCR_RST_UART3_POS + 64), /**< Reset UART3 */
90 MXC_SYS_RESET_LPCOMP = (MXC_F_LPGCR_RST_LPCOMP_POS + 64), /**< Reset LPCOMP */
91 } mxc_sys_reset_t;
92
93 /** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */
94 typedef enum {
95 MXC_SYS_PERIPH_CLOCK_GPIO0 =
96 MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */
97 MXC_SYS_PERIPH_CLOCK_GPIO1 =
98 MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */
99 MXC_SYS_PERIPH_CLOCK_USB =
100 MXC_F_GCR_PCLKDIS0_USB_POS, /**< Disable MXC_F_GCR_PCLKDIS0_USB clock */
101 MXC_SYS_PERIPH_CLOCK_DMA =
102 MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */
103 MXC_SYS_PERIPH_CLOCK_SPI1 =
104 MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */
105 MXC_SYS_PERIPH_CLOCK_UART0 =
106 MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */
107 MXC_SYS_PERIPH_CLOCK_UART1 =
108 MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */
109 MXC_SYS_PERIPH_CLOCK_I2C0 =
110 MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */
111 MXC_SYS_PERIPH_CLOCK_TMR0 =
112 MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR0 clock */
113 MXC_SYS_PERIPH_CLOCK_TMR1 =
114 MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR1 clock */
115 MXC_SYS_PERIPH_CLOCK_TMR2 =
116 MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR2 clock */
117 MXC_SYS_PERIPH_CLOCK_TMR3 =
118 MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */
119 MXC_SYS_PERIPH_CLOCK_ADC =
120 MXC_F_GCR_PCLKDIS0_ADC_POS, /**< Disable MXC_F_GCR_PCLKDIS0_ADC clock */
121 MXC_SYS_PERIPH_CLOCK_CNN =
122 MXC_F_GCR_PCLKDIS0_CNN_POS, /**< Disable MXC_F_GCR_PCLKDIS0_CNN clock */
123 MXC_SYS_PERIPH_CLOCK_I2C1 =
124 MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */
125 MXC_SYS_PERIPH_CLOCK_PT = MXC_F_GCR_PCLKDIS0_PT_POS, /**< Disable MXC_F_GCR_PCLKDIS0_PT clock */
126 /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
127 MXC_SYS_PERIPH_CLOCK_UART2 =
128 (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */
129 MXC_SYS_PERIPH_CLOCK_TRNG =
130 (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */
131 MXC_SYS_PERIPH_CLOCK_SDHC =
132 (MXC_F_GCR_PCLKDIS1_SDHC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SDHC clock */
133 MXC_SYS_PERIPH_CLOCK_SMPHR =
134 (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SMPHR clock */
135 MXC_SYS_PERIPH_CLOCK_OWIRE =
136 (MXC_F_GCR_PCLKDIS1_OWM_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_OWM clock */
137 MXC_SYS_PERIPH_CLOCK_CRC =
138 (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */
139 MXC_SYS_PERIPH_CLOCK_AES =
140 (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */
141 MXC_SYS_PERIPH_CLOCK_I2S =
142 (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */
143 MXC_SYS_PERIPH_CLOCK_SPI0 =
144 (MXC_F_GCR_PCLKDIS1_SPI0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SPI0 clock */
145 MXC_SYS_PERIPH_CLOCK_PCIF =
146 (MXC_F_GCR_PCLKDIS1_PCIF_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_PCIF clock */
147 MXC_SYS_PERIPH_CLOCK_I2C2 =
148 (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */
149 MXC_SYS_PERIPH_CLOCK_WDT0 =
150 (MXC_F_GCR_PCLKDIS1_WDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */
151 MXC_SYS_PERIPH_CLOCK_CSI2 =
152 (MXC_F_GCR_PCLKDIS1_CSI2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CSI2 clock */
153 MXC_SYS_PERIPH_CLOCK_CPU1 =
154 (MXC_F_GCR_PCLKDIS1_CPU1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CPU1 clock */
155 /* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */
156 MXC_SYS_PERIPH_CLOCK_GPIO2 =
157 (MXC_F_LPGCR_PCLKDIS_GPIO2_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_GPIO2 clock */
158 MXC_SYS_PERIPH_CLOCK_WDT1 =
159 (MXC_F_LPGCR_PCLKDIS_WDT1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_WDT2 clock */
160 MXC_SYS_PERIPH_CLOCK_TMR4 =
161 (MXC_F_LPGCR_PCLKDIS_TMR4_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */
162 MXC_SYS_PERIPH_CLOCK_TMR5 =
163 (MXC_F_LPGCR_PCLKDIS_TMR5_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */
164 MXC_SYS_PERIPH_CLOCK_UART3 =
165 (MXC_F_LPGCR_PCLKDIS_UART3_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */
166 MXC_SYS_PERIPH_CLOCK_LPCOMP =
167 (MXC_F_LPGCR_PCLKDIS_LPCOMP_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_LPCOMP clock */
168 } mxc_sys_periph_clock_t;
169
170 /** @brief Enumeration to select System Clock source */
171 typedef enum {
172 MXC_SYS_CLOCK_IPO =
173 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO, /**< Select the Internal Primary Oscillator (IPO) */
174 MXC_SYS_CLOCK_IBRO =
175 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO, /**< Select the Internal Baud Rate Oscillator (IBRO) */
176 MXC_SYS_CLOCK_ISO =
177 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO, /**< Select the Internal Secondary Oscillator (ISO) */
178 MXC_SYS_CLOCK_IPLL =
179 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPLL, /**< Select the Internal Phase Lock Loop Oscillator (IPLL) */
180 MXC_SYS_CLOCK_EBO =
181 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EBO, /**< Select the IExternal Base Oscillator (EBO) */
182 MXC_SYS_CLOCK_INRO =
183 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, /**< Select the Internal Nanoring Oscillator (INRO) */
184 MXC_SYS_CLOCK_ERTCO =
185 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO, /**< Select the External RTC Crystal Oscillator */
186 MXC_SYS_CLOCK_EXTCLK =
187 MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK /**< Use the external system clock input. */
188 } mxc_sys_system_clock_t;
189
190 typedef enum {
191 MXC_SYS_CLOCK_DIV_1 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1,
192 MXC_SYS_CLOCK_DIV_2 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2,
193 MXC_SYS_CLOCK_DIV_4 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4,
194 MXC_SYS_CLOCK_DIV_8 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8,
195 MXC_SYS_CLOCK_DIV_16 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16,
196 MXC_SYS_CLOCK_DIV_32 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32,
197 MXC_SYS_CLOCK_DIV_64 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64,
198 MXC_SYS_CLOCK_DIV_128 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128
199 } mxc_sys_system_clock_div_t;
200
201 #define MXC_SYS_USN_CHECKSUM_LEN 16 // Length of the USN + padding for checksum compute
202 #define MXC_SYS_USN_CSUM_FIELD_LEN 2 // Size of the checksum field in the USN
203 #define MXC_SYS_USN_LEN 13 // Size of the USN including the checksum
204
205 /***** Function Prototypes *****/
206
207 typedef struct {
208 int ie_status;
209 int in_critical;
210 } mxc_crit_state_t;
211
212 static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 };
213
_mxc_crit_get_state(void)214 static inline void _mxc_crit_get_state(void)
215 {
216 #ifndef __riscv
217 /*
218 On ARM M the 0th bit of the Priority Mask register indicates
219 whether interrupts are enabled or not.
220
221 0 = enabled
222 1 = disabled
223 */
224 uint32_t primask = __get_PRIMASK();
225 _state.ie_status = (primask == 0);
226 #else
227 /*
228 On RISC-V bit position 3 (Machine Interrupt Enable) of the
229 mstatus register indicates whether interrupts are enabled.
230
231 0 = disabled
232 1 = enabled
233 */
234 uint32_t mstatus = get_mstatus();
235 _state.ie_status = ((mstatus & (1 << 3)) != 0);
236 #endif
237 }
238
239 /**
240 * @brief Enter a critical section of code that cannot be interrupted. Call @ref MXC_SYS_Crit_Exit to exit the critical section.
241 * @details Ex:
242 * @code
243 * MXC_SYS_Crit_Enter();
244 * printf("Hello critical section!\n");
245 * MXC_SYS_Crit_Exit();
246 * @endcode
247 * The @ref MXC_CRITICAL macro is also provided as a convencience macro for wrapping a code section in this way.
248 * @returns None
249 */
MXC_SYS_Crit_Enter(void)250 static inline void MXC_SYS_Crit_Enter(void)
251 {
252 _mxc_crit_get_state();
253 if (_state.ie_status)
254 __disable_irq();
255 _state.in_critical = 1;
256 }
257
258 /**
259 * @brief Exit a critical section of code from @ref MXC_SYS_Crit_Enter
260 * @returns None
261 */
MXC_SYS_Crit_Exit(void)262 static inline void MXC_SYS_Crit_Exit(void)
263 {
264 if (_state.ie_status) {
265 __enable_irq();
266 }
267 _state.in_critical = 0;
268 _mxc_crit_get_state();
269 /*
270 ^ Reset the state again to prevent edge case
271 where interrupts get disabled, then Crit_Exit() gets
272 called, which would inadvertently re-enable interrupts
273 from old state.
274 */
275 }
276
277 /**
278 * @brief Polls whether code is currently executing from a critical section.
279 * @returns 1 if code is currently in a critical section (interrupts are disabled).
280 * 0 if code is not in a critical section.
281 */
MXC_SYS_In_Crit_Section(void)282 static inline int MXC_SYS_In_Crit_Section(void)
283 {
284 return _state.in_critical;
285 }
286
287 // clang-format off
288 /**
289 * @brief Macro for wrapping a section of code to make it critical (interrupts disabled). Note: this macro
290 * does not support nesting.
291 * @details
292 * Ex:
293 * \code
294 * MXC_CRITICAL(
295 * printf("Hello critical section!\n");
296 * )
297 * \endcode
298 * This macro places a call to @ref MXC_SYS_Crit_Enter before the code, and a call to @ref MXC_SYS_Crit_Exit after.
299 * @param code The code section to wrap.
300 */
301 #define MXC_CRITICAL(code) {\
302 MXC_SYS_Crit_Enter();\
303 code;\
304 MXC_SYS_Crit_Exit();\
305 }
306 // clang-format on
307
308 /**
309 * @brief Reads the device USN and verifies the checksum.
310 * @param usn Pointer to store the USN. Array must be at least MXC_SYS_USN_LEN bytes long.
311 * @param checksum Optional pointer to store the AES checksum. If not NULL, checksum is verified with AES engine.
312 * @returns E_NO_ERROR if everything is successful.
313 */
314 int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum);
315
316 /**
317 * @brief Determines if the selected peripheral clock is enabled.
318 * @param clock Enumeration for desired clock.
319 * @returns 0 is the clock is disabled, non 0 if the clock is enabled.
320 */
321 int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock);
322
323 /**
324 * @brief Disables the selected peripheral clock.
325 * @param clock Enumeration for desired clock.
326 */
327 void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock);
328
329 /**
330 * @brief Enables the selected peripheral clock.
331 * @param clock Enumeration for desired clock.
332 */
333 void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock);
334
335 /**
336 * @brief Enables the 32kHz oscillator
337 * @param mxc_sys_cfg Not used, may be NULL.
338 */
339 void MXC_SYS_RTCClockEnable(void);
340
341 /**
342 * @brief Disables the 32kHz oscillator
343 * @returns E_NO_ERROR if everything is successful
344 */
345 int MXC_SYS_RTCClockDisable(void);
346
347 /**
348 * @brief Enable System Clock Source without switching to it
349 * @param clock The clock to enable
350 * @return E_NO_ERROR if everything is successful
351 */
352 int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock);
353
354 /**
355 * @brief Disable System Clock Source
356 * @param clock The clock to disable
357 * @return E_NO_ERROR if everything is successful
358 */
359 int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock);
360
361 /**
362 * @brief Select the system clock.
363 * @param clock Enumeration for desired clock. Note: If using the external clock input be sure to define EXTCLK_FREQ correctly.
364 * The default EXTCLK_FREQ value is defined in the system_max32690.h file and can be overridden at compile time.
365 * @returns E_NO_ERROR if everything is successful.
366 */
367 int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock);
368
369 /**
370 * @brief Set the system clock divider.
371 * @param div Enumeration for desired clock divider.
372 */
373 void MXC_SYS_SetClockDiv(mxc_sys_system_clock_div_t div);
374
375 /**
376 * @brief Get the system clock divider.
377 * @returns System clock divider.
378 */
379 mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void);
380
381 /**
382 * @brief Wait for a clock to enable with timeout
383 * @param ready The clock to wait for
384 * @return E_NO_ERROR if ready, E_TIME_OUT if timeout
385 */
386 int MXC_SYS_Clock_Timeout(uint32_t ready);
387
388 /**
389 * @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register.
390 * @param Enumeration for what to reset. Can reset multiple items at once.
391 */
392 void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset);
393
394 /**
395 * @brief Setup and run RISCV core
396 */
397 void MXC_SYS_RISCVRun(void);
398
399 /**
400 * @brief Shutdown the RISCV core
401 */
402 void MXC_SYS_RISCVShutdown(void);
403
404 /**
405 * @brief Returns the clock rate (in Hz) of the Risc-V core.
406 */
407 uint32_t MXC_SYS_RiscVClockRate(void);
408
409 /**
410 * @brief This function PERMANENTLY locks the Debug Access Port.
411 *
412 * @warning After executing this function you will never be able
413 * to reprogram the target micro.
414 */
415 int MXC_SYS_LockDAP_Permanent(void);
416
417 #ifdef __cplusplus
418 }
419 #endif
420
421 #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78002_MXC_SYS_H_
422
