1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include "srcc_reva.h"
22
23 #if TARGET_NUM != 32650
24 #include "srcc.h"
MXC_SRCC_RevA_ID(mxc_srcc_reva_regs_t * srcc,mxc_srcc_cache_id_t id)25 uint32_t MXC_SRCC_RevA_ID(mxc_srcc_reva_regs_t *srcc, mxc_srcc_cache_id_t id)
26 {
27 switch (id) {
28 case SRCC_CACHE_ID_RELNUM:
29 return (((srcc->cache_id) & MXC_F_SRCC_REVA_CACHE_ID_RELNUM)) >>
30 MXC_F_SRCC_REVA_CACHE_ID_RELNUM_POS;
31
32 case SRCC_CACHE_ID_PARTNUM:
33 return (((srcc->cache_id) & MXC_F_SRCC_REVA_CACHE_ID_PARTNUM)) >>
34 MXC_F_SRCC_REVA_CACHE_ID_PARTNUM_POS;
35
36 case SRCC_CACHE_ID_CCHID:
37 default:
38 return (((srcc->cache_id) & MXC_F_SRCC_REVA_CACHE_ID_CCHID)) >>
39 MXC_F_SRCC_REVA_CACHE_ID_CCHID_POS;
40 }
41 }
42 #endif
43
MXC_SRCC_RevA_CacheSize(mxc_srcc_reva_regs_t * srcc)44 uint32_t MXC_SRCC_RevA_CacheSize(mxc_srcc_reva_regs_t *srcc)
45 {
46 return (((srcc->memcfg) & MXC_F_SRCC_REVA_MEMCFG_CCHSZ)) >> MXC_F_SRCC_REVA_MEMCFG_CCHSZ_POS;
47 }
48
MXC_SRCC_RevA_MemSize(mxc_srcc_reva_regs_t * srcc)49 uint32_t MXC_SRCC_RevA_MemSize(mxc_srcc_reva_regs_t *srcc)
50 {
51 return (srcc->memcfg & MXC_F_SRCC_REVA_MEMCFG_MEMSZ) >> MXC_F_SRCC_REVA_MEMCFG_MEMSZ_POS;
52 }
53
MXC_SRCC_RevA_Enable(mxc_srcc_reva_regs_t * srcc)54 void MXC_SRCC_RevA_Enable(mxc_srcc_reva_regs_t *srcc)
55 {
56 srcc->cache_ctrl |= MXC_F_SRCC_REVA_CACHE_CTRL_CACHE_EN;
57 }
58
MXC_SRCC_RevA_Disable(mxc_srcc_reva_regs_t * srcc)59 void MXC_SRCC_RevA_Disable(mxc_srcc_reva_regs_t *srcc)
60 {
61 srcc->cache_ctrl &= ~MXC_F_SRCC_REVA_CACHE_CTRL_CACHE_EN;
62 }
63
MXC_SRCC_RevA_WriteAllocateEnable(mxc_srcc_reva_regs_t * srcc)64 void MXC_SRCC_RevA_WriteAllocateEnable(mxc_srcc_reva_regs_t *srcc)
65 {
66 srcc->cache_ctrl |= MXC_F_SRCC_REVA_CACHE_CTRL_WRITE_ALLOC_EN;
67 }
68
MXC_SRCC_RevA_WriteAllocateDisable(mxc_srcc_reva_regs_t * srcc)69 void MXC_SRCC_RevA_WriteAllocateDisable(mxc_srcc_reva_regs_t *srcc)
70 {
71 srcc->cache_ctrl &= ~MXC_F_SRCC_REVA_CACHE_CTRL_WRITE_ALLOC_EN;
72 }
73
MXC_SRCC_RevA_CriticalWordFirstEnable(mxc_srcc_reva_regs_t * srcc)74 void MXC_SRCC_RevA_CriticalWordFirstEnable(mxc_srcc_reva_regs_t *srcc) //cwfst_dis
75 {
76 srcc->cache_ctrl &= ~MXC_F_SRCC_REVA_CACHE_CTRL_CWFST_DIS;
77 }
78
MXC_SRCC_RevA_CriticalWordFirstDisable(mxc_srcc_reva_regs_t * srcc)79 void MXC_SRCC_RevA_CriticalWordFirstDisable(mxc_srcc_reva_regs_t *srcc) //cwfst_dis
80 {
81 srcc->cache_ctrl |= MXC_F_SRCC_REVA_CACHE_CTRL_CWFST_DIS;
82 }
83
MXC_SRCC_RevA_Ready(mxc_srcc_reva_regs_t * srcc)84 uint32_t MXC_SRCC_RevA_Ready(mxc_srcc_reva_regs_t *srcc)
85 {
86 return (srcc->cache_ctrl & MXC_F_SRCC_REVA_CACHE_CTRL_CACHE_RDY) >>
87 MXC_F_SRCC_REVA_CACHE_CTRL_CACHE_RDY_POS;
88 }
89
