1 /** 2 * @file rpu_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the RPU Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup rpu_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_RPU_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_RPU_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup rpu 67 * @defgroup rpu_registers RPU_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the RPU Peripheral Module. 69 * @details Resource Protection Unit 70 */ 71 72 /** 73 * @ingroup rpu_registers 74 * Structure type to access the RPU Registers. 75 */ 76 typedef struct { 77 __IO uint32_t gcr; /**< <tt>\b 0x0000:</tt> RPU GCR Register */ 78 __IO uint32_t sir; /**< <tt>\b 0x0004:</tt> RPU SIR Register */ 79 __IO uint32_t fcr; /**< <tt>\b 0x0008:</tt> RPU FCR Register */ 80 __R uint32_t rsv_0xc; 81 __IO uint32_t tpu; /**< <tt>\b 0x0010:</tt> RPU TPU Register */ 82 __R uint32_t rsv_0x14_0x1f[3]; 83 __IO uint32_t rpu; /**< <tt>\b 0x0020:</tt> RPU RPU Register */ 84 __R uint32_t rsv_0x24_0x2f[3]; 85 __IO uint32_t wdt0; /**< <tt>\b 0x0030:</tt> RPU WDT0 Register */ 86 __IO uint32_t wdt1; /**< <tt>\b 0x0034:</tt> RPU WDT1 Register */ 87 __IO uint32_t wdt2; /**< <tt>\b 0x0038:</tt> RPU WDT2 Register */ 88 __R uint32_t rsv_0x3c; 89 __IO uint32_t smon; /**< <tt>\b 0x0040:</tt> RPU SMON Register */ 90 __IO uint32_t simo; /**< <tt>\b 0x0044:</tt> RPU SIMO Register */ 91 __IO uint32_t dvs; /**< <tt>\b 0x0048:</tt> RPU DVS Register */ 92 __R uint32_t rsv_0x4c; 93 __IO uint32_t aes; /**< <tt>\b 0x0050:</tt> RPU AES Register */ 94 __R uint32_t rsv_0x54_0x5f[3]; 95 __IO uint32_t rtc; /**< <tt>\b 0x0060:</tt> RPU RTC Register */ 96 __IO uint32_t wut; /**< <tt>\b 0x0064:</tt> RPU WUT Register */ 97 __IO uint32_t pwrseq; /**< <tt>\b 0x0068:</tt> RPU PWRSEQ Register */ 98 __IO uint32_t mcr; /**< <tt>\b 0x006C:</tt> RPU MCR Register */ 99 __R uint32_t rsv_0x70_0x7f[4]; 100 __IO uint32_t gpio0; /**< <tt>\b 0x0080:</tt> RPU GPIO0 Register */ 101 __R uint32_t rsv_0x84_0x8f[3]; 102 __IO uint32_t gpio1; /**< <tt>\b 0x0090:</tt> RPU GPIO1 Register */ 103 __R uint32_t rsv_0x94_0xff[27]; 104 __IO uint32_t tmr0; /**< <tt>\b 0x0100:</tt> RPU TMR0 Register */ 105 __R uint32_t rsv_0x104_0x10f[3]; 106 __IO uint32_t tmr1; /**< <tt>\b 0x0110:</tt> RPU TMR1 Register */ 107 __R uint32_t rsv_0x114_0x11f[3]; 108 __IO uint32_t tmr2; /**< <tt>\b 0x0120:</tt> RPU TMR2 Register */ 109 __R uint32_t rsv_0x124_0x12f[3]; 110 __IO uint32_t tmr3; /**< <tt>\b 0x0130:</tt> RPU TMR3 Register */ 111 __R uint32_t rsv_0x134_0x13f[3]; 112 __IO uint32_t tmr4; /**< <tt>\b 0x0140:</tt> RPU TMR4 Register */ 113 __R uint32_t rsv_0x144_0x14f[3]; 114 __IO uint32_t tmr5; /**< <tt>\b 0x0150:</tt> RPU TMR5 Register */ 115 __R uint32_t rsv_0x154_0x1af[23]; 116 __IO uint32_t htimer0; /**< <tt>\b 0x01B0:</tt> RPU HTIMER0 Register */ 117 __R uint32_t rsv_0x1b4_0x1bf[3]; 118 __IO uint32_t htimer1; /**< <tt>\b 0x01C0:</tt> RPU HTIMER1 Register */ 119 __R uint32_t rsv_0x1c4_0x1cf[3]; 120 __IO uint32_t i2c0_bus0; /**< <tt>\b 0x01D0:</tt> RPU I2C0_BUS0 Register */ 121 __R uint32_t rsv_0x1d4_0x1df[3]; 122 __IO uint32_t i2c1_bus0; /**< <tt>\b 0x01E0:</tt> RPU I2C1_BUS0 Register */ 123 __R uint32_t rsv_0x1e4_0x1ef[3]; 124 __IO uint32_t i2c2_bus0; /**< <tt>\b 0x01F0:</tt> RPU I2C2_BUS0 Register */ 125 __R uint32_t rsv_0x1f4_0x25f[27]; 126 __IO uint32_t spixfm; /**< <tt>\b 0x0260:</tt> RPU SPIXFM Register */ 127 __R uint32_t rsv_0x264_0x26f[3]; 128 __IO uint32_t spixfc; /**< <tt>\b 0x0270:</tt> RPU SPIXFC Register */ 129 __R uint32_t rsv_0x274_0x27f[3]; 130 __IO uint32_t dma0; /**< <tt>\b 0x0280:</tt> RPU DMA0 Register */ 131 __R uint32_t rsv_0x284_0x28f[3]; 132 __IO uint32_t flc0; /**< <tt>\b 0x0290:</tt> RPU FLC0 Register */ 133 __IO uint32_t flc1; /**< <tt>\b 0x0294:</tt> RPU FLC1 Register */ 134 __R uint32_t rsv_0x298_0x29f[2]; 135 __IO uint32_t icc0; /**< <tt>\b 0x02A0:</tt> RPU ICC0 Register */ 136 __IO uint32_t icc1; /**< <tt>\b 0x02A4:</tt> RPU ICC1 Register */ 137 __R uint32_t rsv_0x2a8_0x2ef[18]; 138 __IO uint32_t sfcc; /**< <tt>\b 0x02F0:</tt> RPU SFCC Register */ 139 __R uint32_t rsv_0x2f4_0x32f[15]; 140 __IO uint32_t srcc; /**< <tt>\b 0x0330:</tt> RPU SRCC Register */ 141 __R uint32_t rsv_0x334_0x33f[3]; 142 __IO uint32_t adc; /**< <tt>\b 0x0340:</tt> RPU ADC Register */ 143 __R uint32_t rsv_0x344_0x34f[3]; 144 __IO uint32_t dma1; /**< <tt>\b 0x0350:</tt> RPU DMA1 Register */ 145 __R uint32_t rsv_0x354_0x35f[3]; 146 __IO uint32_t sdma; /**< <tt>\b 0x0360:</tt> RPU SDMA Register */ 147 __R uint32_t rsv_0x364_0x36f[3]; 148 __IO uint32_t sdhcctrl; /**< <tt>\b 0x0370:</tt> RPU SDHCCTRL Register */ 149 __R uint32_t rsv_0x374_0x39f[11]; 150 __IO uint32_t spixr; /**< <tt>\b 0x03A0:</tt> RPU SPIXR Register */ 151 __R uint32_t rsv_0x3a4_0x3bf[7]; 152 __IO uint32_t ptg_bus0; /**< <tt>\b 0x03C0:</tt> RPU PTG_BUS0 Register */ 153 __R uint32_t rsv_0x3c4_0x3cf[3]; 154 __IO uint32_t owm; /**< <tt>\b 0x03D0:</tt> RPU OWM Register */ 155 __R uint32_t rsv_0x3d4_0x3df[3]; 156 __IO uint32_t sema; /**< <tt>\b 0x03E0:</tt> RPU SEMA Register */ 157 __R uint32_t rsv_0x3e4_0x41f[15]; 158 __IO uint32_t uart0; /**< <tt>\b 0x0420:</tt> RPU UART0 Register */ 159 __R uint32_t rsv_0x424_0x42f[3]; 160 __IO uint32_t uart1; /**< <tt>\b 0x0430:</tt> RPU UART1 Register */ 161 __R uint32_t rsv_0x434_0x43f[3]; 162 __IO uint32_t uart2; /**< <tt>\b 0x0440:</tt> RPU UART2 Register */ 163 __R uint32_t rsv_0x444_0x45f[7]; 164 __IO uint32_t spi1; /**< <tt>\b 0x0460:</tt> RPU SPI1 Register */ 165 __R uint32_t rsv_0x464_0x46f[3]; 166 __IO uint32_t spi2; /**< <tt>\b 0x0470:</tt> RPU SPI2 Register */ 167 __R uint32_t rsv_0x474_0x4bf[19]; 168 __IO uint32_t audio; /**< <tt>\b 0x04C0:</tt> RPU AUDIO Register */ 169 __R uint32_t rsv_0x4c4_0x4cf[3]; 170 __IO uint32_t trng; /**< <tt>\b 0x04D0:</tt> RPU TRNG Register */ 171 __R uint32_t rsv_0x4d4_0x4ff[11]; 172 __IO uint32_t btle; /**< <tt>\b 0x0500:</tt> RPU BTLE Register */ 173 __R uint32_t rsv_0x504_0xb0f[387]; 174 __IO uint32_t usbhs; /**< <tt>\b 0x0B10:</tt> RPU USBHS Register */ 175 __R uint32_t rsv_0xb14_0xb5f[19]; 176 __IO uint32_t sdio; /**< <tt>\b 0x0B60:</tt> RPU SDIO Register */ 177 __R uint32_t rsv_0xb64_0xbbf[23]; 178 __IO uint32_t spixfm_fifo; /**< <tt>\b 0x0BC0:</tt> RPU SPIXFM_FIFO Register */ 179 __R uint32_t rsv_0xbc4_0xbdf[7]; 180 __IO uint32_t spi0; /**< <tt>\b 0x0BE0:</tt> RPU SPI0 Register */ 181 __R uint32_t rsv_0xbe4_0xeff[199]; 182 __IO uint32_t sysram0; /**< <tt>\b 0x0F00:</tt> RPU SYSRAM0 Register */ 183 __R uint32_t rsv_0xf04_0xf0f[3]; 184 __IO uint32_t sysram1; /**< <tt>\b 0x0F10:</tt> RPU SYSRAM1 Register */ 185 __R uint32_t rsv_0xf14_0xf1f[3]; 186 __IO uint32_t sysram2; /**< <tt>\b 0x0F20:</tt> RPU SYSRAM2 Register */ 187 __R uint32_t rsv_0xf24_0xf2f[3]; 188 __IO uint32_t sysram3; /**< <tt>\b 0x0F30:</tt> RPU SYSRAM3 Register */ 189 __R uint32_t rsv_0xf34_0xf3f[3]; 190 __IO uint32_t sysram4; /**< <tt>\b 0x0F40:</tt> RPU SYSRAM4 Register */ 191 __R uint32_t rsv_0xf44_0xf4f[3]; 192 __IO uint32_t sysram5; /**< <tt>\b 0x0F50:</tt> RPU SYSRAM5 Register */ 193 __R uint32_t rsv_0xf54_0xf5f[3]; 194 __IO uint32_t sysram6_11; /**< <tt>\b 0x0F60:</tt> RPU SYSRAM6_11 Register */ 195 __R uint32_t rsv_0xf64_0x11cf[155]; 196 __IO uint32_t i2c0_bus1; /**< <tt>\b 0x11D0:</tt> RPU I2C0_BUS1 Register */ 197 __R uint32_t rsv_0x11d4_0x11df[3]; 198 __IO uint32_t i2c1_bus1; /**< <tt>\b 0x11E0:</tt> RPU I2C1_BUS1 Register */ 199 __R uint32_t rsv_0x11e4_0x11ef[3]; 200 __IO uint32_t i2c2_bus1; /**< <tt>\b 0x11F0:</tt> RPU I2C2_BUS1 Register */ 201 __R uint32_t rsv_0x11f4_0x13bf[115]; 202 __IO uint32_t ptg_bus1; /**< <tt>\b 0x13C0:</tt> RPU PTG_BUS1 Register */ 203 } mxc_rpu_regs_t; 204 205 /* Register offsets for module RPU */ 206 /** 207 * @ingroup rpu_registers 208 * @defgroup RPU_Register_Offsets Register Offsets 209 * @brief RPU Peripheral Register Offsets from the RPU Base Peripheral Address. 210 * @{ 211 */ 212 #define MXC_R_RPU_GCR ((uint32_t)0x00000000UL) /**< Offset from RPU Base Address: <tt> 0x0000</tt> */ 213 #define MXC_R_RPU_SIR ((uint32_t)0x00000004UL) /**< Offset from RPU Base Address: <tt> 0x0004</tt> */ 214 #define MXC_R_RPU_FCR ((uint32_t)0x00000008UL) /**< Offset from RPU Base Address: <tt> 0x0008</tt> */ 215 #define MXC_R_RPU_TPU ((uint32_t)0x00000010UL) /**< Offset from RPU Base Address: <tt> 0x0010</tt> */ 216 #define MXC_R_RPU_RPU ((uint32_t)0x00000020UL) /**< Offset from RPU Base Address: <tt> 0x0020</tt> */ 217 #define MXC_R_RPU_WDT0 ((uint32_t)0x00000030UL) /**< Offset from RPU Base Address: <tt> 0x0030</tt> */ 218 #define MXC_R_RPU_WDT1 ((uint32_t)0x00000034UL) /**< Offset from RPU Base Address: <tt> 0x0034</tt> */ 219 #define MXC_R_RPU_WDT2 ((uint32_t)0x00000038UL) /**< Offset from RPU Base Address: <tt> 0x0038</tt> */ 220 #define MXC_R_RPU_SMON ((uint32_t)0x00000040UL) /**< Offset from RPU Base Address: <tt> 0x0040</tt> */ 221 #define MXC_R_RPU_SIMO ((uint32_t)0x00000044UL) /**< Offset from RPU Base Address: <tt> 0x0044</tt> */ 222 #define MXC_R_RPU_DVS ((uint32_t)0x00000048UL) /**< Offset from RPU Base Address: <tt> 0x0048</tt> */ 223 #define MXC_R_RPU_AES ((uint32_t)0x00000050UL) /**< Offset from RPU Base Address: <tt> 0x0050</tt> */ 224 #define MXC_R_RPU_RTC ((uint32_t)0x00000060UL) /**< Offset from RPU Base Address: <tt> 0x0060</tt> */ 225 #define MXC_R_RPU_WUT ((uint32_t)0x00000064UL) /**< Offset from RPU Base Address: <tt> 0x0064</tt> */ 226 #define MXC_R_RPU_PWRSEQ ((uint32_t)0x00000068UL) /**< Offset from RPU Base Address: <tt> 0x0068</tt> */ 227 #define MXC_R_RPU_MCR ((uint32_t)0x0000006CUL) /**< Offset from RPU Base Address: <tt> 0x006C</tt> */ 228 #define MXC_R_RPU_GPIO0 ((uint32_t)0x00000080UL) /**< Offset from RPU Base Address: <tt> 0x0080</tt> */ 229 #define MXC_R_RPU_GPIO1 ((uint32_t)0x00000090UL) /**< Offset from RPU Base Address: <tt> 0x0090</tt> */ 230 #define MXC_R_RPU_TMR0 ((uint32_t)0x00000100UL) /**< Offset from RPU Base Address: <tt> 0x0100</tt> */ 231 #define MXC_R_RPU_TMR1 ((uint32_t)0x00000110UL) /**< Offset from RPU Base Address: <tt> 0x0110</tt> */ 232 #define MXC_R_RPU_TMR2 ((uint32_t)0x00000120UL) /**< Offset from RPU Base Address: <tt> 0x0120</tt> */ 233 #define MXC_R_RPU_TMR3 ((uint32_t)0x00000130UL) /**< Offset from RPU Base Address: <tt> 0x0130</tt> */ 234 #define MXC_R_RPU_TMR4 ((uint32_t)0x00000140UL) /**< Offset from RPU Base Address: <tt> 0x0140</tt> */ 235 #define MXC_R_RPU_TMR5 ((uint32_t)0x00000150UL) /**< Offset from RPU Base Address: <tt> 0x0150</tt> */ 236 #define MXC_R_RPU_HTIMER0 ((uint32_t)0x000001B0UL) /**< Offset from RPU Base Address: <tt> 0x01B0</tt> */ 237 #define MXC_R_RPU_HTIMER1 ((uint32_t)0x000001C0UL) /**< Offset from RPU Base Address: <tt> 0x01C0</tt> */ 238 #define MXC_R_RPU_I2C0_BUS0 ((uint32_t)0x000001D0UL) /**< Offset from RPU Base Address: <tt> 0x01D0</tt> */ 239 #define MXC_R_RPU_I2C1_BUS0 ((uint32_t)0x000001E0UL) /**< Offset from RPU Base Address: <tt> 0x01E0</tt> */ 240 #define MXC_R_RPU_I2C2_BUS0 ((uint32_t)0x000001F0UL) /**< Offset from RPU Base Address: <tt> 0x01F0</tt> */ 241 #define MXC_R_RPU_SPIXFM ((uint32_t)0x00000260UL) /**< Offset from RPU Base Address: <tt> 0x0260</tt> */ 242 #define MXC_R_RPU_SPIXFC ((uint32_t)0x00000270UL) /**< Offset from RPU Base Address: <tt> 0x0270</tt> */ 243 #define MXC_R_RPU_DMA0 ((uint32_t)0x00000280UL) /**< Offset from RPU Base Address: <tt> 0x0280</tt> */ 244 #define MXC_R_RPU_FLC0 ((uint32_t)0x00000290UL) /**< Offset from RPU Base Address: <tt> 0x0290</tt> */ 245 #define MXC_R_RPU_FLC1 ((uint32_t)0x00000294UL) /**< Offset from RPU Base Address: <tt> 0x0294</tt> */ 246 #define MXC_R_RPU_ICC0 ((uint32_t)0x000002A0UL) /**< Offset from RPU Base Address: <tt> 0x02A0</tt> */ 247 #define MXC_R_RPU_ICC1 ((uint32_t)0x000002A4UL) /**< Offset from RPU Base Address: <tt> 0x02A4</tt> */ 248 #define MXC_R_RPU_SFCC ((uint32_t)0x000002F0UL) /**< Offset from RPU Base Address: <tt> 0x02F0</tt> */ 249 #define MXC_R_RPU_SRCC ((uint32_t)0x00000330UL) /**< Offset from RPU Base Address: <tt> 0x0330</tt> */ 250 #define MXC_R_RPU_ADC ((uint32_t)0x00000340UL) /**< Offset from RPU Base Address: <tt> 0x0340</tt> */ 251 #define MXC_R_RPU_DMA1 ((uint32_t)0x00000350UL) /**< Offset from RPU Base Address: <tt> 0x0350</tt> */ 252 #define MXC_R_RPU_SDMA ((uint32_t)0x00000360UL) /**< Offset from RPU Base Address: <tt> 0x0360</tt> */ 253 #define MXC_R_RPU_SDHCCTRL ((uint32_t)0x00000370UL) /**< Offset from RPU Base Address: <tt> 0x0370</tt> */ 254 #define MXC_R_RPU_SPIXR ((uint32_t)0x000003A0UL) /**< Offset from RPU Base Address: <tt> 0x03A0</tt> */ 255 #define MXC_R_RPU_PTG_BUS0 ((uint32_t)0x000003C0UL) /**< Offset from RPU Base Address: <tt> 0x03C0</tt> */ 256 #define MXC_R_RPU_OWM ((uint32_t)0x000003D0UL) /**< Offset from RPU Base Address: <tt> 0x03D0</tt> */ 257 #define MXC_R_RPU_SEMA ((uint32_t)0x000003E0UL) /**< Offset from RPU Base Address: <tt> 0x03E0</tt> */ 258 #define MXC_R_RPU_UART0 ((uint32_t)0x00000420UL) /**< Offset from RPU Base Address: <tt> 0x0420</tt> */ 259 #define MXC_R_RPU_UART1 ((uint32_t)0x00000430UL) /**< Offset from RPU Base Address: <tt> 0x0430</tt> */ 260 #define MXC_R_RPU_UART2 ((uint32_t)0x00000440UL) /**< Offset from RPU Base Address: <tt> 0x0440</tt> */ 261 #define MXC_R_RPU_SPI1 ((uint32_t)0x00000460UL) /**< Offset from RPU Base Address: <tt> 0x0460</tt> */ 262 #define MXC_R_RPU_SPI2 ((uint32_t)0x00000470UL) /**< Offset from RPU Base Address: <tt> 0x0470</tt> */ 263 #define MXC_R_RPU_AUDIO ((uint32_t)0x000004C0UL) /**< Offset from RPU Base Address: <tt> 0x04C0</tt> */ 264 #define MXC_R_RPU_TRNG ((uint32_t)0x000004D0UL) /**< Offset from RPU Base Address: <tt> 0x04D0</tt> */ 265 #define MXC_R_RPU_BTLE ((uint32_t)0x00000500UL) /**< Offset from RPU Base Address: <tt> 0x0500</tt> */ 266 #define MXC_R_RPU_USBHS ((uint32_t)0x00000B10UL) /**< Offset from RPU Base Address: <tt> 0x0B10</tt> */ 267 #define MXC_R_RPU_SDIO ((uint32_t)0x00000B60UL) /**< Offset from RPU Base Address: <tt> 0x0B60</tt> */ 268 #define MXC_R_RPU_SPIXFM_FIFO ((uint32_t)0x00000BC0UL) /**< Offset from RPU Base Address: <tt> 0x0BC0</tt> */ 269 #define MXC_R_RPU_SPI0 ((uint32_t)0x00000BE0UL) /**< Offset from RPU Base Address: <tt> 0x0BE0</tt> */ 270 #define MXC_R_RPU_SYSRAM0 ((uint32_t)0x00000F00UL) /**< Offset from RPU Base Address: <tt> 0x0F00</tt> */ 271 #define MXC_R_RPU_SYSRAM1 ((uint32_t)0x00000F10UL) /**< Offset from RPU Base Address: <tt> 0x0F10</tt> */ 272 #define MXC_R_RPU_SYSRAM2 ((uint32_t)0x00000F20UL) /**< Offset from RPU Base Address: <tt> 0x0F20</tt> */ 273 #define MXC_R_RPU_SYSRAM3 ((uint32_t)0x00000F30UL) /**< Offset from RPU Base Address: <tt> 0x0F30</tt> */ 274 #define MXC_R_RPU_SYSRAM4 ((uint32_t)0x00000F40UL) /**< Offset from RPU Base Address: <tt> 0x0F40</tt> */ 275 #define MXC_R_RPU_SYSRAM5 ((uint32_t)0x00000F50UL) /**< Offset from RPU Base Address: <tt> 0x0F50</tt> */ 276 #define MXC_R_RPU_SYSRAM6_11 ((uint32_t)0x00000F60UL) /**< Offset from RPU Base Address: <tt> 0x0F60</tt> */ 277 #define MXC_R_RPU_I2C0_BUS1 ((uint32_t)0x000011D0UL) /**< Offset from RPU Base Address: <tt> 0x11D0</tt> */ 278 #define MXC_R_RPU_I2C1_BUS1 ((uint32_t)0x000011E0UL) /**< Offset from RPU Base Address: <tt> 0x11E0</tt> */ 279 #define MXC_R_RPU_I2C2_BUS1 ((uint32_t)0x000011F0UL) /**< Offset from RPU Base Address: <tt> 0x11F0</tt> */ 280 #define MXC_R_RPU_PTG_BUS1 ((uint32_t)0x000013C0UL) /**< Offset from RPU Base Address: <tt> 0x13C0</tt> */ 281 /**@} end of group rpu_registers */ 282 283 /** 284 * @ingroup rpu_registers 285 * @defgroup RPU_GCR RPU_GCR 286 * @brief GCR RPU Register. 287 * @{ 288 */ 289 #define MXC_F_RPU_GCR_ACCESS_POS 0 /**< GCR_ACCESS Position */ 290 #define MXC_F_RPU_GCR_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_GCR_ACCESS_POS)) /**< GCR_ACCESS Mask */ 291 292 /**@} end of group RPU_GCR_Register */ 293 294 /** 295 * @ingroup rpu_registers 296 * @defgroup RPU_SIR RPU_SIR 297 * @brief SIR RPU Register. 298 * @{ 299 */ 300 #define MXC_F_RPU_SIR_ACCESS_POS 0 /**< SIR_ACCESS Position */ 301 #define MXC_F_RPU_SIR_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SIR_ACCESS_POS)) /**< SIR_ACCESS Mask */ 302 303 /**@} end of group RPU_SIR_Register */ 304 305 /** 306 * @ingroup rpu_registers 307 * @defgroup RPU_FCR RPU_FCR 308 * @brief FCR RPU Register. 309 * @{ 310 */ 311 #define MXC_F_RPU_FCR_ACCESS_POS 0 /**< FCR_ACCESS Position */ 312 #define MXC_F_RPU_FCR_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_FCR_ACCESS_POS)) /**< FCR_ACCESS Mask */ 313 314 /**@} end of group RPU_FCR_Register */ 315 316 /** 317 * @ingroup rpu_registers 318 * @defgroup RPU_TPU RPU_TPU 319 * @brief TPU RPU Register. 320 * @{ 321 */ 322 #define MXC_F_RPU_TPU_ACCESS_POS 0 /**< TPU_ACCESS Position */ 323 #define MXC_F_RPU_TPU_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TPU_ACCESS_POS)) /**< TPU_ACCESS Mask */ 324 325 /**@} end of group RPU_TPU_Register */ 326 327 /** 328 * @ingroup rpu_registers 329 * @defgroup RPU_RPU RPU_RPU 330 * @brief RPU Register. 331 * @{ 332 */ 333 #define MXC_F_RPU_RPU_ACCESS_POS 0 /**< RPU_ACCESS Position */ 334 #define MXC_F_RPU_RPU_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_RPU_ACCESS_POS)) /**< RPU_ACCESS Mask */ 335 336 /**@} end of group RPU_RPU_Register */ 337 338 /** 339 * @ingroup rpu_registers 340 * @defgroup RPU_WDT0 RPU_WDT0 341 * @brief WDT0 RPU Register. 342 * @{ 343 */ 344 #define MXC_F_RPU_WDT0_ACCESS_POS 0 /**< WDT0_ACCESS Position */ 345 #define MXC_F_RPU_WDT0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_WDT0_ACCESS_POS)) /**< WDT0_ACCESS Mask */ 346 347 /**@} end of group RPU_WDT0_Register */ 348 349 /** 350 * @ingroup rpu_registers 351 * @defgroup RPU_WDT1 RPU_WDT1 352 * @brief WDT1 RPU Register. 353 * @{ 354 */ 355 #define MXC_F_RPU_WDT1_ACCESS_POS 0 /**< WDT1_ACCESS Position */ 356 #define MXC_F_RPU_WDT1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_WDT1_ACCESS_POS)) /**< WDT1_ACCESS Mask */ 357 358 /**@} end of group RPU_WDT1_Register */ 359 360 /** 361 * @ingroup rpu_registers 362 * @defgroup RPU_WDT2 RPU_WDT2 363 * @brief WDT2 RPU Register. 364 * @{ 365 */ 366 #define MXC_F_RPU_WDT2_ACCESS_POS 0 /**< WDT2_ACCESS Position */ 367 #define MXC_F_RPU_WDT2_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_WDT2_ACCESS_POS)) /**< WDT2_ACCESS Mask */ 368 369 /**@} end of group RPU_WDT2_Register */ 370 371 /** 372 * @ingroup rpu_registers 373 * @defgroup RPU_SMON RPU_SMON 374 * @brief SMON RPU Register. 375 * @{ 376 */ 377 #define MXC_F_RPU_SMON_ACCESS_POS 0 /**< SMON_ACCESS Position */ 378 #define MXC_F_RPU_SMON_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SMON_ACCESS_POS)) /**< SMON_ACCESS Mask */ 379 380 /**@} end of group RPU_SMON_Register */ 381 382 /** 383 * @ingroup rpu_registers 384 * @defgroup RPU_SIMO RPU_SIMO 385 * @brief SIMO RPU Register. 386 * @{ 387 */ 388 #define MXC_F_RPU_SIMO_ACCESS_POS 0 /**< SIMO_ACCESS Position */ 389 #define MXC_F_RPU_SIMO_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SIMO_ACCESS_POS)) /**< SIMO_ACCESS Mask */ 390 391 /**@} end of group RPU_SIMO_Register */ 392 393 /** 394 * @ingroup rpu_registers 395 * @defgroup RPU_DVS RPU_DVS 396 * @brief DVS RPU Register. 397 * @{ 398 */ 399 #define MXC_F_RPU_DVS_ACCESS_POS 0 /**< DVS_ACCESS Position */ 400 #define MXC_F_RPU_DVS_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_DVS_ACCESS_POS)) /**< DVS_ACCESS Mask */ 401 402 /**@} end of group RPU_DVS_Register */ 403 404 /** 405 * @ingroup rpu_registers 406 * @defgroup RPU_AES RPU_AES 407 * @brief AES RPU Register. 408 * @{ 409 */ 410 #define MXC_F_RPU_AES_ACCESS_POS 0 /**< AES_ACCESS Position */ 411 #define MXC_F_RPU_AES_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_AES_ACCESS_POS)) /**< AES_ACCESS Mask */ 412 413 /**@} end of group RPU_AES_Register */ 414 415 /** 416 * @ingroup rpu_registers 417 * @defgroup RPU_RTC RPU_RTC 418 * @brief RTC RPU Register. 419 * @{ 420 */ 421 #define MXC_F_RPU_RTC_ACCESS_POS 0 /**< RTC_ACCESS Position */ 422 #define MXC_F_RPU_RTC_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_RTC_ACCESS_POS)) /**< RTC_ACCESS Mask */ 423 424 /**@} end of group RPU_RTC_Register */ 425 426 /** 427 * @ingroup rpu_registers 428 * @defgroup RPU_WUT RPU_WUT 429 * @brief WUT RPU Register. 430 * @{ 431 */ 432 #define MXC_F_RPU_WUT_ACCESS_POS 0 /**< WUT_ACCESS Position */ 433 #define MXC_F_RPU_WUT_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_WUT_ACCESS_POS)) /**< WUT_ACCESS Mask */ 434 435 /**@} end of group RPU_WUT_Register */ 436 437 /** 438 * @ingroup rpu_registers 439 * @defgroup RPU_PWRSEQ RPU_PWRSEQ 440 * @brief PWRSEQ RPU Register. 441 * @{ 442 */ 443 #define MXC_F_RPU_PWRSEQ_ACCESS_POS 0 /**< PWRSEQ_ACCESS Position */ 444 #define MXC_F_RPU_PWRSEQ_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_PWRSEQ_ACCESS_POS)) /**< PWRSEQ_ACCESS Mask */ 445 446 /**@} end of group RPU_PWRSEQ_Register */ 447 448 /** 449 * @ingroup rpu_registers 450 * @defgroup RPU_MCR RPU_MCR 451 * @brief MCR RPU Register. 452 * @{ 453 */ 454 #define MXC_F_RPU_MCR_ACCESS_POS 0 /**< MCR_ACCESS Position */ 455 #define MXC_F_RPU_MCR_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_MCR_ACCESS_POS)) /**< MCR_ACCESS Mask */ 456 457 /**@} end of group RPU_MCR_Register */ 458 459 /** 460 * @ingroup rpu_registers 461 * @defgroup RPU_GPIO0 RPU_GPIO0 462 * @brief GPIO0 RPU Register. 463 * @{ 464 */ 465 #define MXC_F_RPU_GPIO0_ACCESS_POS 0 /**< GPIO0_ACCESS Position */ 466 #define MXC_F_RPU_GPIO0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_GPIO0_ACCESS_POS)) /**< GPIO0_ACCESS Mask */ 467 468 /**@} end of group RPU_GPIO0_Register */ 469 470 /** 471 * @ingroup rpu_registers 472 * @defgroup RPU_GPIO1 RPU_GPIO1 473 * @brief GPIO1 RPU Register. 474 * @{ 475 */ 476 #define MXC_F_RPU_GPIO1_ACCESS_POS 0 /**< GPIO1_ACCESS Position */ 477 #define MXC_F_RPU_GPIO1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_GPIO1_ACCESS_POS)) /**< GPIO1_ACCESS Mask */ 478 479 /**@} end of group RPU_GPIO1_Register */ 480 481 /** 482 * @ingroup rpu_registers 483 * @defgroup RPU_TMR0 RPU_TMR0 484 * @brief TMR0 RPU Register. 485 * @{ 486 */ 487 #define MXC_F_RPU_TMR0_ACCESS_POS 0 /**< TMR0_ACCESS Position */ 488 #define MXC_F_RPU_TMR0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TMR0_ACCESS_POS)) /**< TMR0_ACCESS Mask */ 489 490 /**@} end of group RPU_TMR0_Register */ 491 492 /** 493 * @ingroup rpu_registers 494 * @defgroup RPU_TMR1 RPU_TMR1 495 * @brief TMR1 RPU Register. 496 * @{ 497 */ 498 #define MXC_F_RPU_TMR1_ACCESS_POS 0 /**< TMR1_ACCESS Position */ 499 #define MXC_F_RPU_TMR1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TMR1_ACCESS_POS)) /**< TMR1_ACCESS Mask */ 500 501 /**@} end of group RPU_TMR1_Register */ 502 503 /** 504 * @ingroup rpu_registers 505 * @defgroup RPU_TMR2 RPU_TMR2 506 * @brief TMR2 RPU Register. 507 * @{ 508 */ 509 #define MXC_F_RPU_TMR2_ACCESS_POS 0 /**< TMR2_ACCESS Position */ 510 #define MXC_F_RPU_TMR2_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TMR2_ACCESS_POS)) /**< TMR2_ACCESS Mask */ 511 512 /**@} end of group RPU_TMR2_Register */ 513 514 /** 515 * @ingroup rpu_registers 516 * @defgroup RPU_TMR3 RPU_TMR3 517 * @brief TMR3 RPU Register. 518 * @{ 519 */ 520 #define MXC_F_RPU_TMR3_ACCESS_POS 0 /**< TMR3_ACCESS Position */ 521 #define MXC_F_RPU_TMR3_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TMR3_ACCESS_POS)) /**< TMR3_ACCESS Mask */ 522 523 /**@} end of group RPU_TMR3_Register */ 524 525 /** 526 * @ingroup rpu_registers 527 * @defgroup RPU_TMR4 RPU_TMR4 528 * @brief TMR4 RPU Register. 529 * @{ 530 */ 531 #define MXC_F_RPU_TMR4_ACCESS_POS 0 /**< TMR4_ACCESS Position */ 532 #define MXC_F_RPU_TMR4_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TMR4_ACCESS_POS)) /**< TMR4_ACCESS Mask */ 533 534 /**@} end of group RPU_TMR4_Register */ 535 536 /** 537 * @ingroup rpu_registers 538 * @defgroup RPU_TMR5 RPU_TMR5 539 * @brief TMR5 RPU Register. 540 * @{ 541 */ 542 #define MXC_F_RPU_TMR5_ACCESS_POS 0 /**< TMR5_ACCESS Position */ 543 #define MXC_F_RPU_TMR5_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TMR5_ACCESS_POS)) /**< TMR5_ACCESS Mask */ 544 545 /**@} end of group RPU_TMR5_Register */ 546 547 /** 548 * @ingroup rpu_registers 549 * @defgroup RPU_HTIMER0 RPU_HTIMER0 550 * @brief HTIMER0 RPU Register. 551 * @{ 552 */ 553 #define MXC_F_RPU_HTIMER0_ACCESS_POS 0 /**< HTIMER0_ACCESS Position */ 554 #define MXC_F_RPU_HTIMER0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_HTIMER0_ACCESS_POS)) /**< HTIMER0_ACCESS Mask */ 555 556 /**@} end of group RPU_HTIMER0_Register */ 557 558 /** 559 * @ingroup rpu_registers 560 * @defgroup RPU_HTIMER1 RPU_HTIMER1 561 * @brief HTIMER1 RPU Register. 562 * @{ 563 */ 564 #define MXC_F_RPU_HTIMER1_ACCESS_POS 0 /**< HTIMER1_ACCESS Position */ 565 #define MXC_F_RPU_HTIMER1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_HTIMER1_ACCESS_POS)) /**< HTIMER1_ACCESS Mask */ 566 567 /**@} end of group RPU_HTIMER1_Register */ 568 569 /** 570 * @ingroup rpu_registers 571 * @defgroup RPU_I2C0_BUS0 RPU_I2C0_BUS0 572 * @brief I2C0_BUS0 RPU Register. 573 * @{ 574 */ 575 #define MXC_F_RPU_I2C0_BUS0_ACCESS_POS 0 /**< I2C0_BUS0_ACCESS Position */ 576 #define MXC_F_RPU_I2C0_BUS0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_I2C0_BUS0_ACCESS_POS)) /**< I2C0_BUS0_ACCESS Mask */ 577 578 /**@} end of group RPU_I2C0_BUS0_Register */ 579 580 /** 581 * @ingroup rpu_registers 582 * @defgroup RPU_I2C1_BUS0 RPU_I2C1_BUS0 583 * @brief I2C1_BUS0 RPU Register. 584 * @{ 585 */ 586 #define MXC_F_RPU_I2C1_BUS0_ACCESS_POS 0 /**< I2C1_BUS0_ACCESS Position */ 587 #define MXC_F_RPU_I2C1_BUS0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_I2C1_BUS0_ACCESS_POS)) /**< I2C1_BUS0_ACCESS Mask */ 588 589 /**@} end of group RPU_I2C1_BUS0_Register */ 590 591 /** 592 * @ingroup rpu_registers 593 * @defgroup RPU_I2C2_BUS0 RPU_I2C2_BUS0 594 * @brief I2C2_BUS0 RPU Register. 595 * @{ 596 */ 597 #define MXC_F_RPU_I2C2_BUS0_ACCESS_POS 0 /**< I2C2_BUS0_ACCESS Position */ 598 #define MXC_F_RPU_I2C2_BUS0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_I2C2_BUS0_ACCESS_POS)) /**< I2C2_BUS0_ACCESS Mask */ 599 600 /**@} end of group RPU_I2C2_BUS0_Register */ 601 602 /** 603 * @ingroup rpu_registers 604 * @defgroup RPU_SPIXFM RPU_SPIXFM 605 * @brief SPIXFM RPU Register. 606 * @{ 607 */ 608 #define MXC_F_RPU_SPIXFM_ACCESS_POS 0 /**< SPIXFM_ACCESS Position */ 609 #define MXC_F_RPU_SPIXFM_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPIXFM_ACCESS_POS)) /**< SPIXFM_ACCESS Mask */ 610 611 /**@} end of group RPU_SPIXFM_Register */ 612 613 /** 614 * @ingroup rpu_registers 615 * @defgroup RPU_SPIXFC RPU_SPIXFC 616 * @brief SPIXFC RPU Register. 617 * @{ 618 */ 619 #define MXC_F_RPU_SPIXFC_ACCESS_POS 0 /**< SPIXFC_ACCESS Position */ 620 #define MXC_F_RPU_SPIXFC_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPIXFC_ACCESS_POS)) /**< SPIXFC_ACCESS Mask */ 621 622 /**@} end of group RPU_SPIXFC_Register */ 623 624 /** 625 * @ingroup rpu_registers 626 * @defgroup RPU_DMA0 RPU_DMA0 627 * @brief DMA0 RPU Register. 628 * @{ 629 */ 630 #define MXC_F_RPU_DMA0_ACCESS_POS 0 /**< DMA0_ACCESS Position */ 631 #define MXC_F_RPU_DMA0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_DMA0_ACCESS_POS)) /**< DMA0_ACCESS Mask */ 632 633 /**@} end of group RPU_DMA0_Register */ 634 635 /** 636 * @ingroup rpu_registers 637 * @defgroup RPU_FLC0 RPU_FLC0 638 * @brief FLC0 RPU Register. 639 * @{ 640 */ 641 #define MXC_F_RPU_FLC0_ACCESS_POS 0 /**< FLC0_ACCESS Position */ 642 #define MXC_F_RPU_FLC0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_FLC0_ACCESS_POS)) /**< FLC0_ACCESS Mask */ 643 644 /**@} end of group RPU_FLC0_Register */ 645 646 /** 647 * @ingroup rpu_registers 648 * @defgroup RPU_FLC1 RPU_FLC1 649 * @brief FLC1 RPU Register. 650 * @{ 651 */ 652 #define MXC_F_RPU_FLC1_ACCESS_POS 0 /**< FLC1_ACCESS Position */ 653 #define MXC_F_RPU_FLC1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_FLC1_ACCESS_POS)) /**< FLC1_ACCESS Mask */ 654 655 /**@} end of group RPU_FLC1_Register */ 656 657 /** 658 * @ingroup rpu_registers 659 * @defgroup RPU_ICC0 RPU_ICC0 660 * @brief ICC0 RPU Register. 661 * @{ 662 */ 663 #define MXC_F_RPU_ICC0_ACCESS_POS 0 /**< ICC0_ACCESS Position */ 664 #define MXC_F_RPU_ICC0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_ICC0_ACCESS_POS)) /**< ICC0_ACCESS Mask */ 665 666 /**@} end of group RPU_ICC0_Register */ 667 668 /** 669 * @ingroup rpu_registers 670 * @defgroup RPU_ICC1 RPU_ICC1 671 * @brief ICC1 RPU Register. 672 * @{ 673 */ 674 #define MXC_F_RPU_ICC1_ACCESS_POS 0 /**< ICC1_ACCESS Position */ 675 #define MXC_F_RPU_ICC1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_ICC1_ACCESS_POS)) /**< ICC1_ACCESS Mask */ 676 677 /**@} end of group RPU_ICC1_Register */ 678 679 /** 680 * @ingroup rpu_registers 681 * @defgroup RPU_SFCC RPU_SFCC 682 * @brief SFCC RPU Register. 683 * @{ 684 */ 685 #define MXC_F_RPU_SFCC_ACCESS_POS 0 /**< SFCC_ACCESS Position */ 686 #define MXC_F_RPU_SFCC_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SFCC_ACCESS_POS)) /**< SFCC_ACCESS Mask */ 687 688 /**@} end of group RPU_SFCC_Register */ 689 690 /** 691 * @ingroup rpu_registers 692 * @defgroup RPU_SRCC RPU_SRCC 693 * @brief SRCC RPU Register. 694 * @{ 695 */ 696 #define MXC_F_RPU_SRCC_ACCESS_POS 0 /**< SRCC_ACCESS Position */ 697 #define MXC_F_RPU_SRCC_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SRCC_ACCESS_POS)) /**< SRCC_ACCESS Mask */ 698 699 /**@} end of group RPU_SRCC_Register */ 700 701 /** 702 * @ingroup rpu_registers 703 * @defgroup RPU_ADC RPU_ADC 704 * @brief ADC RPU Register. 705 * @{ 706 */ 707 #define MXC_F_RPU_ADC_ACCESS_POS 0 /**< ADC_ACCESS Position */ 708 #define MXC_F_RPU_ADC_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_ADC_ACCESS_POS)) /**< ADC_ACCESS Mask */ 709 710 /**@} end of group RPU_ADC_Register */ 711 712 /** 713 * @ingroup rpu_registers 714 * @defgroup RPU_DMA1 RPU_DMA1 715 * @brief DMA1 RPU Register. 716 * @{ 717 */ 718 #define MXC_F_RPU_DMA1_ACCESS_POS 0 /**< DMA1_ACCESS Position */ 719 #define MXC_F_RPU_DMA1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_DMA1_ACCESS_POS)) /**< DMA1_ACCESS Mask */ 720 721 /**@} end of group RPU_DMA1_Register */ 722 723 /** 724 * @ingroup rpu_registers 725 * @defgroup RPU_SDMA RPU_SDMA 726 * @brief SDMA RPU Register. 727 * @{ 728 */ 729 #define MXC_F_RPU_SDMA_ACCESS_POS 0 /**< SDMA_ACCESS Position */ 730 #define MXC_F_RPU_SDMA_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SDMA_ACCESS_POS)) /**< SDMA_ACCESS Mask */ 731 732 /**@} end of group RPU_SDMA_Register */ 733 734 /** 735 * @ingroup rpu_registers 736 * @defgroup RPU_SDHCCTRL RPU_SDHCCTRL 737 * @brief SD Host Controller (APB). 738 * @{ 739 */ 740 #define MXC_F_RPU_SDHCCTRL_ACCESS_POS 0 /**< SDHCCTRL_ACCESS Position */ 741 #define MXC_F_RPU_SDHCCTRL_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SDHCCTRL_ACCESS_POS)) /**< SDHCCTRL_ACCESS Mask */ 742 743 /**@} end of group RPU_SDHCCTRL_Register */ 744 745 /** 746 * @ingroup rpu_registers 747 * @defgroup RPU_SPIXR RPU_SPIXR 748 * @brief SPIXR RPU Register. 749 * @{ 750 */ 751 #define MXC_F_RPU_SPIXR_ACCESS_POS 0 /**< SPIXR_ACCESS Position */ 752 #define MXC_F_RPU_SPIXR_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPIXR_ACCESS_POS)) /**< SPIXR_ACCESS Mask */ 753 754 /**@} end of group RPU_SPIXR_Register */ 755 756 /** 757 * @ingroup rpu_registers 758 * @defgroup RPU_PTG_BUS0 RPU_PTG_BUS0 759 * @brief PTG_BUS0 RPU Register. 760 * @{ 761 */ 762 #define MXC_F_RPU_PTG_BUS0_ACCESS_POS 0 /**< PTG_BUS0_ACCESS Position */ 763 #define MXC_F_RPU_PTG_BUS0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_PTG_BUS0_ACCESS_POS)) /**< PTG_BUS0_ACCESS Mask */ 764 765 /**@} end of group RPU_PTG_BUS0_Register */ 766 767 /** 768 * @ingroup rpu_registers 769 * @defgroup RPU_OWM RPU_OWM 770 * @brief OWM RPU Register. 771 * @{ 772 */ 773 #define MXC_F_RPU_OWM_ACCESS_POS 0 /**< OWM_ACCESS Position */ 774 #define MXC_F_RPU_OWM_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_OWM_ACCESS_POS)) /**< OWM_ACCESS Mask */ 775 776 /**@} end of group RPU_OWM_Register */ 777 778 /** 779 * @ingroup rpu_registers 780 * @defgroup RPU_SEMA RPU_SEMA 781 * @brief SEMA RPU Register. 782 * @{ 783 */ 784 #define MXC_F_RPU_SEMA_ACCESS_POS 0 /**< SEMA_ACCESS Position */ 785 #define MXC_F_RPU_SEMA_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SEMA_ACCESS_POS)) /**< SEMA_ACCESS Mask */ 786 787 /**@} end of group RPU_SEMA_Register */ 788 789 /** 790 * @ingroup rpu_registers 791 * @defgroup RPU_UART0 RPU_UART0 792 * @brief UART0 RPU Register. 793 * @{ 794 */ 795 #define MXC_F_RPU_UART0_ACCESS_POS 0 /**< UART0_ACCESS Position */ 796 #define MXC_F_RPU_UART0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_UART0_ACCESS_POS)) /**< UART0_ACCESS Mask */ 797 798 /**@} end of group RPU_UART0_Register */ 799 800 /** 801 * @ingroup rpu_registers 802 * @defgroup RPU_UART1 RPU_UART1 803 * @brief UART1 RPU Register. 804 * @{ 805 */ 806 #define MXC_F_RPU_UART1_ACCESS_POS 0 /**< UART1_ACCESS Position */ 807 #define MXC_F_RPU_UART1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_UART1_ACCESS_POS)) /**< UART1_ACCESS Mask */ 808 809 /**@} end of group RPU_UART1_Register */ 810 811 /** 812 * @ingroup rpu_registers 813 * @defgroup RPU_UART2 RPU_UART2 814 * @brief UART2 RPU Register. 815 * @{ 816 */ 817 #define MXC_F_RPU_UART2_ACCESS_POS 0 /**< UART2_ACCESS Position */ 818 #define MXC_F_RPU_UART2_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_UART2_ACCESS_POS)) /**< UART2_ACCESS Mask */ 819 820 /**@} end of group RPU_UART2_Register */ 821 822 /** 823 * @ingroup rpu_registers 824 * @defgroup RPU_SPI1 RPU_SPI1 825 * @brief SPI1 RPU Register. 826 * @{ 827 */ 828 #define MXC_F_RPU_SPI1_ACCESS_POS 0 /**< SPI1_ACCESS Position */ 829 #define MXC_F_RPU_SPI1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPI1_ACCESS_POS)) /**< SPI1_ACCESS Mask */ 830 831 /**@} end of group RPU_SPI1_Register */ 832 833 /** 834 * @ingroup rpu_registers 835 * @defgroup RPU_SPI2 RPU_SPI2 836 * @brief SPI2 RPU Register. 837 * @{ 838 */ 839 #define MXC_F_RPU_SPI2_ACCESS_POS 0 /**< SPI2_ACCESS Position */ 840 #define MXC_F_RPU_SPI2_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPI2_ACCESS_POS)) /**< SPI2_ACCESS Mask */ 841 842 /**@} end of group RPU_SPI2_Register */ 843 844 /** 845 * @ingroup rpu_registers 846 * @defgroup RPU_AUDIO RPU_AUDIO 847 * @brief AUDIO RPU Register. 848 * @{ 849 */ 850 #define MXC_F_RPU_AUDIO_ACCESS_POS 0 /**< AUDIO_ACCESS Position */ 851 #define MXC_F_RPU_AUDIO_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_AUDIO_ACCESS_POS)) /**< AUDIO_ACCESS Mask */ 852 853 /**@} end of group RPU_AUDIO_Register */ 854 855 /** 856 * @ingroup rpu_registers 857 * @defgroup RPU_TRNG RPU_TRNG 858 * @brief TRNG RPU Register. 859 * @{ 860 */ 861 #define MXC_F_RPU_TRNG_ACCESS_POS 0 /**< TRNG_ACCESS Position */ 862 #define MXC_F_RPU_TRNG_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_TRNG_ACCESS_POS)) /**< TRNG_ACCESS Mask */ 863 864 /**@} end of group RPU_TRNG_Register */ 865 866 /** 867 * @ingroup rpu_registers 868 * @defgroup RPU_BTLE RPU_BTLE 869 * @brief BTLE RPU Register. 870 * @{ 871 */ 872 #define MXC_F_RPU_BTLE_ACCESS_POS 0 /**< BTLE_ACCESS Position */ 873 #define MXC_F_RPU_BTLE_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_BTLE_ACCESS_POS)) /**< BTLE_ACCESS Mask */ 874 875 /**@} end of group RPU_BTLE_Register */ 876 877 /** 878 * @ingroup rpu_registers 879 * @defgroup RPU_USBHS RPU_USBHS 880 * @brief USBHS RPU Register. 881 * @{ 882 */ 883 #define MXC_F_RPU_USBHS_ACCESS_POS 0 /**< USBHS_ACCESS Position */ 884 #define MXC_F_RPU_USBHS_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_USBHS_ACCESS_POS)) /**< USBHS_ACCESS Mask */ 885 886 /**@} end of group RPU_USBHS_Register */ 887 888 /** 889 * @ingroup rpu_registers 890 * @defgroup RPU_SDIO RPU_SDIO 891 * @brief SDIO/SDHC Target RPU Register. 892 * @{ 893 */ 894 #define MXC_F_RPU_SDIO_ACCESS_POS 0 /**< SDIO_ACCESS Position */ 895 #define MXC_F_RPU_SDIO_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SDIO_ACCESS_POS)) /**< SDIO_ACCESS Mask */ 896 897 /**@} end of group RPU_SDIO_Register */ 898 899 /** 900 * @ingroup rpu_registers 901 * @defgroup RPU_SPIXFM_FIFO RPU_SPIXFM_FIFO 902 * @brief SPIXFM_FIFO RPU Register. 903 * @{ 904 */ 905 #define MXC_F_RPU_SPIXFM_FIFO_ACCESS_POS 0 /**< SPIXFM_FIFO_ACCESS Position */ 906 #define MXC_F_RPU_SPIXFM_FIFO_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPIXFM_FIFO_ACCESS_POS)) /**< SPIXFM_FIFO_ACCESS Mask */ 907 908 /**@} end of group RPU_SPIXFM_FIFO_Register */ 909 910 /** 911 * @ingroup rpu_registers 912 * @defgroup RPU_SPI0 RPU_SPI0 913 * @brief SPI0 RPU Register. 914 * @{ 915 */ 916 #define MXC_F_RPU_SPI0_ACCESS_POS 0 /**< SPI0_ACCESS Position */ 917 #define MXC_F_RPU_SPI0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SPI0_ACCESS_POS)) /**< SPI0_ACCESS Mask */ 918 919 /**@} end of group RPU_SPI0_Register */ 920 921 /** 922 * @ingroup rpu_registers 923 * @defgroup RPU_SYSRAM0 RPU_SYSRAM0 924 * @brief SYSRAM0 RPU Register. 925 * @{ 926 */ 927 #define MXC_F_RPU_SYSRAM0_ACCESS_POS 0 /**< SYSRAM0_ACCESS Position */ 928 #define MXC_F_RPU_SYSRAM0_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM0_ACCESS_POS)) /**< SYSRAM0_ACCESS Mask */ 929 930 /**@} end of group RPU_SYSRAM0_Register */ 931 932 /** 933 * @ingroup rpu_registers 934 * @defgroup RPU_SYSRAM1 RPU_SYSRAM1 935 * @brief SYSRAM1 RPU Register. 936 * @{ 937 */ 938 #define MXC_F_RPU_SYSRAM1_ACCESS_POS 0 /**< SYSRAM1_ACCESS Position */ 939 #define MXC_F_RPU_SYSRAM1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM1_ACCESS_POS)) /**< SYSRAM1_ACCESS Mask */ 940 941 /**@} end of group RPU_SYSRAM1_Register */ 942 943 /** 944 * @ingroup rpu_registers 945 * @defgroup RPU_SYSRAM2 RPU_SYSRAM2 946 * @brief SYSRAM2 RPU Register. 947 * @{ 948 */ 949 #define MXC_F_RPU_SYSRAM2_ACCESS_POS 0 /**< SYSRAM2_ACCESS Position */ 950 #define MXC_F_RPU_SYSRAM2_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM2_ACCESS_POS)) /**< SYSRAM2_ACCESS Mask */ 951 952 /**@} end of group RPU_SYSRAM2_Register */ 953 954 /** 955 * @ingroup rpu_registers 956 * @defgroup RPU_SYSRAM3 RPU_SYSRAM3 957 * @brief SYSRAM3 RPU Register. 958 * @{ 959 */ 960 #define MXC_F_RPU_SYSRAM3_ACCESS_POS 0 /**< SYSRAM3_ACCESS Position */ 961 #define MXC_F_RPU_SYSRAM3_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM3_ACCESS_POS)) /**< SYSRAM3_ACCESS Mask */ 962 963 /**@} end of group RPU_SYSRAM3_Register */ 964 965 /** 966 * @ingroup rpu_registers 967 * @defgroup RPU_SYSRAM4 RPU_SYSRAM4 968 * @brief SYSRAM4 RPU Register. 969 * @{ 970 */ 971 #define MXC_F_RPU_SYSRAM4_ACCESS_POS 0 /**< SYSRAM4_ACCESS Position */ 972 #define MXC_F_RPU_SYSRAM4_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM4_ACCESS_POS)) /**< SYSRAM4_ACCESS Mask */ 973 974 /**@} end of group RPU_SYSRAM4_Register */ 975 976 /** 977 * @ingroup rpu_registers 978 * @defgroup RPU_SYSRAM5 RPU_SYSRAM5 979 * @brief SYSRAM5 RPU Register. 980 * @{ 981 */ 982 #define MXC_F_RPU_SYSRAM5_ACCESS_POS 0 /**< SYSRAM5_ACCESS Position */ 983 #define MXC_F_RPU_SYSRAM5_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM5_ACCESS_POS)) /**< SYSRAM5_ACCESS Mask */ 984 985 /**@} end of group RPU_SYSRAM5_Register */ 986 987 /** 988 * @ingroup rpu_registers 989 * @defgroup RPU_SYSRAM6_11 RPU_SYSRAM6_11 990 * @brief SYSRAM6-11 RPU Register. 991 * @{ 992 */ 993 #define MXC_F_RPU_SYSRAM6_11_ACCESS_POS 0 /**< SYSRAM6_11_ACCESS Position */ 994 #define MXC_F_RPU_SYSRAM6_11_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_SYSRAM6_11_ACCESS_POS)) /**< SYSRAM6_11_ACCESS Mask */ 995 996 /**@} end of group RPU_SYSRAM6_11_Register */ 997 998 /** 999 * @ingroup rpu_registers 1000 * @defgroup RPU_I2C0_BUS1 RPU_I2C0_BUS1 1001 * @brief I2C0_BUS1 RPU Register. 1002 * @{ 1003 */ 1004 #define MXC_F_RPU_I2C0_BUS1_ACCESS_POS 0 /**< I2C0_BUS1_ACCESS Position */ 1005 #define MXC_F_RPU_I2C0_BUS1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_I2C0_BUS1_ACCESS_POS)) /**< I2C0_BUS1_ACCESS Mask */ 1006 1007 /**@} end of group RPU_I2C0_BUS1_Register */ 1008 1009 /** 1010 * @ingroup rpu_registers 1011 * @defgroup RPU_I2C1_BUS1 RPU_I2C1_BUS1 1012 * @brief I2C1_BUS1 RPU Register. 1013 * @{ 1014 */ 1015 #define MXC_F_RPU_I2C1_BUS1_ACCESS_POS 0 /**< I2C1_BUS1_ACCESS Position */ 1016 #define MXC_F_RPU_I2C1_BUS1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_I2C1_BUS1_ACCESS_POS)) /**< I2C1_BUS1_ACCESS Mask */ 1017 1018 /**@} end of group RPU_I2C1_BUS1_Register */ 1019 1020 /** 1021 * @ingroup rpu_registers 1022 * @defgroup RPU_I2C2_BUS1 RPU_I2C2_BUS1 1023 * @brief I2C2_BU1 RPU Register. 1024 * @{ 1025 */ 1026 #define MXC_F_RPU_I2C2_BUS1_ACCESS_POS 0 /**< I2C2_BUS1_ACCESS Position */ 1027 #define MXC_F_RPU_I2C2_BUS1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_I2C2_BUS1_ACCESS_POS)) /**< I2C2_BUS1_ACCESS Mask */ 1028 1029 /**@} end of group RPU_I2C2_BUS1_Register */ 1030 1031 /** 1032 * @ingroup rpu_registers 1033 * @defgroup RPU_PTG_BUS1 RPU_PTG_BUS1 1034 * @brief PTG_BUS1 RPU Register. 1035 * @{ 1036 */ 1037 #define MXC_F_RPU_PTG_BUS1_ACCESS_POS 0 /**< PTG_BUS1_ACCESS Position */ 1038 #define MXC_F_RPU_PTG_BUS1_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_RPU_PTG_BUS1_ACCESS_POS)) /**< PTG_BUS1_ACCESS Mask */ 1039 1040 /**@} end of group RPU_PTG_BUS1_Register */ 1041 1042 #ifdef __cplusplus 1043 } 1044 #endif 1045 1046 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_RPU_REGS_H_ 1047
