1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 /* **** Includes **** */
22 #include <string.h>
23 #include "mxc_device.h"
24 #include "mxc_assert.h"
25 #include "mxc_pins.h"
26 #include "mxc_sys.h"
27 #include "cameraif.h"
28 #include "cameraif_reva.h"
29
30 /* **** Definitions **** */
31
32 /* **** Globals **** */
33
34 /* **** Functions **** */
35
MXC_PCIF_Init(mxc_pcif_gpio_datawidth_t gpioDataWidth)36 int MXC_PCIF_Init(mxc_pcif_gpio_datawidth_t gpioDataWidth)
37 {
38 if ((gpioDataWidth != MXC_PCIF_GPIO_DATAWIDTH_8_BIT) &&
39 (gpioDataWidth != MXC_PCIF_GPIO_DATAWIDTH_10_BIT) &&
40 (gpioDataWidth != MXC_PCIF_GPIO_DATAWIDTH_12_BIT)) {
41 return E_BAD_PARAM;
42 }
43
44 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_PCIF);
45
46 switch (gpioDataWidth) {
47 case MXC_PCIF_DATAWIDTH_8_BIT:
48 MXC_GPIO_Config(&gpio_cfg_pcif_P0_BITS_0_7);
49 break;
50
51 case MXC_PCIF_DATAWIDTH_10_BIT:
52 MXC_GPIO_Config(&gpio_cfg_pcif_P0_BITS_0_7);
53 MXC_GPIO_Config(&gpio_cfg_pcif_P0_BITS_8);
54 MXC_GPIO_Config(&gpio_cfg_pcif_P1_BITS_9);
55 break;
56
57 case MXC_PCIF_DATAWIDTH_12_BIT:
58 MXC_GPIO_Config(&gpio_cfg_pcif_P0_BITS_0_7);
59 MXC_GPIO_Config(&gpio_cfg_pcif_P0_BITS_8);
60 MXC_GPIO_Config(&gpio_cfg_pcif_P1_BITS_9);
61 MXC_GPIO_Config(&gpio_cfg_pcif_P1_BITS_10_11);
62 break;
63 }
64
65 MXC_GPIO_Config(&gpio_cfg_pcif_hsync);
66 MXC_GPIO_Config(&gpio_cfg_pcif_vsync);
67 MXC_GPIO_Config(&gpio_cfg_pcif_pclk);
68 MXC_GPIO_Config(&gpio_cfg_pcif_pwrdwn);
69
70 MXC_GPIO_OutClr(gpio_cfg_pcif_pwrdwn.port, gpio_cfg_pcif_pwrdwn.mask);
71
72 return E_NO_ERROR;
73 }
74
MXC_PCIF_SetDatawidth(mxc_pcif_datawidth_t datawidth)75 void MXC_PCIF_SetDatawidth(mxc_pcif_datawidth_t datawidth)
76 {
77 MXC_PCIF_RevA_SetDatawidth((mxc_cameraif_reva_regs_t *)MXC_PCIF,
78 (mxc_pcif_reva_datawith_t)datawidth);
79 }
80
MXC_PCIF_SetTimingSel(mxc_pcif_timingsel_t timingsel)81 void MXC_PCIF_SetTimingSel(mxc_pcif_timingsel_t timingsel)
82 {
83 MXC_PCIF_RevA_SetTimingSel((mxc_cameraif_reva_regs_t *)MXC_PCIF, timingsel);
84 }
85
MXC_PCIF_SetThreshold(int fifo_thrsh)86 void MXC_PCIF_SetThreshold(int fifo_thrsh)
87 {
88 MXC_PCIF_RevA_SetThreshold((mxc_cameraif_reva_regs_t *)MXC_PCIF, fifo_thrsh);
89 }
90
MXC_PCIF_EnableInt(uint32_t flags)91 void MXC_PCIF_EnableInt(uint32_t flags)
92 {
93 MXC_PCIF_RevA_EnableInt((mxc_cameraif_reva_regs_t *)MXC_PCIF, flags);
94 }
95
MXC_PCIF_DisableInt(uint32_t flags)96 void MXC_PCIF_DisableInt(uint32_t flags)
97 {
98 MXC_PCIF_RevA_DisableInt((mxc_cameraif_reva_regs_t *)MXC_PCIF, flags);
99 }
100
MXC_PCIF_Start(mxc_pcif_readmode_t readmode)101 void MXC_PCIF_Start(mxc_pcif_readmode_t readmode)
102 {
103 MXC_PCIF_RevA_Start((mxc_cameraif_reva_regs_t *)MXC_PCIF, readmode);
104 }
105
MXC_PCIF_Stop(void)106 void MXC_PCIF_Stop(void)
107 {
108 MXC_PCIF_RevA_Stop((mxc_cameraif_reva_regs_t *)MXC_PCIF);
109 }
110
MXC_PCIF_GetData(void)111 unsigned int MXC_PCIF_GetData(void)
112 {
113 return MXC_PCIF_RevA_GetData((mxc_cameraif_reva_regs_t *)MXC_PCIF);
114 }
115
116 /**@} end of group cameraif */
117
