1 /****************************************************************************** 2 * 3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 4 * Analog Devices, Inc.), 5 * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software 6 * is proprietary to Analog Devices, Inc. and its licensors. 7 * 8 * Licensed under the Apache License, Version 2.0 (the "License"); 9 * you may not use this file except in compliance with the License. 10 * You may obtain a copy of the License at 11 * 12 * http://www.apache.org/licenses/LICENSE-2.0 13 * 14 * Unless required by applicable law or agreed to in writing, software 15 * distributed under the License is distributed on an "AS IS" BASIS, 16 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 17 * See the License for the specific language governing permissions and 18 * limitations under the License. 19 * 20 ******************************************************************************/ 21 22 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_MAX32572_H_ 23 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_MAX32572_H_ 24 25 #ifndef TARGET_NUM 26 #define TARGET_NUM 32572 27 #endif 28 29 #define MXC_NUMCORES 2 30 31 #include <stdint.h> 32 33 #ifndef FALSE 34 #define FALSE (0) 35 #endif 36 37 #ifndef TRUE 38 #define TRUE (1) 39 #endif 40 41 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ 42 #if defined(__GNUC__) 43 #ifndef __weak 44 #define __weak __attribute__((weak)) 45 #endif 46 47 #elif defined(__CC_ARM) 48 49 #define inline __inline 50 #pragma anon_unions 51 52 #endif 53 54 // clang-format off 55 typedef enum { 56 #ifndef __riscv // not RISC-V 57 NonMaskableInt_IRQn = -14, 58 HardFault_IRQn = -13, 59 MemoryManagement_IRQn = -12, 60 BusFault_IRQn = -11, 61 UsageFault_IRQn = -10, 62 SVCall_IRQn = -5, 63 DebugMonitor_IRQn = -4, 64 PendSV_IRQn = -2, 65 SysTick_IRQn = -1, 66 67 /* Device-specific interrupt sources (external to ARM core) */ 68 /* table entry number */ 69 /* |||| */ 70 /* |||| table offset address */ 71 /* vvvv vvvvvv */ 72 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ 73 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ 74 USB_IRQn, /* 0x12 0x0048 18: USB */ 75 RTC_IRQn, /* 0x13 0x004C 19: RTC */ 76 TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */ 77 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ 78 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ 79 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ 80 TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */ 81 TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 */ 82 TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */ 83 SC0_IRQn, /* 0x1B 0x006C 27: Smart Card 0 */ 84 RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */ 85 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ 86 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ 87 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ 88 SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */ 89 SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */ 90 RSV18_IRQn, /* 0x22 0x0088 34: Reserved */ 91 SKB_IRQn, /* 0x23 0x008C 35: Secure Keypad */ 92 ADC_IRQn, /* 0x24 0x0090 36: ADC */ 93 RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ 94 MSRADC_IRQn, /* 0x26 0x0098 38: Magstripe DSP */ 95 RSV23_IRQn, /* 0x27 0x009C 39: Reserved */ 96 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ 97 GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO1 */ 98 RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */ 99 CRYPTO_IRQn, /* 0x2B 0x00AC 43: Crypto */ 100 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ 101 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ 102 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ 103 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ 104 RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */ 105 RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */ 106 UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */ 107 RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */ 108 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ 109 SC1_IRQn, /* 0x35 0x00D4 53: Smart Card 1 */ 110 SPIXFC_IRQn, /* 0x36 0x00D8 54: SPI execute in place */ 111 RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */ 112 RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */ 113 RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */ 114 RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */ 115 RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */ 116 RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */ 117 RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */ 118 RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */ 119 RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ 120 RSV48_IRQn, /* 0x40 0x0100 64: Reserved */ 121 RSV49_IRQn, /* 0x41 0x0104 65: Reserved */ 122 RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ 123 RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ 124 RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ 125 RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ 126 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ 127 RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ 128 SPI3_IRQn, /* 0x48 0x0120 72: SPI3 */ 129 WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */ 130 RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */ 131 PT_IRQn, /* 0x4B 0x012C 75: Pulse train */ 132 RSV60_IRQn, /* 0x4C 0x0130 76: Reserved */ 133 RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ 134 RSV62_IRQn, /* 0x4E 0x0138 78: Reserved */ 135 RISCV_IRQn, /* 0x4F 0x013C 79: RISCV */ 136 RSV64_IRQn, /* 0x50 0x0140 80: Reserved */ 137 RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ 138 RSV66_IRQn, /* 0x52 0x0148 82: Reserved */ 139 RSV67_IRQn, /* 0x53 0x014C 83: Reserved */ 140 DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */ 141 DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */ 142 DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */ 143 DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */ 144 DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */ 145 DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */ 146 DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */ 147 DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */ 148 DMA12_IRQn, /* 0x5C 0x0170 92: DMA12 */ 149 DMA13_IRQn, /* 0x5D 0x0174 93: DMA13 */ 150 DMA14_IRQn, /* 0x5E 0x0178 94: DMA14 */ 151 DMA15_IRQn, /* 0x5F 0x017C 95: DMA15 */ 152 USBDMA_IRQn, /* 0x60 0x0180 96: USB DMA */ 153 RSV81_IRQn, /* 0x61 0x0184 97: Reserved */ 154 ECC_IRQn, /* 0x62 0x0188 98: Error Correction */ 155 RSV83_IRQn, /* 0x63 0x018C 99: Reserved */ 156 RSV84_IRQn, /* 0x64 0x0190 100: Reserved */ 157 SCA_IRQn, /* 0x65 0x0194 101: SCA Crypto Accelerator */ 158 RSV86_IRQn, /* 0x66 0x0198 102: Reserved */ 159 RSV87_IRQn, /* 0x67 0x019C 103: Reserved */ 160 UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */ 161 RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */ 162 RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */ 163 RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */ 164 RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */ 165 HTMR0_IRQn, /* 0x6D 0x01B4 109: HTimer0 */ 166 HTMR1_IRQn, /* 0x6E 0x01B8 110: HTimer1 */ 167 RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */ 168 RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */ 169 RSV97_IRQn, /* 0x71 0x01C4 113: Reserved */ 170 RSV98_IRQn, /* 0x72 0x01C8 114: Reserved */ 171 RSV99_IRQn, /* 0x73 0x01CC 115: Reserved */ 172 RSV100_IRQn, /* 0x74 0x01D0 116: Reserved */ 173 RSV101_IRQn, /* 0x75 0x01D4 117: Reserved */ 174 RSV102_IRQn, /* 0x76 0x01D8 118: Reserved */ 175 RSV103_IRQn, /* 0x77 0x01DC 119: Reserved */ 176 RSV104_IRQn, /* 0x78 0x01E0 120: Reserved */ 177 RSV105_IRQn, /* 0x79 0x01E4 121: Reserved */ 178 RSV106_IRQn, /* 0x7A 0x01E8 122: Reserved */ 179 RSV107_IRQn, /* 0x7B 0x01EC 123: Reserved */ 180 RSV108_IRQn, /* 0x7C 0x01F0 124: Reserved */ 181 RSV109_IRQn, /* 0x7D 0x01F4 125: Reserved */ 182 RSV110_IRQn, /* 0x7E 0x01F8 126: Reserved */ 183 RSV111_IRQn, /* 0x7F 0x01FC 127: Reserved */ 184 #else // __riscv 185 HardFault_IRQn = 3, /* 0x03, 3 HardFault */ 186 CM4_IRQn = 4, /* 0x04, 4 Cortex-M4 (CPU0) */ 187 RSV5_IRQn, /* 0x05, 5 Reserved */ 188 RSV6_IRQn, /* 0x06, 6 Reserved */ 189 WDT0_IRQn, /* 0x07, 7 Watchdog 0 */ 190 WDT1_IRQn, /* 0x08, 8 Watchdog 1 */ 191 RTC_IRQn, /* 0x09, 9 RTC */ 192 MSRADC_IRQn, /* 0x0A, 10 Magstripe DSP */ 193 RSV11_IRQn, /* 0x0B, 11 Reserved */ 194 TMR0_IRQn, /* 0x0C, 12 Timer 0 */ 195 TMR1_IRQn, /* 0x0D, 13 Timer 1 */ 196 TMR2_IRQn, /* 0x0E, 14 Timer 2 */ 197 TMR3_IRQn, /* 0x0F, 15 Timer 3 */ 198 TMR4_IRQn, /* 0x10, 16 Timer 4 */ 199 TMR5_IRQn, /* 0x11, 17 Timer 5 */ 200 RSV18_IRQn, /* 0x12, 18 Reserved */ 201 RSV19_IRQn, /* 0x13, 19 Reserved */ 202 GPIO0_IRQn, /* 0x14, 20 GPIO0 */ 203 GPIO1_IRQn, /* 0x15, 21 GPIO1 */ 204 RSV22_IRQn, /* 0x16, 22 Reserved */ 205 RSV23_IRQn, /* 0x17, 23 Reserved */ 206 I2C0_IRQn, /* 0x18, 24 I2C0 */ 207 SPI0_IRQn, /* 0x19, 25 SPI0 */ 208 UART0_IRQn, /* 0x1A, 26 UART0 */ 209 I2C1_IRQn, /* 0x1B, 27 UART1 */ 210 SPI1_IRQn, /* 0x1C, 28 SPI1 */ 211 UART1_IRQn, /* 0x1D, 29 UART1 */ 212 RSV30_IRQn, /* 0x1E, 30 Reserved */ 213 RSV31_IRQn, /* 0x1F, 31 Reserved */ 214 UART2_IRQn, /* 0x20, 32 UART2 */ 215 SPI3_IRQn, /* 0x21, 33 SPI3 */ 216 UART3_IRQn, /* 0x22, 34 UART3 */ 217 RSV35_IRQn, /* 0x23, 35 Reserved */ 218 RSV36_IRQn, /* 0x24, 36 Reserved */ 219 RSV37_IRQn, /* 0x25, 37 Reserved */ 220 TRNG_IRQn, /* 0x26, 38 TRNG */ 221 CRYPTO_IRQn, /* 0x27, 39 CTB */ 222 SCA_IRQn, /* 0x28, 40 SCA Accelerator */ 223 SC0_IRQn, /* 0x29, 41 SC0 */ 224 SC1_IRQn, /* 0x2A, 42 SC1 */ 225 SKBD_IRQn, /* 0x2B, 43 SKBD */ 226 ADC_IRQn, /* 0x2C, 44 ADC */ 227 PT_IRQn, /* 0x2D, 45 Pulse Train */ 228 RSV46_IRQn, /* 0x2E, 46 Reserved */ 229 RSV47_IRQn, /* 0x2F, 47 Reserved */ 230 RSV48_IRQn, /* 0x30, 48 Reserved */ 231 RSV49_IRQn, /* 0x31, 49 Reserved */ 232 HTMR0_IRQn, /* 0x32, 50 HTimer 0 */ 233 HTMR1_IRQn, /* 0x33, 51 HTimer 1 */ 234 SPIXIP_IRQn, /* 0x34, 52 SPI XIP */ 235 RSV53_IRQn, /* 0x35, 53 Reserved */ 236 RSV54_IRQn, /* 0x36, 54 Reserved */ 237 DMA0_IRQn, /* 0x37, 55 DMA0 */ 238 DMA1_IRQn, /* 0x38, 56 DMA1 */ 239 DMA2_IRQn, /* 0x39, 57 DMA2 */ 240 DMA3_IRQn, /* 0x3A, 58 DMA3 */ 241 DMA4_IRQn, /* 0x3B, 59 DMA4 */ 242 DMA5_IRQn, /* 0x3C, 60 DMA5 */ 243 DMA6_IRQn, /* 0x3D, 61 DMA6 */ 244 DMA7_IRQn, /* 0x3E, 62 DMA7 */ 245 DMA8_15_IRQn, /* 0x3F, 63 DMA 8-15 */ 246 #endif // __riscv 247 MXC_IRQ_EXT_COUNT 248 } IRQn_Type; 249 250 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) 251 252 /* ================================================================================ */ 253 /* ================ Processor and Core Peripheral Section ================ */ 254 /* ================================================================================ */ 255 256 #ifndef __riscv 257 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ 258 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ 259 #define __MPU_PRESENT 1 /*!< MPU present or not */ 260 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 261 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 262 #define __FPU_PRESENT 1 /*!< FPU present or not */ 263 264 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */ 265 266 #else // __riscv 267 268 #include <core_rv32.h> 269 270 #endif // __riscv 271 272 #include "system_max32572.h" /*!< System Header */ 273 274 /* ================================================================================ */ 275 /* ================== Device Specific Memory Section ================== */ 276 /* ================================================================================ */ 277 278 #define MXC_ROM0_MEM_BASE 0x00000000UL 279 #define MXC_ROM0_MEM_SIZE 0x00020000UL 280 #define MXC_ROM1_MEM_BASE 0x2006C000UL 281 #define MXC_ROM1_MEM_SIZE 0x00008000UL 282 #define MXC_ROM_MEM_BASE MXC_ROM0_MEM_BASE 283 #define MXC_ROM_MEM_SIZE MXC_ROM0_MEM_SIZE 284 #define MXC_XIP_MEM_BASE 0x08000000UL 285 #define MXC_XIP_MEM_SIZE 0x08000000UL 286 #define MXC_XIP_SECTOR_SIZE 0x00001000UL 287 #define MXC_SRAM_MEM_BASE 0x20000000UL 288 #define MXC_SRAM_MEM_SIZE 0x0006C000UL 289 #define MXC_OTP_MEM_BASE 0x400C0000UL 290 #define MXC_OTP_MEM_SIZE 0x00000800UL 291 292 /* ================================================================================ */ 293 /* ================ Device Specific Peripheral Section ================ */ 294 /* ================================================================================ */ 295 296 /* 297 Base addresses and configuration settings for all MAX32572 peripheral modules. 298 */ 299 300 /******************************************************************************/ 301 /* Global control */ 302 #define MXC_BASE_GCR ((uint32_t)0x40000000UL) 303 #define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR) 304 305 /******************************************************************************/ 306 /* Non-battery backed SI Registers */ 307 #define MXC_BASE_SIR ((uint32_t)0x40000400UL) 308 #define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR) 309 310 /******************************************************************************/ 311 /* Non-battery backed Function Control */ 312 #define MXC_BASE_FCR ((uint32_t)0x40000800UL) 313 #define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR) 314 315 /******************************************************************************/ 316 /* Trust Protection Unit */ 317 #define MXC_BASE_CTB ((uint32_t)0x40001000UL) 318 #define MXC_CTB ((mxc_ctb_regs_t *)MXC_BASE_CTB) 319 320 /******************************************************************************/ 321 /* Watchdog */ 322 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) 323 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) 324 #define MXC_BASE_WDT1 ((uint32_t)0x40003400UL) 325 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) 326 327 /******************************************************************************/ 328 /* Security Monitor */ 329 #define MXC_BASE_SMON ((uint32_t)0x40004000UL) 330 #define MXC_SMON ((mxc_smon_regs_t *)MXC_BASE_SMON) 331 332 /******************************************************************************/ 333 /* AES Keys */ 334 #define MXC_BASE_AESKEYS ((uint32_t)0x40005000UL) 335 #define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS) 336 337 /******************************************************************************/ 338 /* Trim System Initalization Register */ 339 #define MXC_BASE_TRIMSIR ((uint32_t)0x40005400UL) 340 #define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR) 341 342 /******************************************************************************/ 343 /* Real Time Clock */ 344 #define MXC_BASE_RTC ((uint32_t)0x40006000UL) 345 #define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC) 346 347 /******************************************************************************/ 348 /* Power Sequencer */ 349 #define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) 350 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) 351 352 /******************************************************************************/ 353 /* Power Sequencer */ 354 #define MXC_BASE_MCR ((uint32_t)0x40006C00UL) 355 #define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR) 356 357 /******************************************************************************/ 358 /* GPIO */ 359 #define MXC_CFG_GPIO_INSTANCES (2) 360 #define MXC_CFG_GPIO_PINS_PORT (32) 361 362 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) 363 #define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0) 364 #define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL) 365 #define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1) 366 367 #define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : -1) 368 369 #define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : 0) 370 371 #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (i) == 1 ? GPIO1_IRQn : 0) 372 373 /******************************************************************************/ 374 /* Magstripe Reader ADC */ 375 #define MXC_BASE_MSRADC ((uint32_t)0x4012B000UL) 376 #define MXC_MSRADC ((mxc_msradc_regs_t *)MXC_BASE_MSRADC) 377 378 /******************************************************************************/ 379 #define SEC(s) (((uint32_t)s) * 1000000UL) 380 #define MSEC(ms) (ms * 1000UL) 381 #define USEC(us) (us) 382 /* Timer */ 383 #define MXC_CFG_TMR_INSTANCES (6) 384 385 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) 386 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) 387 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) 388 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) 389 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) 390 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) 391 #define MXC_BASE_TMR3 ((uint32_t)0x40013000UL) 392 #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) 393 #define MXC_BASE_TMR4 ((uint32_t)0x40014000UL) 394 #define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) 395 #define MXC_BASE_TMR5 ((uint32_t)0x40115000UL) 396 #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) 397 398 #define MXC_TMR_GET_IRQ(i) \ 399 (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ 400 (i) == 1 ? TMR1_IRQn : \ 401 (i) == 2 ? TMR2_IRQn : \ 402 (i) == 3 ? TMR3_IRQn : \ 403 (i) == 4 ? TMR4_IRQn : \ 404 (i) == 5 ? TMR5_IRQn : \ 405 0) 406 407 #define MXC_TMR_GET_BASE(i) \ 408 ((i) == 0 ? MXC_BASE_TMR0 : \ 409 (i) == 1 ? MXC_BASE_TMR1 : \ 410 (i) == 2 ? MXC_BASE_TMR2 : \ 411 (i) == 3 ? MXC_BASE_TMR3 : \ 412 (i) == 4 ? MXC_BASE_TMR4 : \ 413 (i) == 5 ? MXC_BASE_TMR5 : \ 414 0) 415 416 #define MXC_TMR_GET_TMR(i) \ 417 ((i) == 0 ? MXC_TMR0 : \ 418 (i) == 1 ? MXC_TMR1 : \ 419 (i) == 2 ? MXC_TMR2 : \ 420 (i) == 3 ? MXC_TMR3 : \ 421 (i) == 4 ? MXC_TMR4 : \ 422 (i) == 5 ? MXC_TMR5 : \ 423 0) 424 425 #define MXC_TMR_GET_IDX(p) \ 426 ((p) == MXC_TMR0 ? 0 : \ 427 (p) == MXC_TMR1 ? 1 : \ 428 (p) == MXC_TMR2 ? 2 : \ 429 (p) == MXC_TMR3 ? 3 : \ 430 (p) == MXC_TMR4 ? 4 : \ 431 (p) == MXC_TMR5 ? 5 : \ 432 -1) 433 434 /******************************************************************************/ 435 /* High Speed Timer */ 436 #define MXC_BASE_HTMR0 ((uint32_t)0x4001B000UL) 437 #define MXC_HTMR0 ((mxc_htmr_regs_t *)MXC_BASE_HTMR0) 438 #define MXC_BASE_HTMR1 ((uint32_t)0x4001C000UL) 439 #define MXC_HTMR1 ((mxc_htmr_regs_t *)MXC_BASE_HTMR1) 440 441 /******************************************************************************/ 442 /* I2C */ 443 #define MXC_I2C_INSTANCES (2) 444 #define MXC_I2C_FIFO_DEPTH (8) 445 446 #define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) 447 #define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0) 448 #define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) 449 #define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1) 450 451 #define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : 0) 452 453 #define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : 0) 454 455 #define MXC_I2C_GET_TMR(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : 0) 456 457 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : -1) 458 459 /******************************************************************************/ 460 /* SPI Execute in Place Master */ 461 #define MXC_BASE_SPIXFM ((uint32_t)0x40026000UL) 462 #define MXC_SPIXFM ((mxc_spixfm_regs_t *)MXC_BASE_SPIXFM) 463 464 /******************************************************************************/ 465 /* SPI Execute in Place Master Controller */ 466 #define MXC_CFG_SPIXFC_FIFO_DEPTH (16) 467 468 #define MXC_BASE_SPIXFC ((uint32_t)0x40027000UL) 469 #define MXC_SPIXFC ((mxc_spixfc_regs_t *)MXC_BASE_SPIXFC) 470 #define MXC_BASE_SPIXFC_FIFO ((uint32_t)0x400BC000UL) 471 #define MXC_SPIXFC_FIFO ((mxc_spixfc_fifo_regs_t *)MXC_BASE_SPIXFC_FIFO) 472 473 /******************************************************************************/ 474 /* DMA */ 475 #define MXC_DMA_CHANNELS (16) 476 #define MXC_DMA_INSTANCES (1) 477 478 #define MXC_BASE_DMA ((uint32_t)0x40028000UL) 479 #define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA) 480 481 #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) 482 483 #ifndef __riscv // ARM 484 #define MXC_DMA_CH_GET_IRQ(i) \ 485 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ 486 ((i) == 1) ? DMA1_IRQn : \ 487 ((i) == 2) ? DMA2_IRQn : \ 488 ((i) == 3) ? DMA3_IRQn : \ 489 ((i) == 4) ? DMA4_IRQn : \ 490 ((i) == 5) ? DMA5_IRQn : \ 491 ((i) == 6) ? DMA6_IRQn : \ 492 ((i) == 7) ? DMA7_IRQn : \ 493 ((i) == 8) ? DMA8_IRQn : \ 494 ((i) == 9) ? DMA9_IRQn : \ 495 ((i) == 10) ? DMA10_IRQn : \ 496 ((i) == 11) ? DMA11_IRQn : \ 497 ((i) == 12) ? DMA12_IRQn : \ 498 ((i) == 13) ? DMA13_IRQn : \ 499 ((i) == 14) ? DMA14_IRQn : \ 500 ((i) == 15) ? DMA15_IRQn : \ 501 0)) 502 #else 503 #define MXC_DMA_CH_GET_IRQ(i) \ 504 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ 505 ((i) == 1) ? DMA1_IRQn : \ 506 ((i) == 2) ? DMA2_IRQn : \ 507 ((i) == 3) ? DMA3_IRQn : \ 508 ((i) == 4) ? DMA4_IRQn : \ 509 ((i) == 5) ? DMA5_IRQn : \ 510 ((i) == 6) ? DMA6_IRQn : \ 511 ((i) == 7) ? DMA7_IRQn : \ 512 ((i) == 8) ? DMA8_15_IRQn : \ 513 ((i) == 9) ? DMA8_15_IRQn : \ 514 ((i) == 10) ? DMA8_15_IRQn : \ 515 ((i) == 11) ? DMA8_15_IRQn : \ 516 ((i) == 12) ? DMA8_15_IRQn : \ 517 ((i) == 13) ? DMA8_15_IRQn : \ 518 ((i) == 14) ? DMA8_15_IRQn : \ 519 ((i) == 15) ? DMA8_15_IRQn : \ 520 0)) 521 #endif 522 523 /******************************************************************************/ 524 /* Smart Card */ 525 #define MXC_SC_INSTANCES (2) 526 527 #define MXC_BASE_SC0 ((uint32_t)0x4002C000UL) 528 #define MXC_SC0 ((mxc_scn_regs_t *)MXC_BASE_SC0) 529 #define MXC_BASE_SC1 ((uint32_t)0x4002D000UL) 530 #define MXC_SC1 ((mxc_scn_regs_t *)MXC_BASE_SC1) 531 532 #ifndef __riscv 533 #define MXC_SC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SC0_IRQn : (i) == 1 ? SC1_IRQn : 0) 534 #endif 535 536 #define MXC_SC_GET_BASE(i) ((i) == 0 ? MXC_BASE_SC0 : (i) == 1 ? MXC_BASE_SC1 : 0) 537 538 #define MXC_SC_GET_IDX(p) ((p) == MXC_SC0 ? 0 : (p) == MXC_SC1 ? 1 : -1) 539 540 /******************************************************************************/ 541 /* Instruction Cache XIP Controller */ 542 #define MXC_BASE_SFCC ((uint32_t)0x4002F000UL) 543 #define MXC_SFCC ((mxc_sfcc_regs_t *)MXC_BASE_SFCC) 544 545 /******************************************************************************/ 546 /* Secure Keyboard */ 547 #define MXC_BASE_SKBD ((uint32_t)0x40032000UL) 548 #define MXC_SKBD ((mxc_skbd_regs_t *)MXC_BASE_SKBD) 549 550 /******************************************************************************/ 551 /* ADC */ 552 #define MXC_BASE_ADC ((uint32_t)0x40034000UL) 553 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) 554 #define MXC_ADC_MAX_CLOCK (8000000) // Maximum ADC clock in Hz 555 556 /*******************************************************************************/ 557 /* Pulse Train Generation */ 558 #define MXC_CFG_PT_INSTANCES (8) 559 560 #define MXC_BASE_PTG ((uint32_t)0x4003C000UL) 561 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) 562 #define MXC_BASE_PT0 ((uint32_t)0x4003C020UL) 563 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) 564 #define MXC_BASE_PT1 ((uint32_t)0x4003C040UL) 565 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) 566 #define MXC_BASE_PT2 ((uint32_t)0x4003C060UL) 567 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) 568 #define MXC_BASE_PT3 ((uint32_t)0x4003C080UL) 569 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) 570 #define MXC_BASE_PT4 ((uint32_t)0x4003C0A0UL) 571 #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4) 572 #define MXC_BASE_PT5 ((uint32_t)0x4003C0C0UL) 573 #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5) 574 #define MXC_BASE_PT6 ((uint32_t)0x4003C0E0UL) 575 #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6) 576 #define MXC_BASE_PT7 ((uint32_t)0x4003C100UL) 577 #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7) 578 579 #define MXC_PT_GET_BASE(i) \ 580 ((i) == 0 ? MXC_BASE_PT0 : \ 581 (i) == 1 ? MXC_BASE_PT1 : \ 582 (i) == 2 ? MXC_BASE_PT2 : \ 583 (i) == 3 ? MXC_BASE_PT3 : \ 584 (i) == 4 ? MXC_BASE_PT4 : \ 585 (i) == 5 ? MXC_BASE_PT5 : \ 586 (i) == 6 ? MXC_BASE_PT6 : \ 587 (i) == 7 ? MXC_BASE_PT7 : \ 588 0) 589 590 #define MXC_PT_GET_PT(i) \ 591 ((i) == 0 ? MXC_PT0 : \ 592 (i) == 1 ? MXC_PT1 : \ 593 (i) == 2 ? MXC_PT2 : \ 594 (i) == 3 ? MXC_PT3 : \ 595 (i) == 4 ? MXC_PT4 : \ 596 (i) == 5 ? MXC_PT5 : \ 597 (i) == 6 ? MXC_PT6 : \ 598 (i) == 7 ? MXC_PT7 : \ 599 0) 600 601 #define MXC_PT_GET_IDX(p) \ 602 ((p) == MXC_PT0 ? 0 : \ 603 (p) == MXC_PT1 ? 1 : \ 604 (p) == MXC_PT2 ? 2 : \ 605 (p) == MXC_PT3 ? 3 : \ 606 (p) == MXC_PT4 ? 4 : \ 607 (p) == MXC_PT5 ? 5 : \ 608 (p) == MXC_PT6 ? 6 : \ 609 (p) == MXC_PT7 ? 7 : \ 610 -1) 611 612 /******************************************************************************/ 613 /* Semaphores */ 614 #define MXC_BASE_SEMA ((uint32_t)0x4003E000UL) 615 #define MXC_SEMA ((mxc_sema_regs_t *)MXC_BASE_SEMA) 616 617 /******************************************************************************/ 618 /* OTP Controller */ 619 #define MXC_BASE_OTP ((uint32_t)0x40041000UL) 620 #define MXC_OTP ((mxc_otp_regs_t *)MXC_BASE_OTP) 621 622 /******************************************************************************/ 623 /* UART / Serial Port Interface */ 624 #define MXC_UART_INSTANCES (4) 625 #define MXC_UART_FIFO_DEPTH (8) 626 627 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL) 628 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) 629 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL) 630 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) 631 #define MXC_BASE_UART2 ((uint32_t)0x40044000UL) 632 #define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2) 633 #define MXC_BASE_UART3 ((uint32_t)0x40045000UL) 634 #define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3) 635 636 #define MXC_UART_GET_IRQ(i) \ 637 (IRQn_Type)((i) == 0 ? UART0_IRQn : \ 638 (i) == 1 ? UART1_IRQn : \ 639 (i) == 2 ? UART2_IRQn : \ 640 (i) == 3 ? UART3_IRQn : \ 641 0) 642 643 #define MXC_UART_GET_BASE(i) \ 644 ((i) == 0 ? MXC_BASE_UART0 : \ 645 (i) == 1 ? MXC_BASE_UART1 : \ 646 (i) == 2 ? MXC_BASE_UART2 : \ 647 (i) == 3 ? MXC_BASE_UART3 : \ 648 0) 649 650 #define MXC_UART_GET_UART(i) \ 651 ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : (i) == 3 ? MXC_UART3 : 0) 652 653 #define MXC_UART_GET_IDX(p) \ 654 ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : (p) == MXC_UART3 ? 3 : -1) 655 656 /******************************************************************************/ 657 /* SPI */ 658 #define MXC_SPI_INSTANCES (3) 659 #define MXC_SPI_SS_INSTANCES (4) 660 #define MXC_SPI_FIFO_DEPTH (32) 661 662 #define MXC_BASE_SPI0 ((uint32_t)0x40046000UL) 663 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) 664 #define MXC_BASE_SPI1 ((uint32_t)0x40047000UL) 665 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) 666 // SPI2 does not exist in the MAX32572 (to match instance addressing with MAX32570B) 667 #define MXC_BASE_SPI3 ((uint32_t)0x400BE000UL) 668 #define MXC_SPI3 ((mxc_spi_regs_t *)MXC_BASE_SPI3) 669 670 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI3 ? 3 : -1) 671 672 #define MXC_SPI_GET_BASE(i) \ 673 ((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : (i) == 3 ? MXC_BASE_SPI3 : 0) 674 675 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : (i) == 3 ? MXC_SPI3 : 0) 676 677 #define MXC_SPI_GET_IRQ(i) \ 678 (IRQn_Type)((i) == 0 ? SPI0_IRQn : (i) == 1 ? SPI1_IRQn : (i) == 3 ? SPI3_IRQn : 0) 679 680 /******************************************************************************/ 681 /* TRNG */ 682 #define MXC_BASE_TRNG ((uint32_t)0x4004D000UL) 683 #define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG) 684 685 /******************************************************************************/ 686 /* USB */ 687 #define MXC_BASE_USBHS ((uint32_t)0x400B1000UL) 688 #define MXC_USBHS ((mxc_usbhs_regs_t *)MXC_BASE_USBHS) 689 #define MXC_USBHS_NUM_EP 12 /* HW must have at least EP 0 CONTROL + 11 IN/OUT */ 690 #define MXC_USBHS_NUM_DMA 8 /* HW must have at least this many DMA channels */ 691 #define MXC_USBHS_MAX_PACKET 64 692 693 /******************************************************************************/ 694 /* Bit Shifting */ 695 696 #define MXC_F_BIT_0 (1 << 0) 697 #define MXC_F_BIT_1 (1 << 1) 698 #define MXC_F_BIT_2 (1 << 2) 699 #define MXC_F_BIT_3 (1 << 3) 700 #define MXC_F_BIT_4 (1 << 4) 701 #define MXC_F_BIT_5 (1 << 5) 702 #define MXC_F_BIT_6 (1 << 6) 703 #define MXC_F_BIT_7 (1 << 7) 704 #define MXC_F_BIT_8 (1 << 8) 705 #define MXC_F_BIT_9 (1 << 9) 706 #define MXC_F_BIT_10 (1 << 10) 707 #define MXC_F_BIT_11 (1 << 11) 708 #define MXC_F_BIT_12 (1 << 12) 709 #define MXC_F_BIT_13 (1 << 13) 710 #define MXC_F_BIT_14 (1 << 14) 711 #define MXC_F_BIT_15 (1 << 15) 712 #define MXC_F_BIT_16 (1 << 16) 713 #define MXC_F_BIT_17 (1 << 17) 714 #define MXC_F_BIT_18 (1 << 18) 715 #define MXC_F_BIT_19 (1 << 19) 716 #define MXC_F_BIT_20 (1 << 20) 717 #define MXC_F_BIT_21 (1 << 21) 718 #define MXC_F_BIT_22 (1 << 22) 719 #define MXC_F_BIT_23 (1 << 23) 720 #define MXC_F_BIT_24 (1 << 24) 721 #define MXC_F_BIT_25 (1 << 25) 722 #define MXC_F_BIT_26 (1 << 26) 723 #define MXC_F_BIT_27 (1 << 27) 724 #define MXC_F_BIT_28 (1 << 28) 725 #define MXC_F_BIT_29 (1 << 29) 726 #define MXC_F_BIT_30 (1 << 30) 727 #define MXC_F_BIT_31 (1 << 31) 728 729 /******************************************************************************/ 730 /* Bit Banding */ 731 #define BITBAND(reg, bit) \ 732 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ 733 ((bit) << 2)) 734 735 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) 736 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) 737 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) 738 739 #define MXC_SETFIELD(reg, mask, setting) ((reg) = ((reg) & ~(mask)) | ((setting) & (mask))) 740 741 /******************************************************************************/ 742 /* SCB CPACR */ 743 744 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ 745 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ 746 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ 747 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ 748 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ 749 750 // clang-format on 751 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_MAX32572_H_ 752
