1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 /* **** Includes **** */
22 #include <stddef.h>
23 #include "mxc_device.h"
24 #include "mxc_assert.h"
25 #include "gpio.h"
26 #include "gpio_revb.h"
27 #include "gpio_common.h"
28
29 /* **** Functions **** */
MXC_GPIO_RevB_Config(const mxc_gpio_cfg_t * cfg,uint8_t psMask)30 int MXC_GPIO_RevB_Config(const mxc_gpio_cfg_t *cfg, uint8_t psMask)
31 {
32 mxc_gpio_regs_t *gpio = cfg->port;
33
34 // Set the GPIO type
35 switch (cfg->func) {
36 case MXC_GPIO_FUNC_IN:
37 gpio->outen_clr = cfg->mask;
38 gpio->en0_set = cfg->mask;
39 gpio->en1_clr = cfg->mask;
40 gpio->en2_clr = cfg->mask;
41 break;
42
43 case MXC_GPIO_FUNC_OUT:
44 gpio->outen_set = cfg->mask;
45 gpio->en0_set = cfg->mask;
46 gpio->en1_clr = cfg->mask;
47 gpio->en2_clr = cfg->mask;
48 break;
49
50 case MXC_GPIO_FUNC_ALT1:
51 gpio->en0_clr = cfg->mask;
52 gpio->en1_clr = cfg->mask;
53 gpio->en2_clr = cfg->mask;
54 break;
55
56 case MXC_GPIO_FUNC_ALT2:
57 gpio->en0_clr = cfg->mask;
58 gpio->en1_set = cfg->mask;
59 gpio->en2_clr = cfg->mask;
60 break;
61
62 case MXC_GPIO_FUNC_ALT3:
63 gpio->en0_set = cfg->mask;
64 gpio->en1_set = cfg->mask;
65 gpio->en2_clr = cfg->mask;
66 break;
67
68 default:
69 return E_BAD_PARAM;
70 }
71
72 // Configure the pad
73 switch (cfg->pad) {
74 case MXC_GPIO_PAD_NONE:
75 gpio->padctrl0 &= ~cfg->mask;
76 gpio->padctrl1 &= ~cfg->mask;
77 if (psMask == MXC_GPIO_PS_PULL_SELECT) {
78 gpio->ps &= ~cfg->mask;
79 }
80 break;
81
82 case MXC_GPIO_PAD_PULL_UP:
83 gpio->padctrl0 |= cfg->mask;
84 gpio->padctrl1 &= ~cfg->mask;
85 if (psMask == MXC_GPIO_PS_PULL_SELECT) {
86 gpio->ps |= cfg->mask;
87 }
88 break;
89
90 case MXC_GPIO_PAD_PULL_DOWN:
91 gpio->padctrl0 &= ~cfg->mask;
92 gpio->padctrl1 |= cfg->mask;
93 if (psMask == MXC_GPIO_PS_PULL_SELECT) {
94 gpio->ps &= ~cfg->mask;
95 }
96 break;
97
98 default:
99 return E_BAD_PARAM;
100 }
101
102 // Configure the vssel
103 MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask);
104
105 return E_NO_ERROR;
106 }
107
MXC_GPIO_RevB_InGet(mxc_gpio_regs_t * port,uint32_t mask)108 uint32_t MXC_GPIO_RevB_InGet(mxc_gpio_regs_t *port, uint32_t mask)
109 {
110 return (port->in & mask);
111 }
112
MXC_GPIO_RevB_OutSet(mxc_gpio_regs_t * port,uint32_t mask)113 void MXC_GPIO_RevB_OutSet(mxc_gpio_regs_t *port, uint32_t mask)
114 {
115 port->out_set = mask;
116 }
117
MXC_GPIO_RevB_OutClr(mxc_gpio_regs_t * port,uint32_t mask)118 void MXC_GPIO_RevB_OutClr(mxc_gpio_regs_t *port, uint32_t mask)
119 {
120 port->out_clr = mask;
121 }
122
MXC_GPIO_RevB_OutGet(mxc_gpio_regs_t * port,uint32_t mask)123 uint32_t MXC_GPIO_RevB_OutGet(mxc_gpio_regs_t *port, uint32_t mask)
124 {
125 return (port->out & mask);
126 }
127
MXC_GPIO_RevB_OutPut(mxc_gpio_regs_t * port,uint32_t mask,uint32_t val)128 void MXC_GPIO_RevB_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val)
129 {
130 port->out = (port->out & ~mask) | (val & mask);
131 }
132
MXC_GPIO_RevB_OutToggle(mxc_gpio_regs_t * port,uint32_t mask)133 void MXC_GPIO_RevB_OutToggle(mxc_gpio_regs_t *port, uint32_t mask)
134 {
135 port->out ^= mask;
136 }
137
MXC_GPIO_RevB_IntConfig(const mxc_gpio_cfg_t * cfg,mxc_gpio_int_pol_t pol)138 int MXC_GPIO_RevB_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol)
139 {
140 mxc_gpio_regs_t *gpio = cfg->port;
141
142 switch (pol) {
143 case MXC_GPIO_INT_HIGH:
144 gpio->intpol &= ~cfg->mask;
145 gpio->dualedge &= ~cfg->mask;
146 gpio->intmode &= ~cfg->mask;
147 break;
148
149 case MXC_GPIO_INT_FALLING: /* MXC_GPIO_INT_HIGH */
150 gpio->intpol &= ~cfg->mask;
151 gpio->dualedge &= ~cfg->mask;
152 gpio->intmode |= cfg->mask;
153 break;
154
155 case MXC_GPIO_INT_LOW: /* MXC_GPIO_INT_LOW */
156 gpio->intpol |= cfg->mask;
157 gpio->dualedge &= ~cfg->mask;
158 gpio->intmode &= ~cfg->mask;
159 break;
160
161 case MXC_GPIO_INT_RISING: /* MXC_GPIO_INT_LOW */
162 gpio->intpol |= cfg->mask;
163 gpio->dualedge &= ~cfg->mask;
164 gpio->intmode |= cfg->mask;
165 break;
166
167 case MXC_GPIO_INT_BOTH:
168 gpio->dualedge |= cfg->mask;
169 gpio->intmode |= cfg->mask;
170 break;
171
172 default:
173 return E_BAD_PARAM;
174 }
175
176 return E_NO_ERROR;
177 }
178
MXC_GPIO_RevB_EnableInt(mxc_gpio_regs_t * port,uint32_t mask)179 void MXC_GPIO_RevB_EnableInt(mxc_gpio_regs_t *port, uint32_t mask)
180 {
181 port->inten_set = mask;
182 }
183
MXC_GPIO_RevB_DisableInt(mxc_gpio_regs_t * port,uint32_t mask)184 void MXC_GPIO_RevB_DisableInt(mxc_gpio_regs_t *port, uint32_t mask)
185 {
186 port->inten_clr = mask;
187 }
188
MXC_GPIO_RevB_ClearFlags(mxc_gpio_regs_t * port,uint32_t flags)189 void MXC_GPIO_RevB_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags)
190 {
191 port->intfl_clr = flags;
192 }
193
MXC_GPIO_RevB_GetFlags(mxc_gpio_regs_t * port)194 uint32_t MXC_GPIO_RevB_GetFlags(mxc_gpio_regs_t *port)
195 {
196 return port->intfl;
197 }
198
MXC_GPIO_RevB_SetVSSEL(mxc_gpio_regs_t * port,mxc_gpio_vssel_t vssel,uint32_t mask)199 int MXC_GPIO_RevB_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask)
200 {
201 // Configure the vssel
202 switch (vssel) {
203 case MXC_GPIO_VSSEL_VDDIO:
204 port->vssel &= ~mask;
205 break;
206
207 case MXC_GPIO_VSSEL_VDDIOH:
208 port->vssel |= mask;
209 break;
210
211 default:
212 return E_BAD_PARAM;
213 }
214
215 return E_NO_ERROR;
216 }
217
