1 /** 2 * @file uart_revb_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the UART_REVB Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _UART_REVB_REGS_H_ 27 #define _UART_REVB_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup uart_revb 65 * @defgroup uart_revb_registers UART_REVB_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the UART_REVB Peripheral Module. 67 * @details UART Low Power Registers 68 */ 69 70 /** 71 * @ingroup uart_revb_registers 72 * Structure type to access the UART_REVB Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> UART_REVB CTRL Register */ 76 __I uint32_t status; /**< <tt>\b 0x0004:</tt> UART_REVB STATUS Register */ 77 __IO uint32_t int_en; /**< <tt>\b 0x0008:</tt> UART_REVB INT_EN Register */ 78 __IO uint32_t int_fl; /**< <tt>\b 0x000C:</tt> UART_REVB INT_FL Register */ 79 __IO uint32_t clkdiv; /**< <tt>\b 0x0010:</tt> UART_REVB CLKDIV Register */ 80 __IO uint32_t osr; /**< <tt>\b 0x0014:</tt> UART_REVB OSR Register */ 81 __IO uint32_t txpeek; /**< <tt>\b 0x0018:</tt> UART_REVB TXPEEK Register */ 82 __IO uint32_t pnr; /**< <tt>\b 0x001C:</tt> UART_REVB PNR Register */ 83 __IO uint32_t fifo; /**< <tt>\b 0x0020:</tt> UART_REVB FIFO Register */ 84 __R uint32_t rsv_0x24_0x2f[3]; 85 __IO uint32_t dma; /**< <tt>\b 0x0030:</tt> UART_REVB DMA Register */ 86 __IO uint32_t wken; /**< <tt>\b 0x0034:</tt> UART_REVB WKEN Register */ 87 __IO uint32_t wkfl; /**< <tt>\b 0x0038:</tt> UART_REVB WKFL Register */ 88 } mxc_uart_revb_regs_t; 89 90 /* Register offsets for module UART_REVB */ 91 /** 92 * @ingroup uart_revb_registers 93 * @defgroup UART_REVB_Register_Offsets Register Offsets 94 * @brief UART_REVB Peripheral Register Offsets from the UART_REVB Base Peripheral Address. 95 * @{ 96 */ 97 #define MXC_R_UART_REVB_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART_REVB Base Address: <tt> 0x0000</tt> */ 98 #define MXC_R_UART_REVB_STATUS ((uint32_t)0x00000004UL) /**< Offset from UART_REVB Base Address: <tt> 0x0004</tt> */ 99 #define MXC_R_UART_REVB_INT_EN ((uint32_t)0x00000008UL) /**< Offset from UART_REVB Base Address: <tt> 0x0008</tt> */ 100 #define MXC_R_UART_REVB_INT_FL ((uint32_t)0x0000000CUL) /**< Offset from UART_REVB Base Address: <tt> 0x000C</tt> */ 101 #define MXC_R_UART_REVB_CLKDIV ((uint32_t)0x00000010UL) /**< Offset from UART_REVB Base Address: <tt> 0x0010</tt> */ 102 #define MXC_R_UART_REVB_OSR ((uint32_t)0x00000014UL) /**< Offset from UART_REVB Base Address: <tt> 0x0014</tt> */ 103 #define MXC_R_UART_REVB_TXPEEK ((uint32_t)0x00000018UL) /**< Offset from UART_REVB Base Address: <tt> 0x0018</tt> */ 104 #define MXC_R_UART_REVB_PNR ((uint32_t)0x0000001CUL) /**< Offset from UART_REVB Base Address: <tt> 0x001C</tt> */ 105 #define MXC_R_UART_REVB_FIFO ((uint32_t)0x00000020UL) /**< Offset from UART_REVB Base Address: <tt> 0x0020</tt> */ 106 #define MXC_R_UART_REVB_DMA ((uint32_t)0x00000030UL) /**< Offset from UART_REVB Base Address: <tt> 0x0030</tt> */ 107 #define MXC_R_UART_REVB_WKEN ((uint32_t)0x00000034UL) /**< Offset from UART_REVB Base Address: <tt> 0x0034</tt> */ 108 #define MXC_R_UART_REVB_WKFL ((uint32_t)0x00000038UL) /**< Offset from UART_REVB Base Address: <tt> 0x0038</tt> */ 109 /**@} end of group uart_revb_registers */ 110 111 /** 112 * @ingroup uart_revb_registers 113 * @defgroup UART_REVB_CTRL UART_REVB_CTRL 114 * @brief Control register 115 * @{ 116 */ 117 #define MXC_F_UART_REVB_CTRL_RX_THD_VAL_POS 0 /**< CTRL_RX_THD_VAL Position */ 118 #define MXC_F_UART_REVB_CTRL_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */ 119 120 #define MXC_F_UART_REVB_CTRL_PAR_EN_POS 4 /**< CTRL_PAR_EN Position */ 121 #define MXC_F_UART_REVB_CTRL_PAR_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */ 122 123 #define MXC_F_UART_REVB_CTRL_PAR_EO_POS 5 /**< CTRL_PAR_EO Position */ 124 #define MXC_F_UART_REVB_CTRL_PAR_EO ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */ 125 126 #define MXC_F_UART_REVB_CTRL_PAR_MD_POS 6 /**< CTRL_PAR_MD Position */ 127 #define MXC_F_UART_REVB_CTRL_PAR_MD ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */ 128 129 #define MXC_F_UART_REVB_CTRL_CTS_DIS_POS 7 /**< CTRL_CTS_DIS Position */ 130 #define MXC_F_UART_REVB_CTRL_CTS_DIS ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */ 131 132 #define MXC_F_UART_REVB_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */ 133 #define MXC_F_UART_REVB_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ 134 135 #define MXC_F_UART_REVB_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */ 136 #define MXC_F_UART_REVB_CTRL_RX_FLUSH ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ 137 138 #define MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */ 139 #define MXC_F_UART_REVB_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ 140 #define MXC_V_UART_REVB_CTRL_CHAR_SIZE_5BITS ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */ 141 #define MXC_S_UART_REVB_CTRL_CHAR_SIZE_5BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */ 142 #define MXC_V_UART_REVB_CTRL_CHAR_SIZE_6BITS ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */ 143 #define MXC_S_UART_REVB_CTRL_CHAR_SIZE_6BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */ 144 #define MXC_V_UART_REVB_CTRL_CHAR_SIZE_7BITS ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */ 145 #define MXC_S_UART_REVB_CTRL_CHAR_SIZE_7BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */ 146 #define MXC_V_UART_REVB_CTRL_CHAR_SIZE_8BITS ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */ 147 #define MXC_S_UART_REVB_CTRL_CHAR_SIZE_8BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */ 148 149 #define MXC_F_UART_REVB_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */ 150 #define MXC_F_UART_REVB_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ 151 152 #define MXC_F_UART_REVB_CTRL_HFC_EN_POS 13 /**< CTRL_HFC_EN Position */ 153 #define MXC_F_UART_REVB_CTRL_HFC_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */ 154 155 #define MXC_F_UART_REVB_CTRL_RTSDC_POS 14 /**< CTRL_RTSDC Position */ 156 #define MXC_F_UART_REVB_CTRL_RTSDC ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_RTSDC_POS)) /**< CTRL_RTSDC Mask */ 157 158 #define MXC_F_UART_REVB_CTRL_BCLKEN_POS 15 /**< CTRL_BCLKEN Position */ 159 #define MXC_F_UART_REVB_CTRL_BCLKEN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_BCLKEN_POS)) /**< CTRL_BCLKEN Mask */ 160 161 #define MXC_F_UART_REVB_CTRL_BCLKSRC_POS 16 /**< CTRL_BCLKSRC Position */ 162 #define MXC_F_UART_REVB_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */ 163 #define MXC_V_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */ 164 #define MXC_S_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */ 165 #define MXC_V_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Value */ 166 #define MXC_S_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK (MXC_V_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Setting */ 167 #define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */ 168 #define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK2 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK2 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */ 169 #define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */ 170 #define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK3 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK3 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK3 Setting */ 171 172 #define MXC_F_UART_REVB_CTRL_DPFE_EN_POS 18 /**< CTRL_DPFE_EN Position */ 173 #define MXC_F_UART_REVB_CTRL_DPFE_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_DPFE_EN_POS)) /**< CTRL_DPFE_EN Mask */ 174 175 #define MXC_F_UART_REVB_CTRL_BCLKRDY_POS 19 /**< CTRL_BCLKRDY Position */ 176 #define MXC_F_UART_REVB_CTRL_BCLKRDY ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_BCLKRDY_POS)) /**< CTRL_BCLKRDY Mask */ 177 178 #define MXC_F_UART_REVB_CTRL_UCAGM_POS 20 /**< CTRL_UCAGM Position */ 179 #define MXC_F_UART_REVB_CTRL_UCAGM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_UCAGM_POS)) /**< CTRL_UCAGM Mask */ 180 181 #define MXC_F_UART_REVB_CTRL_FDM_POS 21 /**< CTRL_FDM Position */ 182 #define MXC_F_UART_REVB_CTRL_FDM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_FDM_POS)) /**< CTRL_FDM Mask */ 183 184 #define MXC_F_UART_REVB_CTRL_DESM_POS 22 /**< CTRL_DESM Position */ 185 #define MXC_F_UART_REVB_CTRL_DESM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_DESM_POS)) /**< CTRL_DESM Mask */ 186 187 /**@} end of group UART_REVB_CTRL_Register */ 188 189 /** 190 * @ingroup uart_revb_registers 191 * @defgroup UART_REVB_STATUS UART_REVB_STATUS 192 * @brief Status register 193 * @{ 194 */ 195 #define MXC_F_UART_REVB_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ 196 #define MXC_F_UART_REVB_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ 197 198 #define MXC_F_UART_REVB_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ 199 #define MXC_F_UART_REVB_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ 200 201 #define MXC_F_UART_REVB_STATUS_RX_EM_POS 4 /**< STATUS_RX_EM Position */ 202 #define MXC_F_UART_REVB_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ 203 204 #define MXC_F_UART_REVB_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ 205 #define MXC_F_UART_REVB_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ 206 207 #define MXC_F_UART_REVB_STATUS_TX_EM_POS 6 /**< STATUS_TX_EM Position */ 208 #define MXC_F_UART_REVB_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ 209 210 #define MXC_F_UART_REVB_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ 211 #define MXC_F_UART_REVB_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ 212 213 #define MXC_F_UART_REVB_STATUS_RX_LVL_POS 8 /**< STATUS_RX_LVL Position */ 214 #define MXC_F_UART_REVB_STATUS_RX_LVL ((uint32_t)(0xFUL << MXC_F_UART_REVB_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */ 215 216 #define MXC_F_UART_REVB_STATUS_TX_LVL_POS 12 /**< STATUS_TX_LVL Position */ 217 #define MXC_F_UART_REVB_STATUS_TX_LVL ((uint32_t)(0xFUL << MXC_F_UART_REVB_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */ 218 219 /**@} end of group UART_REVB_STATUS_Register */ 220 221 /** 222 * @ingroup uart_revb_registers 223 * @defgroup UART_REVB_INT_EN UART_REVB_INT_EN 224 * @brief Interrupt Enable control register 225 * @{ 226 */ 227 #define MXC_F_UART_REVB_INT_EN_RX_FERR_POS 0 /**< INT_EN_RX_FERR Position */ 228 #define MXC_F_UART_REVB_INT_EN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_FERR_POS)) /**< INT_EN_RX_FERR Mask */ 229 230 #define MXC_F_UART_REVB_INT_EN_RX_PAR_POS 1 /**< INT_EN_RX_PAR Position */ 231 #define MXC_F_UART_REVB_INT_EN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_PAR_POS)) /**< INT_EN_RX_PAR Mask */ 232 233 #define MXC_F_UART_REVB_INT_EN_CTS_EV_POS 2 /**< INT_EN_CTS_EV Position */ 234 #define MXC_F_UART_REVB_INT_EN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_CTS_EV_POS)) /**< INT_EN_CTS_EV Mask */ 235 236 #define MXC_F_UART_REVB_INT_EN_RX_OV_POS 3 /**< INT_EN_RX_OV Position */ 237 #define MXC_F_UART_REVB_INT_EN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_OV_POS)) /**< INT_EN_RX_OV Mask */ 238 239 #define MXC_F_UART_REVB_INT_EN_RX_THD_POS 4 /**< INT_EN_RX_THD Position */ 240 #define MXC_F_UART_REVB_INT_EN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_THD_POS)) /**< INT_EN_RX_THD Mask */ 241 242 #define MXC_F_UART_REVB_INT_EN_TX_HE_POS 6 /**< INT_EN_TX_HE Position */ 243 #define MXC_F_UART_REVB_INT_EN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_TX_HE_POS)) /**< INT_EN_TX_HE Mask */ 244 245 /**@} end of group UART_REVB_INT_EN_Register */ 246 247 /** 248 * @ingroup uart_revb_registers 249 * @defgroup UART_REVB_INT_FL UART_REVB_INT_FL 250 * @brief Interrupt status flags Control register 251 * @{ 252 */ 253 #define MXC_F_UART_REVB_INT_FL_RX_FERR_POS 0 /**< INT_FL_RX_FERR Position */ 254 #define MXC_F_UART_REVB_INT_FL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_FERR_POS)) /**< INT_FL_RX_FERR Mask */ 255 256 #define MXC_F_UART_REVB_INT_FL_RX_PAR_POS 1 /**< INT_FL_RX_PAR Position */ 257 #define MXC_F_UART_REVB_INT_FL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_PAR_POS)) /**< INT_FL_RX_PAR Mask */ 258 259 #define MXC_F_UART_REVB_INT_FL_CTS_EV_POS 2 /**< INT_FL_CTS_EV Position */ 260 #define MXC_F_UART_REVB_INT_FL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_CTS_EV_POS)) /**< INT_FL_CTS_EV Mask */ 261 262 #define MXC_F_UART_REVB_INT_FL_RX_OV_POS 3 /**< INT_FL_RX_OV Position */ 263 #define MXC_F_UART_REVB_INT_FL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_OV_POS)) /**< INT_FL_RX_OV Mask */ 264 265 #define MXC_F_UART_REVB_INT_FL_RX_THD_POS 4 /**< INT_FL_RX_THD Position */ 266 #define MXC_F_UART_REVB_INT_FL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_THD_POS)) /**< INT_FL_RX_THD Mask */ 267 268 #define MXC_F_UART_REVB_INT_FL_TX_HE_POS 6 /**< INT_FL_TX_HE Position */ 269 #define MXC_F_UART_REVB_INT_FL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_TX_HE_POS)) /**< INT_FL_TX_HE Mask */ 270 271 /**@} end of group UART_REVB_INT_FL_Register */ 272 273 /** 274 * @ingroup uart_revb_registers 275 * @defgroup UART_REVB_CLKDIV UART_REVB_CLKDIV 276 * @brief Clock Divider register 277 * @{ 278 */ 279 #define MXC_F_UART_REVB_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ 280 #define MXC_F_UART_REVB_CLKDIV_CLKDIV ((uint32_t)(0xFFFFFUL << MXC_F_UART_REVB_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ 281 282 /**@} end of group UART_REVB_CLKDIV_Register */ 283 284 /** 285 * @ingroup uart_revb_registers 286 * @defgroup UART_REVB_OSR UART_REVB_OSR 287 * @brief Over Sampling Rate register 288 * @{ 289 */ 290 #define MXC_F_UART_REVB_OSR_OSR_POS 0 /**< OSR_OSR Position */ 291 #define MXC_F_UART_REVB_OSR_OSR ((uint32_t)(0x7UL << MXC_F_UART_REVB_OSR_OSR_POS)) /**< OSR_OSR Mask */ 292 293 /**@} end of group UART_REVB_OSR_Register */ 294 295 /** 296 * @ingroup uart_revb_registers 297 * @defgroup UART_REVB_TXPEEK UART_REVB_TXPEEK 298 * @brief TX FIFO Output Peek register 299 * @{ 300 */ 301 #define MXC_F_UART_REVB_TXPEEK_DATA_POS 0 /**< TXPEEK_DATA Position */ 302 #define MXC_F_UART_REVB_TXPEEK_DATA ((uint32_t)(0xFFUL << MXC_F_UART_REVB_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */ 303 304 /**@} end of group UART_REVB_TXPEEK_Register */ 305 306 /** 307 * @ingroup uart_revb_registers 308 * @defgroup UART_REVB_PNR UART_REVB_PNR 309 * @brief Pin register 310 * @{ 311 */ 312 #define MXC_F_UART_REVB_PNR_CTS_POS 0 /**< PNR_CTS Position */ 313 #define MXC_F_UART_REVB_PNR_CTS ((uint32_t)(0x1UL << MXC_F_UART_REVB_PNR_CTS_POS)) /**< PNR_CTS Mask */ 314 315 #define MXC_F_UART_REVB_PNR_RTS_POS 1 /**< PNR_RTS Position */ 316 #define MXC_F_UART_REVB_PNR_RTS ((uint32_t)(0x1UL << MXC_F_UART_REVB_PNR_RTS_POS)) /**< PNR_RTS Mask */ 317 318 /**@} end of group UART_REVB_PNR_Register */ 319 320 /** 321 * @ingroup uart_revb_registers 322 * @defgroup UART_REVB_FIFO UART_REVB_FIFO 323 * @brief FIFO Read/Write register 324 * @{ 325 */ 326 #define MXC_F_UART_REVB_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ 327 #define MXC_F_UART_REVB_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_UART_REVB_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ 328 329 #define MXC_F_UART_REVB_FIFO_RX_PAR_POS 8 /**< FIFO_RX_PAR Position */ 330 #define MXC_F_UART_REVB_FIFO_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */ 331 332 /**@} end of group UART_REVB_FIFO_Register */ 333 334 /** 335 * @ingroup uart_revb_registers 336 * @defgroup UART_REVB_DMA UART_REVB_DMA 337 * @brief DMA Configuration register 338 * @{ 339 */ 340 #define MXC_F_UART_REVB_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ 341 #define MXC_F_UART_REVB_DMA_TX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ 342 343 #define MXC_F_UART_REVB_DMA_TX_EN_POS 4 /**< DMA_TX_EN Position */ 344 #define MXC_F_UART_REVB_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ 345 346 #define MXC_F_UART_REVB_DMA_RX_THD_VAL_POS 5 /**< DMA_RX_THD_VAL Position */ 347 #define MXC_F_UART_REVB_DMA_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ 348 349 #define MXC_F_UART_REVB_DMA_RX_EN_POS 9 /**< DMA_RX_EN Position */ 350 #define MXC_F_UART_REVB_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ 351 352 /**@} end of group UART_REVB_DMA_Register */ 353 354 /** 355 * @ingroup uart_revb_registers 356 * @defgroup UART_REVB_WKEN UART_REVB_WKEN 357 * @brief Wake up enable Control register 358 * @{ 359 */ 360 #define MXC_F_UART_REVB_WKEN_RX_NE_POS 0 /**< WKEN_RX_NE Position */ 361 #define MXC_F_UART_REVB_WKEN_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */ 362 363 #define MXC_F_UART_REVB_WKEN_RX_FULL_POS 1 /**< WKEN_RX_FULL Position */ 364 #define MXC_F_UART_REVB_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ 365 366 #define MXC_F_UART_REVB_WKEN_RX_THD_POS 1 /**< WKEN_RX_THD Position */ 367 #define MXC_F_UART_REVB_WKEN_RX_THD ((uint32_t)(0x3UL << MXC_F_UART_REVB_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ 368 369 /**@} end of group UART_REVB_WKEN_Register */ 370 371 /** 372 * @ingroup uart_revb_registers 373 * @defgroup UART_REVB_WKFL UART_REVB_WKFL 374 * @brief Wake up Flags register 375 * @{ 376 */ 377 #define MXC_F_UART_REVB_WKFL_RX_NE_POS 0 /**< WKFL_RX_NE Position */ 378 #define MXC_F_UART_REVB_WKFL_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */ 379 380 #define MXC_F_UART_REVB_WKFL_RX_FULL_POS 1 /**< WKFL_RX_FULL Position */ 381 #define MXC_F_UART_REVB_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ 382 383 #define MXC_F_UART_REVB_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ 384 #define MXC_F_UART_REVB_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ 385 386 /**@} end of group UART_REVB_WKFL_Register */ 387 388 #ifdef __cplusplus 389 } 390 #endif 391 392 #endif /* _UART_REVB_REGS_H_ */ 393
