1 /** 2 * @file uart_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _UART_REVA_REGS_H_ 27 #define _UART_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup uart 65 * @defgroup uart_registers UART_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. 67 * @details UART 68 */ 69 70 /** 71 * @ingroup uart_registers 72 * Structure type to access the UART Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> UART CTRL Register */ 76 __IO uint32_t thresh_ctrl; /**< <tt>\b 0x04:</tt> UART THRESH_CTRL Register */ 77 __I uint32_t status; /**< <tt>\b 0x08:</tt> UART STATUS Register */ 78 __IO uint32_t int_en; /**< <tt>\b 0x0C:</tt> UART INT_EN Register */ 79 __IO uint32_t int_fl; /**< <tt>\b 0x10:</tt> UART INT_FL Register */ 80 __IO uint32_t baud0; /**< <tt>\b 0x14:</tt> UART BAUD0 Register */ 81 __IO uint32_t baud1; /**< <tt>\b 0x18:</tt> UART BAUD1 Register */ 82 __IO uint32_t fifo; /**< <tt>\b 0x1C:</tt> UART FIFO Register */ 83 __IO uint32_t dma; /**< <tt>\b 0x20:</tt> UART DMA Register */ 84 __IO uint32_t tx_fifo; /**< <tt>\b 0x24:</tt> UART TX_FIFO Register */ 85 } mxc_uart_reva_regs_t; 86 87 /* Register offsets for module UART */ 88 /** 89 * @ingroup uart_registers 90 * @defgroup UART_Register_Offsets Register Offsets 91 * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_UART_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_UART_REVA_THRESH_CTRL ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */ 96 #define MXC_R_UART_REVA_STATUS ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_UART_REVA_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */ 98 #define MXC_R_UART_REVA_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */ 99 #define MXC_R_UART_REVA_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */ 100 #define MXC_R_UART_REVA_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */ 101 #define MXC_R_UART_REVA_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */ 102 #define MXC_R_UART_REVA_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */ 103 #define MXC_R_UART_REVA_TX_FIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> 0x0024</tt> */ 104 /**@} end of group uart_registers */ 105 106 /** 107 * @ingroup uart_registers 108 * @defgroup UART_CTRL UART_CTRL 109 * @brief Control Register. 110 * @{ 111 */ 112 #define MXC_F_UART_REVA_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ 113 #define MXC_F_UART_REVA_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ 114 115 #define MXC_F_UART_REVA_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */ 116 #define MXC_F_UART_REVA_CTRL_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */ 117 118 #define MXC_F_UART_REVA_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */ 119 #define MXC_F_UART_REVA_CTRL_PARITY ((uint32_t)(0x3UL << MXC_F_UART_REVA_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */ 120 #define MXC_V_UART_REVA_CTRL_PARITY_EVEN ((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */ 121 #define MXC_S_UART_REVA_CTRL_PARITY_EVEN (MXC_V_UART_REVA_CTRL_PARITY_EVEN << MXC_F_UART_REVA_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */ 122 #define MXC_V_UART_REVA_CTRL_PARITY_ODD ((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */ 123 #define MXC_S_UART_REVA_CTRL_PARITY_ODD (MXC_V_UART_REVA_CTRL_PARITY_ODD << MXC_F_UART_REVA_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */ 124 #define MXC_V_UART_REVA_CTRL_PARITY_MARK ((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */ 125 #define MXC_S_UART_REVA_CTRL_PARITY_MARK (MXC_V_UART_REVA_CTRL_PARITY_MARK << MXC_F_UART_REVA_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */ 126 #define MXC_V_UART_REVA_CTRL_PARITY_SPACE ((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */ 127 #define MXC_S_UART_REVA_CTRL_PARITY_SPACE (MXC_V_UART_REVA_CTRL_PARITY_SPACE << MXC_F_UART_REVA_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */ 128 129 #define MXC_F_UART_REVA_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */ 130 #define MXC_F_UART_REVA_CTRL_PARMD ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask */ 131 132 #define MXC_F_UART_REVA_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */ 133 #define MXC_F_UART_REVA_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ 134 135 #define MXC_F_UART_REVA_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */ 136 #define MXC_F_UART_REVA_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ 137 138 #define MXC_F_UART_REVA_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */ 139 #define MXC_F_UART_REVA_CTRL_BITACC ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */ 140 141 #define MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */ 142 #define MXC_F_UART_REVA_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ 143 #define MXC_V_UART_REVA_CTRL_CHAR_SIZE_5 ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */ 144 #define MXC_S_UART_REVA_CTRL_CHAR_SIZE_5 (MXC_V_UART_REVA_CTRL_CHAR_SIZE_5 << MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */ 145 #define MXC_V_UART_REVA_CTRL_CHAR_SIZE_6 ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */ 146 #define MXC_S_UART_REVA_CTRL_CHAR_SIZE_6 (MXC_V_UART_REVA_CTRL_CHAR_SIZE_6 << MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */ 147 #define MXC_V_UART_REVA_CTRL_CHAR_SIZE_7 ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */ 148 #define MXC_S_UART_REVA_CTRL_CHAR_SIZE_7 (MXC_V_UART_REVA_CTRL_CHAR_SIZE_7 << MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */ 149 #define MXC_V_UART_REVA_CTRL_CHAR_SIZE_8 ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */ 150 #define MXC_S_UART_REVA_CTRL_CHAR_SIZE_8 (MXC_V_UART_REVA_CTRL_CHAR_SIZE_8 << MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */ 151 152 #define MXC_F_UART_REVA_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */ 153 #define MXC_F_UART_REVA_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ 154 155 #define MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */ 156 #define MXC_F_UART_REVA_CTRL_FLOW_CTRL ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */ 157 158 #define MXC_F_UART_REVA_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */ 159 #define MXC_F_UART_REVA_CTRL_FLOW_POL ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */ 160 161 #define MXC_F_UART_REVA_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */ 162 #define MXC_F_UART_REVA_CTRL_NULL_MODEM ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM Mask */ 163 164 #define MXC_F_UART_REVA_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */ 165 #define MXC_F_UART_REVA_CTRL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask */ 166 167 #define MXC_F_UART_REVA_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */ 168 #define MXC_F_UART_REVA_CTRL_CLKSEL ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */ 169 170 #define MXC_F_UART_REVA_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */ 171 #define MXC_F_UART_REVA_CTRL_RX_TO ((uint32_t)(0xFFUL << MXC_F_UART_REVA_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */ 172 173 /**@} end of group UART_CTRL_Register */ 174 175 /** 176 * @ingroup uart_registers 177 * @defgroup UART_THRESH_CTRL UART_THRESH_CTRL 178 * @brief Threshold Control register. 179 * @{ 180 */ 181 #define MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS 0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */ 182 #define MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**< THRESH_CTRL_RX_FIFO_THRESH Mask */ 183 184 #define MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH_POS 8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */ 185 #define MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**< THRESH_CTRL_TX_FIFO_THRESH Mask */ 186 187 #define MXC_F_UART_REVA_THRESH_CTRL_RTS_FIFO_THRESH_POS 16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */ 188 #define MXC_F_UART_REVA_THRESH_CTRL_RTS_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_REVA_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**< THRESH_CTRL_RTS_FIFO_THRESH Mask */ 189 190 /**@} end of group UART_THRESH_CTRL_Register */ 191 192 /** 193 * @ingroup uart_registers 194 * @defgroup UART_STATUS UART_STATUS 195 * @brief Status Register. 196 * @{ 197 */ 198 #define MXC_F_UART_REVA_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ 199 #define MXC_F_UART_REVA_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ 200 201 #define MXC_F_UART_REVA_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ 202 #define MXC_F_UART_REVA_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ 203 204 #define MXC_F_UART_REVA_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */ 205 #define MXC_F_UART_REVA_STATUS_PARITY ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */ 206 207 #define MXC_F_UART_REVA_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */ 208 #define MXC_F_UART_REVA_STATUS_BREAK ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */ 209 210 #define MXC_F_UART_REVA_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */ 211 #define MXC_F_UART_REVA_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */ 212 213 #define MXC_F_UART_REVA_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ 214 #define MXC_F_UART_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ 215 216 #define MXC_F_UART_REVA_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */ 217 #define MXC_F_UART_REVA_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */ 218 219 #define MXC_F_UART_REVA_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ 220 #define MXC_F_UART_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ 221 222 #define MXC_F_UART_REVA_STATUS_RX_FIFO_CNT_POS 8 /**< STATUS_RX_FIFO_CNT Position */ 223 #define MXC_F_UART_REVA_STATUS_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_REVA_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT Mask */ 224 225 #define MXC_F_UART_REVA_STATUS_TX_FIFO_CNT_POS 16 /**< STATUS_TX_FIFO_CNT Position */ 226 #define MXC_F_UART_REVA_STATUS_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_REVA_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT Mask */ 227 228 /**@} end of group UART_STATUS_Register */ 229 230 /** 231 * @ingroup uart_registers 232 * @defgroup UART_INT_EN UART_INT_EN 233 * @brief Interrupt Enable Register. 234 * @{ 235 */ 236 #define MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */ 237 #define MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */ 238 239 #define MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */ 240 #define MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */ 241 242 #define MXC_F_UART_REVA_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */ 243 #define MXC_F_UART_REVA_INT_EN_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE Mask */ 244 245 #define MXC_F_UART_REVA_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */ 246 #define MXC_F_UART_REVA_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */ 247 248 #define MXC_F_UART_REVA_INT_EN_RX_FIFO_THRESH_POS 4 /**< INT_EN_RX_FIFO_THRESH Position */ 249 #define MXC_F_UART_REVA_INT_EN_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_RX_FIFO_THRESH_POS)) /**< INT_EN_RX_FIFO_THRESH Mask */ 250 251 #define MXC_F_UART_REVA_INT_EN_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */ 252 #define MXC_F_UART_REVA_INT_EN_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_EN_TX_FIFO_ALMOST_EMPTY Mask */ 253 254 #define MXC_F_UART_REVA_INT_EN_TX_FIFO_THRESH_POS 6 /**< INT_EN_TX_FIFO_THRESH Position */ 255 #define MXC_F_UART_REVA_INT_EN_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_TX_FIFO_THRESH_POS)) /**< INT_EN_TX_FIFO_THRESH Mask */ 256 257 #define MXC_F_UART_REVA_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */ 258 #define MXC_F_UART_REVA_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */ 259 260 #define MXC_F_UART_REVA_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */ 261 #define MXC_F_UART_REVA_INT_EN_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT Mask */ 262 263 #define MXC_F_UART_REVA_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */ 264 #define MXC_F_UART_REVA_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */ 265 266 /**@} end of group UART_INT_EN_Register */ 267 268 /** 269 * @ingroup uart_registers 270 * @defgroup UART_INT_FL UART_INT_FL 271 * @brief Interrupt Status Flags. 272 * @{ 273 */ 274 #define MXC_F_UART_REVA_INT_FL_RX_FRAME_ERROR_POS 0 /**< INT_FL_RX_FRAME_ERROR Position */ 275 #define MXC_F_UART_REVA_INT_FL_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_RX_FRAME_ERROR_POS)) /**< INT_FL_RX_FRAME_ERROR Mask */ 276 277 #define MXC_F_UART_REVA_INT_FL_RX_PARITY_ERROR_POS 1 /**< INT_FL_RX_PARITY_ERROR Position */ 278 #define MXC_F_UART_REVA_INT_FL_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_RX_PARITY_ERROR_POS)) /**< INT_FL_RX_PARITY_ERROR Mask */ 279 280 #define MXC_F_UART_REVA_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */ 281 #define MXC_F_UART_REVA_INT_FL_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE Mask */ 282 283 #define MXC_F_UART_REVA_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */ 284 #define MXC_F_UART_REVA_INT_FL_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN Mask */ 285 286 #define MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH_POS 4 /**< INT_FL_RX_FIFO_THRESH Position */ 287 #define MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH_POS)) /**< INT_FL_RX_FIFO_THRESH Mask */ 288 289 #define MXC_F_UART_REVA_INT_FL_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */ 290 #define MXC_F_UART_REVA_INT_FL_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_FL_TX_FIFO_ALMOST_EMPTY Mask */ 291 292 #define MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH_POS 6 /**< INT_FL_TX_FIFO_THRESH Position */ 293 #define MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH_POS)) /**< INT_FL_TX_FIFO_THRESH Mask */ 294 295 #define MXC_F_UART_REVA_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */ 296 #define MXC_F_UART_REVA_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */ 297 298 #define MXC_F_UART_REVA_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */ 299 #define MXC_F_UART_REVA_INT_FL_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT Mask */ 300 301 #define MXC_F_UART_REVA_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */ 302 #define MXC_F_UART_REVA_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */ 303 304 /**@} end of group UART_INT_FL_Register */ 305 306 /** 307 * @ingroup uart_registers 308 * @defgroup UART_BAUD0 UART_BAUD0 309 * @brief Baud rate register. Integer portion. 310 * @{ 311 */ 312 #define MXC_F_UART_REVA_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */ 313 #define MXC_F_UART_REVA_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_REVA_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */ 314 315 #define MXC_F_UART_REVA_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */ 316 #define MXC_F_UART_REVA_BAUD0_FACTOR ((uint32_t)(0x3UL << MXC_F_UART_REVA_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */ 317 #define MXC_V_UART_REVA_BAUD0_FACTOR_128 ((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */ 318 #define MXC_S_UART_REVA_BAUD0_FACTOR_128 (MXC_V_UART_REVA_BAUD0_FACTOR_128 << MXC_F_UART_REVA_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */ 319 #define MXC_V_UART_REVA_BAUD0_FACTOR_64 ((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */ 320 #define MXC_S_UART_REVA_BAUD0_FACTOR_64 (MXC_V_UART_REVA_BAUD0_FACTOR_64 << MXC_F_UART_REVA_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */ 321 #define MXC_V_UART_REVA_BAUD0_FACTOR_32 ((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */ 322 #define MXC_S_UART_REVA_BAUD0_FACTOR_32 (MXC_V_UART_REVA_BAUD0_FACTOR_32 << MXC_F_UART_REVA_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */ 323 #define MXC_V_UART_REVA_BAUD0_FACTOR_16 ((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */ 324 #define MXC_S_UART_REVA_BAUD0_FACTOR_16 (MXC_V_UART_REVA_BAUD0_FACTOR_16 << MXC_F_UART_REVA_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */ 325 326 /**@} end of group UART_BAUD0_Register */ 327 328 /** 329 * @ingroup uart_registers 330 * @defgroup UART_BAUD1 UART_BAUD1 331 * @brief Baud rate register. Decimal Setting. 332 * @{ 333 */ 334 #define MXC_F_UART_REVA_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */ 335 #define MXC_F_UART_REVA_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_REVA_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */ 336 337 /**@} end of group UART_BAUD1_Register */ 338 339 /** 340 * @ingroup uart_registers 341 * @defgroup UART_FIFO UART_FIFO 342 * @brief FIFO Data buffer. 343 * @{ 344 */ 345 #define MXC_F_UART_REVA_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */ 346 #define MXC_F_UART_REVA_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_REVA_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */ 347 348 /**@} end of group UART_FIFO_Register */ 349 350 /** 351 * @ingroup uart_registers 352 * @defgroup UART_DMA UART_DMA 353 * @brief DMA Configuration. 354 * @{ 355 */ 356 #define MXC_F_UART_REVA_DMA_TXDMA_EN_POS 0 /**< DMA_TXDMA_EN Position */ 357 #define MXC_F_UART_REVA_DMA_TXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_REVA_DMA_TXDMA_EN_POS)) /**< DMA_TXDMA_EN Mask */ 358 359 #define MXC_F_UART_REVA_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */ 360 #define MXC_F_UART_REVA_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_REVA_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */ 361 362 #define MXC_F_UART_REVA_DMA_RXDMA_START_POS 3 /**< DMA_RXDMA_START Position */ 363 #define MXC_F_UART_REVA_DMA_RXDMA_START ((uint32_t)(0x1UL << MXC_F_UART_REVA_DMA_RXDMA_START_POS)) /**< DMA_RXDMA_START Mask */ 364 365 #define MXC_F_UART_REVA_DMA_RXDMA_AUTO_TO_POS 5 /**< DMA_RXDMA_AUTO_TO Position */ 366 #define MXC_F_UART_REVA_DMA_RXDMA_AUTO_TO ((uint32_t)(0x1UL << MXC_F_UART_REVA_DMA_RXDMA_AUTO_TO_POS)) /**< DMA_RXDMA_AUTO_TO Mask */ 367 368 #define MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */ 369 #define MXC_F_UART_REVA_DMA_TXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL Mask */ 370 371 #define MXC_F_UART_REVA_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */ 372 #define MXC_F_UART_REVA_DMA_RXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_REVA_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL Mask */ 373 374 /**@} end of group UART_DMA_Register */ 375 376 /** 377 * @ingroup uart_registers 378 * @defgroup UART_TX_FIFO UART_TX_FIFO 379 * @brief Transmit FIFO Status register. 380 * @{ 381 */ 382 #define MXC_F_UART_REVA_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */ 383 #define MXC_F_UART_REVA_TX_FIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_REVA_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */ 384 385 /**@} end of group UART_TX_FIFO_Register */ 386 387 #ifdef __cplusplus 388 } 389 #endif 390 391 #endif /* _UART_REVA_REGS_H_ */ 392
