1 /**
2  * @file    trng_revb_regs.h
3  * @brief   Registers, Bit Masks and Bit Positions for the TRNG_REVB Peripheral Module.
4  */
5 
6 /******************************************************************************
7  *
8  * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
9  * Analog Devices, Inc.),
10  * Copyright (C) 2023-2024 Analog Devices, Inc.
11  *
12  * Licensed under the Apache License, Version 2.0 (the "License");
13  * you may not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  *     http://www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an "AS IS" BASIS,
20  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  *
24  ******************************************************************************/
25 
26 #ifndef _TRNG_REVB_REGS_H_
27 #define _TRNG_REVB_REGS_H_
28 
29 /* **** Includes **** */
30 #include <stdint.h>
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 #if defined (__ICCARM__)
37   #pragma system_include
38 #endif
39 
40 #if defined (__CC_ARM)
41   #pragma anon_unions
42 #endif
43 /// @cond
44 /*
45     If types are not defined elsewhere (CMSIS) define them here
46 */
47 #ifndef __IO
48 #define __IO volatile
49 #endif
50 #ifndef __I
51 #define __I  volatile const
52 #endif
53 #ifndef __O
54 #define __O  volatile
55 #endif
56 #ifndef __R
57 #define __R  volatile const
58 #endif
59 /// @endcond
60 
61 /* **** Definitions **** */
62 
63 /**
64  * @ingroup     trng_revb
65  * @defgroup    trng_revb_registers TRNG_REVB_Registers
66  * @brief       Registers, Bit Masks and Bit Positions for the TRNG_REVB Peripheral Module.
67  * @details Random Number Generator.
68  */
69 
70 /**
71  * @ingroup trng_revb_registers
72  * Structure type to access the TRNG_REVB Registers.
73  */
74 typedef struct {
75     __IO uint32_t ctrl;                 /**< <tt>\b 0x00:</tt> TRNG_REVB CTRL Register */
76     __IO uint32_t status;               /**< <tt>\b 0x04:</tt> TRNG_REVB STATUS Register */
77     __I  uint32_t data;                 /**< <tt>\b 0x08:</tt> TRNG_REVB DATA Register */
78 } mxc_trng_revb_regs_t;
79 
80 /* Register offsets for module TRNG_REVB */
81 /**
82  * @ingroup    trng_revb_registers
83  * @defgroup   TRNG_REVB_Register_Offsets Register Offsets
84  * @brief      TRNG_REVB Peripheral Register Offsets from the TRNG_REVB Base Peripheral Address.
85  * @{
86  */
87  #define MXC_R_TRNG_REVB_CTRL               ((uint32_t)0x00000000UL) /**< Offset from TRNG_REVB Base Address: <tt> 0x0000</tt> */
88  #define MXC_R_TRNG_REVB_STATUS             ((uint32_t)0x00000004UL) /**< Offset from TRNG_REVB Base Address: <tt> 0x0004</tt> */
89  #define MXC_R_TRNG_REVB_DATA               ((uint32_t)0x00000008UL) /**< Offset from TRNG_REVB Base Address: <tt> 0x0008</tt> */
90 /**@} end of group trng_revb_registers */
91 
92 /**
93  * @ingroup  trng_revb_registers
94  * @defgroup TRNG_REVB_CTRL TRNG_REVB_CTRL
95  * @brief    TRNG Control Register.
96  * @{
97  */
98  #define MXC_F_TRNG_REVB_CTRL_ODHT_POS                  0 /**< CTRL_ODHT Position */
99  #define MXC_F_TRNG_REVB_CTRL_ODHT                      ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_ODHT_POS)) /**< CTRL_ODHT Mask */
100 
101  #define MXC_F_TRNG_REVB_CTRL_RND_IE_POS                1 /**< CTRL_RND_IE Position */
102  #define MXC_F_TRNG_REVB_CTRL_RND_IE                    ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */
103 
104  #define MXC_F_TRNG_REVB_CTRL_HEALTH_EN_POS             2 /**< CTRL_HEALTH_EN Position */
105  #define MXC_F_TRNG_REVB_CTRL_HEALTH_EN                 ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_HEALTH_EN_POS)) /**< CTRL_HEALTH_EN Mask */
106 
107  #define MXC_F_TRNG_REVB_CTRL_AESKG_USR_POS             3 /**< CTRL_AESKG_USR Position */
108  #define MXC_F_TRNG_REVB_CTRL_AESKG_USR                 ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_AESKG_USR_POS)) /**< CTRL_AESKG_USR Mask */
109 
110  #define MXC_F_TRNG_REVB_CTRL_AESKG_SYS_POS             4 /**< CTRL_AESKG_SYS Position */
111  #define MXC_F_TRNG_REVB_CTRL_AESKG_SYS                 ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_AESKG_SYS_POS)) /**< CTRL_AESKG_SYS Mask */
112 
113  #define MXC_F_TRNG_REVB_CTRL_KEYWIPE_POS               15 /**< CTRL_KEYWIPE Position */
114  #define MXC_F_TRNG_REVB_CTRL_KEYWIPE                   ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */
115 
116 /**@} end of group TRNG_REVB_CTRL_Register */
117 
118 /**
119  * @ingroup  trng_revb_registers
120  * @defgroup TRNG_REVB_STATUS TRNG_REVB_STATUS
121  * @brief    Data. The content of this register is valid only when RNG_IS = 1. When TRNG is
122  *           disabled, read returns 0x0000 0000.
123  * @{
124  */
125  #define MXC_F_TRNG_REVB_STATUS_RDY_POS                 0 /**< STATUS_RDY Position */
126  #define MXC_F_TRNG_REVB_STATUS_RDY                     ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_STATUS_RDY_POS)) /**< STATUS_RDY Mask */
127 
128  #define MXC_F_TRNG_REVB_STATUS_ODHT_POS                1 /**< STATUS_ODHT Position */
129  #define MXC_F_TRNG_REVB_STATUS_ODHT                    ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_STATUS_ODHT_POS)) /**< STATUS_ODHT Mask */
130 
131  #define MXC_F_TRNG_REVB_STATUS_HT_POS                  2 /**< STATUS_HT Position */
132  #define MXC_F_TRNG_REVB_STATUS_HT                      ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_STATUS_HT_POS)) /**< STATUS_HT Mask */
133 
134  #define MXC_F_TRNG_REVB_STATUS_SRCFAIL_POS             3 /**< STATUS_SRCFAIL Position */
135  #define MXC_F_TRNG_REVB_STATUS_SRCFAIL                 ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_STATUS_SRCFAIL_POS)) /**< STATUS_SRCFAIL Mask */
136 
137  #define MXC_F_TRNG_REVB_STATUS_AESKGD_POS              4 /**< STATUS_AESKGD Position */
138  #define MXC_F_TRNG_REVB_STATUS_AESKGD                  ((uint32_t)(0x1UL << MXC_F_TRNG_REVB_STATUS_AESKGD_POS)) /**< STATUS_AESKGD Mask */
139 
140  #define MXC_F_TRNG_REVB_STATUS_LD_CNT_POS              24 /**< STATUS_LD_CNT Position */
141  #define MXC_F_TRNG_REVB_STATUS_LD_CNT                  ((uint32_t)(0xFFUL << MXC_F_TRNG_REVB_STATUS_LD_CNT_POS)) /**< STATUS_LD_CNT Mask */
142 
143 /**@} end of group TRNG_REVB_STATUS_Register */
144 
145 /**
146  * @ingroup  trng_revb_registers
147  * @defgroup TRNG_REVB_DATA TRNG_REVB_DATA
148  * @brief    Data. The content of this register is valid only when RNG_IS = 1. When TRNG is
149  *           disabled, read returns 0x0000 0000.
150  * @{
151  */
152  #define MXC_F_TRNG_REVB_DATA_DATA_POS                  0 /**< DATA_DATA Position */
153  #define MXC_F_TRNG_REVB_DATA_DATA                      ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_REVB_DATA_DATA_POS)) /**< DATA_DATA Mask */
154 
155 /**@} end of group TRNG_REVB_DATA_Register */
156 
157 #ifdef __cplusplus
158 }
159 #endif
160 
161 #endif /* _TRNG_REVB_REGS_H_ */
162