1 /** 2 * @file tpu_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the TPU_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _TPU_REVA_REGS_H_ 27 #define _TPU_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup tpu_reva 65 * @defgroup tpu_reva_registers TPU_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the TPU_REVA Peripheral Module. 67 * @details The Trust Protection Unit used to assist the computationally intensive operations of several common cryptographic algorithms. 68 */ 69 70 /** 71 * @ingroup tpu_reva_registers 72 * Structure type to access the TPU_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> TPU_REVA CTRL Register */ 76 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> TPU_REVA CIPHER_CTRL Register */ 77 __IO uint32_t hash_ctrl; /**< <tt>\b 0x08:</tt> TPU_REVA HASH_CTRL Register */ 78 __IO uint32_t crc_ctrl; /**< <tt>\b 0x0C:</tt> TPU_REVA CRC_CTRL Register */ 79 __IO uint32_t dma_src; /**< <tt>\b 0x10:</tt> TPU_REVA DMA_SRC Register */ 80 __IO uint32_t dma_dst; /**< <tt>\b 0x14:</tt> TPU_REVA DMA_DST Register */ 81 __IO uint32_t dma_cnt; /**< <tt>\b 0x18:</tt> TPU_REVA DMA_CNT Register */ 82 __IO uint32_t maa_ctrl; /**< <tt>\b 0x1C:</tt> TPU_REVA MAA_CTRL Register */ 83 __O uint32_t data_in[4]; /**< <tt>\b 0x20:</tt> TPU_REVA DATA_IN Register */ 84 __I uint32_t data_out[4]; /**< <tt>\b 0x30:</tt> TPU_REVA DATA_OUT Register */ 85 __IO uint32_t crc_poly; /**< <tt>\b 0x40:</tt> TPU_REVA CRC_POLY Register */ 86 __IO uint32_t crc_val; /**< <tt>\b 0x44:</tt> TPU_REVA CRC_VAL Register */ 87 __I uint32_t crc_prng; /**< <tt>\b 0x48:</tt> TPU_REVA CRC_PRNG Register */ 88 __IO uint32_t ham_ecc; /**< <tt>\b 0x4C:</tt> TPU_REVA HAM_ECC Register */ 89 __IO uint32_t cipher_init[4]; /**< <tt>\b 0x50:</tt> TPU_REVA CIPHER_INIT Register */ 90 __O uint32_t cipher_key[8]; /**< <tt>\b 0x60:</tt> TPU_REVA CIPHER_KEY Register */ 91 __IO uint32_t hash_digest[16]; /**< <tt>\b 0x80:</tt> TPU_REVA HASH_DIGEST Register */ 92 __IO uint32_t hash_msg_sz[4]; /**< <tt>\b 0xC0:</tt> TPU_REVA HASH_MSG_SZ Register */ 93 __IO uint32_t maa_maws; /**< <tt>\b 0xD0:</tt> TPU_REVA MAA_MAWS Register */ 94 } mxc_tpu_reva_regs_t; 95 96 /* Register offsets for module TPU_REVA */ 97 /** 98 * @ingroup tpu_reva_registers 99 * @defgroup TPU_REVA_Register_Offsets Register Offsets 100 * @brief TPU_REVA Peripheral Register Offsets from the TPU_REVA Base Peripheral Address. 101 * @{ 102 */ 103 #define MXC_R_TPU_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_TPU_REVA_CIPHER_CTRL ((uint32_t)0x00000004UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0004</tt> */ 105 #define MXC_R_TPU_REVA_HASH_CTRL ((uint32_t)0x00000008UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0008</tt> */ 106 #define MXC_R_TPU_REVA_CRC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from TPU_REVA Base Address: <tt> 0x000C</tt> */ 107 #define MXC_R_TPU_REVA_DMA_SRC ((uint32_t)0x00000010UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0010</tt> */ 108 #define MXC_R_TPU_REVA_DMA_DST ((uint32_t)0x00000014UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0014</tt> */ 109 #define MXC_R_TPU_REVA_DMA_CNT ((uint32_t)0x00000018UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0018</tt> */ 110 #define MXC_R_TPU_REVA_MAA_CTRL ((uint32_t)0x0000001CUL) /**< Offset from TPU_REVA Base Address: <tt> 0x001C</tt> */ 111 #define MXC_R_TPU_REVA_DATA_IN ((uint32_t)0x00000020UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0020</tt> */ 112 #define MXC_R_TPU_REVA_DATA_OUT ((uint32_t)0x00000030UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0030</tt> */ 113 #define MXC_R_TPU_REVA_CRC_POLY ((uint32_t)0x00000040UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0040</tt> */ 114 #define MXC_R_TPU_REVA_CRC_VAL ((uint32_t)0x00000044UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0044</tt> */ 115 #define MXC_R_TPU_REVA_CRC_PRNG ((uint32_t)0x00000048UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0048</tt> */ 116 #define MXC_R_TPU_REVA_HAM_ECC ((uint32_t)0x0000004CUL) /**< Offset from TPU_REVA Base Address: <tt> 0x004C</tt> */ 117 #define MXC_R_TPU_REVA_CIPHER_INIT ((uint32_t)0x00000050UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0050</tt> */ 118 #define MXC_R_TPU_REVA_CIPHER_KEY ((uint32_t)0x00000060UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0060</tt> */ 119 #define MXC_R_TPU_REVA_HASH_DIGEST ((uint32_t)0x00000080UL) /**< Offset from TPU_REVA Base Address: <tt> 0x0080</tt> */ 120 #define MXC_R_TPU_REVA_HASH_MSG_SZ ((uint32_t)0x000000C0UL) /**< Offset from TPU_REVA Base Address: <tt> 0x00C0</tt> */ 121 #define MXC_R_TPU_REVA_MAA_MAWS ((uint32_t)0x000000D0UL) /**< Offset from TPU_REVA Base Address: <tt> 0x00D0</tt> */ 122 /**@} end of group tpu_reva_registers */ 123 124 /** 125 * @ingroup tpu_reva_registers 126 * @defgroup TPU_REVA_CTRL TPU_REVA_CTRL 127 * @brief Crypto Control Register. 128 * @{ 129 */ 130 #define MXC_F_TPU_REVA_CTRL_RST_POS 0 /**< CTRL_RST Position */ 131 #define MXC_F_TPU_REVA_CTRL_RST ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_RST_POS)) /**< CTRL_RST Mask */ 132 133 #define MXC_F_TPU_REVA_CTRL_INT_POS 1 /**< CTRL_INT Position */ 134 #define MXC_F_TPU_REVA_CTRL_INT ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_INT_POS)) /**< CTRL_INT Mask */ 135 136 #define MXC_F_TPU_REVA_CTRL_SRC_POS 2 /**< CTRL_SRC Position */ 137 #define MXC_F_TPU_REVA_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_SRC_POS)) /**< CTRL_SRC Mask */ 138 139 #define MXC_F_TPU_REVA_CTRL_BSO_POS 4 /**< CTRL_BSO Position */ 140 #define MXC_F_TPU_REVA_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_BSO_POS)) /**< CTRL_BSO Mask */ 141 142 #define MXC_F_TPU_REVA_CTRL_BSI_POS 5 /**< CTRL_BSI Position */ 143 #define MXC_F_TPU_REVA_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_BSI_POS)) /**< CTRL_BSI Mask */ 144 145 #define MXC_F_TPU_REVA_CTRL_WAIT_EN_POS 6 /**< CTRL_WAIT_EN Position */ 146 #define MXC_F_TPU_REVA_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_WAIT_EN_POS)) /**< CTRL_WAIT_EN Mask */ 147 148 #define MXC_F_TPU_REVA_CTRL_WAIT_POL_POS 7 /**< CTRL_WAIT_POL Position */ 149 #define MXC_F_TPU_REVA_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_WAIT_POL_POS)) /**< CTRL_WAIT_POL Mask */ 150 151 #define MXC_F_TPU_REVA_CTRL_WRSRC_POS 8 /**< CTRL_WRSRC Position */ 152 #define MXC_F_TPU_REVA_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_TPU_REVA_CTRL_WRSRC_POS)) /**< CTRL_WRSRC Mask */ 153 #define MXC_V_TPU_REVA_CTRL_WRSRC_NONE ((uint32_t)0x0UL) /**< CTRL_WRSRC_NONE Value */ 154 #define MXC_S_TPU_REVA_CTRL_WRSRC_NONE (MXC_V_TPU_REVA_CTRL_WRSRC_NONE << MXC_F_TPU_REVA_CTRL_WRSRC_POS) /**< CTRL_WRSRC_NONE Setting */ 155 #define MXC_V_TPU_REVA_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL) /**< CTRL_WRSRC_CIPHEROUTPUT Value */ 156 #define MXC_S_TPU_REVA_CTRL_WRSRC_CIPHEROUTPUT (MXC_V_TPU_REVA_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_TPU_REVA_CTRL_WRSRC_POS) /**< CTRL_WRSRC_CIPHEROUTPUT Setting */ 157 #define MXC_V_TPU_REVA_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL) /**< CTRL_WRSRC_READFIFO Value */ 158 #define MXC_S_TPU_REVA_CTRL_WRSRC_READFIFO (MXC_V_TPU_REVA_CTRL_WRSRC_READFIFO << MXC_F_TPU_REVA_CTRL_WRSRC_POS) /**< CTRL_WRSRC_READFIFO Setting */ 159 160 #define MXC_F_TPU_REVA_CTRL_RDSRC_POS 10 /**< CTRL_RDSRC Position */ 161 #define MXC_F_TPU_REVA_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_TPU_REVA_CTRL_RDSRC_POS)) /**< CTRL_RDSRC Mask */ 162 #define MXC_V_TPU_REVA_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL) /**< CTRL_RDSRC_DMADISABLED Value */ 163 #define MXC_S_TPU_REVA_CTRL_RDSRC_DMADISABLED (MXC_V_TPU_REVA_CTRL_RDSRC_DMADISABLED << MXC_F_TPU_REVA_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMADISABLED Setting */ 164 #define MXC_V_TPU_REVA_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL) /**< CTRL_RDSRC_DMAORAPB Value */ 165 #define MXC_S_TPU_REVA_CTRL_RDSRC_DMAORAPB (MXC_V_TPU_REVA_CTRL_RDSRC_DMAORAPB << MXC_F_TPU_REVA_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMAORAPB Setting */ 166 #define MXC_V_TPU_REVA_CTRL_RDSRC_RNG ((uint32_t)0x2UL) /**< CTRL_RDSRC_RNG Value */ 167 #define MXC_S_TPU_REVA_CTRL_RDSRC_RNG (MXC_V_TPU_REVA_CTRL_RDSRC_RNG << MXC_F_TPU_REVA_CTRL_RDSRC_POS) /**< CTRL_RDSRC_RNG Setting */ 168 169 #define MXC_F_TPU_REVA_CTRL_FLAG_MODE_POS 14 /**< CTRL_FLAG_MODE Position */ 170 #define MXC_F_TPU_REVA_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_FLAG_MODE_POS)) /**< CTRL_FLAG_MODE Mask */ 171 172 #define MXC_F_TPU_REVA_CTRL_DMADNE_MSK_POS 15 /**< CTRL_DMADNE_MSK Position */ 173 #define MXC_F_TPU_REVA_CTRL_DMADNE_MSK ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_DMADNE_MSK_POS)) /**< CTRL_DMADNE_MSK Mask */ 174 175 #define MXC_F_TPU_REVA_CTRL_DMA_DONE_POS 24 /**< CTRL_DMA_DONE Position */ 176 #define MXC_F_TPU_REVA_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_DMA_DONE_POS)) /**< CTRL_DMA_DONE Mask */ 177 178 #define MXC_F_TPU_REVA_CTRL_GLS_DONE_POS 25 /**< CTRL_GLS_DONE Position */ 179 #define MXC_F_TPU_REVA_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_GLS_DONE_POS)) /**< CTRL_GLS_DONE Mask */ 180 181 #define MXC_F_TPU_REVA_CTRL_HSH_DONE_POS 26 /**< CTRL_HSH_DONE Position */ 182 #define MXC_F_TPU_REVA_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_HSH_DONE_POS)) /**< CTRL_HSH_DONE Mask */ 183 184 #define MXC_F_TPU_REVA_CTRL_CPH_DONE_POS 27 /**< CTRL_CPH_DONE Position */ 185 #define MXC_F_TPU_REVA_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_CPH_DONE_POS)) /**< CTRL_CPH_DONE Mask */ 186 187 #define MXC_F_TPU_REVA_CTRL_MAA_DONE_POS 28 /**< CTRL_MAA_DONE Position */ 188 #define MXC_F_TPU_REVA_CTRL_MAA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_MAA_DONE_POS)) /**< CTRL_MAA_DONE Mask */ 189 190 #define MXC_F_TPU_REVA_CTRL_ERR_POS 29 /**< CTRL_ERR Position */ 191 #define MXC_F_TPU_REVA_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_ERR_POS)) /**< CTRL_ERR Mask */ 192 193 #define MXC_F_TPU_REVA_CTRL_RDY_POS 30 /**< CTRL_RDY Position */ 194 #define MXC_F_TPU_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 195 196 #define MXC_F_TPU_REVA_CTRL_DONE_POS 31 /**< CTRL_DONE Position */ 197 #define MXC_F_TPU_REVA_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CTRL_DONE_POS)) /**< CTRL_DONE Mask */ 198 199 /**@} end of group TPU_REVA_CTRL_Register */ 200 201 /** 202 * @ingroup tpu_reva_registers 203 * @defgroup TPU_REVA_CIPHER_CTRL TPU_REVA_CIPHER_CTRL 204 * @brief Cipher Control Register. 205 * @{ 206 */ 207 #define MXC_F_TPU_REVA_CIPHER_CTRL_ENC_POS 0 /**< CIPHER_CTRL_ENC Position */ 208 #define MXC_F_TPU_REVA_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CIPHER_CTRL_ENC_POS)) /**< CIPHER_CTRL_ENC Mask */ 209 210 #define MXC_F_TPU_REVA_CIPHER_CTRL_KEY_POS 1 /**< CIPHER_CTRL_KEY Position */ 211 #define MXC_F_TPU_REVA_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CIPHER_CTRL_KEY_POS)) /**< CIPHER_CTRL_KEY Mask */ 212 213 #define MXC_F_TPU_REVA_CIPHER_CTRL_SRC_POS 2 /**< CIPHER_CTRL_SRC Position */ 214 #define MXC_F_TPU_REVA_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_TPU_REVA_CIPHER_CTRL_SRC_POS)) /**< CIPHER_CTRL_SRC Mask */ 215 #define MXC_V_TPU_REVA_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL) /**< CIPHER_CTRL_SRC_CIPHERKEY Value */ 216 #define MXC_S_TPU_REVA_CIPHER_CTRL_SRC_CIPHERKEY (MXC_V_TPU_REVA_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_TPU_REVA_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_CIPHERKEY Setting */ 217 #define MXC_V_TPU_REVA_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL) /**< CIPHER_CTRL_SRC_REGFILE Value */ 218 #define MXC_S_TPU_REVA_CIPHER_CTRL_SRC_REGFILE (MXC_V_TPU_REVA_CIPHER_CTRL_SRC_REGFILE << MXC_F_TPU_REVA_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_REGFILE Setting */ 219 #define MXC_V_TPU_REVA_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Value */ 220 #define MXC_S_TPU_REVA_CIPHER_CTRL_SRC_QSPIKEY_REGFILE (MXC_V_TPU_REVA_CIPHER_CTRL_SRC_QSPIKEY_REGFILE << MXC_F_TPU_REVA_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Setting */ 221 222 #define MXC_F_TPU_REVA_CIPHER_CTRL_CIPHER_POS 4 /**< CIPHER_CTRL_CIPHER Position */ 223 #define MXC_F_TPU_REVA_CIPHER_CTRL_CIPHER ((uint32_t)(0x7UL << MXC_F_TPU_REVA_CIPHER_CTRL_CIPHER_POS)) /**< CIPHER_CTRL_CIPHER Mask */ 224 #define MXC_V_TPU_REVA_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL) /**< CIPHER_CTRL_CIPHER_DIS Value */ 225 #define MXC_S_TPU_REVA_CIPHER_CTRL_CIPHER_DIS (MXC_V_TPU_REVA_CIPHER_CTRL_CIPHER_DIS << MXC_F_TPU_REVA_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DIS Setting */ 226 #define MXC_V_TPU_REVA_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL) /**< CIPHER_CTRL_CIPHER_AES128 Value */ 227 #define MXC_S_TPU_REVA_CIPHER_CTRL_CIPHER_AES128 (MXC_V_TPU_REVA_CIPHER_CTRL_CIPHER_AES128 << MXC_F_TPU_REVA_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES128 Setting */ 228 #define MXC_V_TPU_REVA_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL) /**< CIPHER_CTRL_CIPHER_AES192 Value */ 229 #define MXC_S_TPU_REVA_CIPHER_CTRL_CIPHER_AES192 (MXC_V_TPU_REVA_CIPHER_CTRL_CIPHER_AES192 << MXC_F_TPU_REVA_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES192 Setting */ 230 #define MXC_V_TPU_REVA_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL) /**< CIPHER_CTRL_CIPHER_AES256 Value */ 231 #define MXC_S_TPU_REVA_CIPHER_CTRL_CIPHER_AES256 (MXC_V_TPU_REVA_CIPHER_CTRL_CIPHER_AES256 << MXC_F_TPU_REVA_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES256 Setting */ 232 #define MXC_V_TPU_REVA_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL) /**< CIPHER_CTRL_CIPHER_DES Value */ 233 #define MXC_S_TPU_REVA_CIPHER_CTRL_CIPHER_DES (MXC_V_TPU_REVA_CIPHER_CTRL_CIPHER_DES << MXC_F_TPU_REVA_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DES Setting */ 234 #define MXC_V_TPU_REVA_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL) /**< CIPHER_CTRL_CIPHER_TDES Value */ 235 #define MXC_S_TPU_REVA_CIPHER_CTRL_CIPHER_TDES (MXC_V_TPU_REVA_CIPHER_CTRL_CIPHER_TDES << MXC_F_TPU_REVA_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_TDES Setting */ 236 237 #define MXC_F_TPU_REVA_CIPHER_CTRL_MODE_POS 8 /**< CIPHER_CTRL_MODE Position */ 238 #define MXC_F_TPU_REVA_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_TPU_REVA_CIPHER_CTRL_MODE_POS)) /**< CIPHER_CTRL_MODE Mask */ 239 #define MXC_V_TPU_REVA_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL) /**< CIPHER_CTRL_MODE_ECB Value */ 240 #define MXC_S_TPU_REVA_CIPHER_CTRL_MODE_ECB (MXC_V_TPU_REVA_CIPHER_CTRL_MODE_ECB << MXC_F_TPU_REVA_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_ECB Setting */ 241 #define MXC_V_TPU_REVA_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL) /**< CIPHER_CTRL_MODE_CBC Value */ 242 #define MXC_S_TPU_REVA_CIPHER_CTRL_MODE_CBC (MXC_V_TPU_REVA_CIPHER_CTRL_MODE_CBC << MXC_F_TPU_REVA_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CBC Setting */ 243 #define MXC_V_TPU_REVA_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL) /**< CIPHER_CTRL_MODE_CFB Value */ 244 #define MXC_S_TPU_REVA_CIPHER_CTRL_MODE_CFB (MXC_V_TPU_REVA_CIPHER_CTRL_MODE_CFB << MXC_F_TPU_REVA_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CFB Setting */ 245 #define MXC_V_TPU_REVA_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL) /**< CIPHER_CTRL_MODE_OFB Value */ 246 #define MXC_S_TPU_REVA_CIPHER_CTRL_MODE_OFB (MXC_V_TPU_REVA_CIPHER_CTRL_MODE_OFB << MXC_F_TPU_REVA_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_OFB Setting */ 247 #define MXC_V_TPU_REVA_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL) /**< CIPHER_CTRL_MODE_CTR Value */ 248 #define MXC_S_TPU_REVA_CIPHER_CTRL_MODE_CTR (MXC_V_TPU_REVA_CIPHER_CTRL_MODE_CTR << MXC_F_TPU_REVA_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CTR Setting */ 249 250 /**@} end of group TPU_REVA_CIPHER_CTRL_Register */ 251 252 /** 253 * @ingroup tpu_reva_registers 254 * @defgroup TPU_REVA_HASH_CTRL TPU_REVA_HASH_CTRL 255 * @brief HASH Control Register. 256 * @{ 257 */ 258 #define MXC_F_TPU_REVA_HASH_CTRL_INIT_POS 0 /**< HASH_CTRL_INIT Position */ 259 #define MXC_F_TPU_REVA_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_TPU_REVA_HASH_CTRL_INIT_POS)) /**< HASH_CTRL_INIT Mask */ 260 261 #define MXC_F_TPU_REVA_HASH_CTRL_XOR_POS 1 /**< HASH_CTRL_XOR Position */ 262 #define MXC_F_TPU_REVA_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_TPU_REVA_HASH_CTRL_XOR_POS)) /**< HASH_CTRL_XOR Mask */ 263 264 #define MXC_F_TPU_REVA_HASH_CTRL_HASH_POS 2 /**< HASH_CTRL_HASH Position */ 265 #define MXC_F_TPU_REVA_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_TPU_REVA_HASH_CTRL_HASH_POS)) /**< HASH_CTRL_HASH Mask */ 266 #define MXC_V_TPU_REVA_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL) /**< HASH_CTRL_HASH_DIS Value */ 267 #define MXC_S_TPU_REVA_HASH_CTRL_HASH_DIS (MXC_V_TPU_REVA_HASH_CTRL_HASH_DIS << MXC_F_TPU_REVA_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_DIS Setting */ 268 #define MXC_V_TPU_REVA_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL) /**< HASH_CTRL_HASH_SHA1 Value */ 269 #define MXC_S_TPU_REVA_HASH_CTRL_HASH_SHA1 (MXC_V_TPU_REVA_HASH_CTRL_HASH_SHA1 << MXC_F_TPU_REVA_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA1 Setting */ 270 #define MXC_V_TPU_REVA_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL) /**< HASH_CTRL_HASH_SHA224 Value */ 271 #define MXC_S_TPU_REVA_HASH_CTRL_HASH_SHA224 (MXC_V_TPU_REVA_HASH_CTRL_HASH_SHA224 << MXC_F_TPU_REVA_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA224 Setting */ 272 #define MXC_V_TPU_REVA_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL) /**< HASH_CTRL_HASH_SHA256 Value */ 273 #define MXC_S_TPU_REVA_HASH_CTRL_HASH_SHA256 (MXC_V_TPU_REVA_HASH_CTRL_HASH_SHA256 << MXC_F_TPU_REVA_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA256 Setting */ 274 #define MXC_V_TPU_REVA_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL) /**< HASH_CTRL_HASH_SHA384 Value */ 275 #define MXC_S_TPU_REVA_HASH_CTRL_HASH_SHA384 (MXC_V_TPU_REVA_HASH_CTRL_HASH_SHA384 << MXC_F_TPU_REVA_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA384 Setting */ 276 #define MXC_V_TPU_REVA_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL) /**< HASH_CTRL_HASH_SHA512 Value */ 277 #define MXC_S_TPU_REVA_HASH_CTRL_HASH_SHA512 (MXC_V_TPU_REVA_HASH_CTRL_HASH_SHA512 << MXC_F_TPU_REVA_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA512 Setting */ 278 279 #define MXC_F_TPU_REVA_HASH_CTRL_LAST_POS 5 /**< HASH_CTRL_LAST Position */ 280 #define MXC_F_TPU_REVA_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_TPU_REVA_HASH_CTRL_LAST_POS)) /**< HASH_CTRL_LAST Mask */ 281 282 /**@} end of group TPU_REVA_HASH_CTRL_Register */ 283 284 /** 285 * @ingroup tpu_reva_registers 286 * @defgroup TPU_REVA_CRC_CTRL TPU_REVA_CRC_CTRL 287 * @brief CRC Control Register. 288 * @{ 289 */ 290 #define MXC_F_TPU_REVA_CRC_CTRL_CRC_EN_POS 0 /**< CRC_CTRL_CRC_EN Position */ 291 #define MXC_F_TPU_REVA_CRC_CTRL_CRC_EN ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CRC_CTRL_CRC_EN_POS)) /**< CRC_CTRL_CRC_EN Mask */ 292 293 #define MXC_F_TPU_REVA_CRC_CTRL_MSB_POS 1 /**< CRC_CTRL_MSB Position */ 294 #define MXC_F_TPU_REVA_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CRC_CTRL_MSB_POS)) /**< CRC_CTRL_MSB Mask */ 295 296 #define MXC_F_TPU_REVA_CRC_CTRL_PRNG_POS 2 /**< CRC_CTRL_PRNG Position */ 297 #define MXC_F_TPU_REVA_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CRC_CTRL_PRNG_POS)) /**< CRC_CTRL_PRNG Mask */ 298 299 #define MXC_F_TPU_REVA_CRC_CTRL_ENT_POS 3 /**< CRC_CTRL_ENT Position */ 300 #define MXC_F_TPU_REVA_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CRC_CTRL_ENT_POS)) /**< CRC_CTRL_ENT Mask */ 301 302 #define MXC_F_TPU_REVA_CRC_CTRL_HAM_POS 4 /**< CRC_CTRL_HAM Position */ 303 #define MXC_F_TPU_REVA_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CRC_CTRL_HAM_POS)) /**< CRC_CTRL_HAM Mask */ 304 305 #define MXC_F_TPU_REVA_CRC_CTRL_HRST_POS 5 /**< CRC_CTRL_HRST Position */ 306 #define MXC_F_TPU_REVA_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_TPU_REVA_CRC_CTRL_HRST_POS)) /**< CRC_CTRL_HRST Mask */ 307 308 /**@} end of group TPU_REVA_CRC_CTRL_Register */ 309 310 /** 311 * @ingroup tpu_reva_registers 312 * @defgroup TPU_REVA_DMA_SRC TPU_REVA_DMA_SRC 313 * @brief Crypto DMA Source Address. 314 * @{ 315 */ 316 #define MXC_F_TPU_REVA_DMA_SRC_SRC_ADDR_POS 0 /**< DMA_SRC_SRC_ADDR Position */ 317 #define MXC_F_TPU_REVA_DMA_SRC_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_REVA_DMA_SRC_SRC_ADDR_POS)) /**< DMA_SRC_SRC_ADDR Mask */ 318 319 /**@} end of group TPU_REVA_DMA_SRC_Register */ 320 321 /** 322 * @ingroup tpu_reva_registers 323 * @defgroup TPU_REVA_DMA_DST TPU_REVA_DMA_DST 324 * @brief Crypto DMA Destination Address. 325 * @{ 326 */ 327 #define MXC_F_TPU_REVA_DMA_DST_DST_ADDR_POS 0 /**< DMA_DST_DST_ADDR Position */ 328 #define MXC_F_TPU_REVA_DMA_DST_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_REVA_DMA_DST_DST_ADDR_POS)) /**< DMA_DST_DST_ADDR Mask */ 329 330 /**@} end of group TPU_REVA_DMA_DST_Register */ 331 332 /** 333 * @ingroup tpu_reva_registers 334 * @defgroup TPU_REVA_DMA_CNT TPU_REVA_DMA_CNT 335 * @brief Crypto DMA Byte Count. 336 * @{ 337 */ 338 #define MXC_F_TPU_REVA_DMA_CNT_COUNT_POS 0 /**< DMA_CNT_COUNT Position */ 339 #define MXC_F_TPU_REVA_DMA_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_REVA_DMA_CNT_COUNT_POS)) /**< DMA_CNT_COUNT Mask */ 340 341 /**@} end of group TPU_REVA_DMA_CNT_Register */ 342 343 /** 344 * @ingroup tpu_reva_registers 345 * @defgroup TPU_REVA_MAA_CTRL TPU_REVA_MAA_CTRL 346 * @brief MAA Control Register. 347 * @{ 348 */ 349 #define MXC_F_TPU_REVA_MAA_CTRL_STC_POS 0 /**< MAA_CTRL_STC Position */ 350 #define MXC_F_TPU_REVA_MAA_CTRL_STC ((uint32_t)(0x1UL << MXC_F_TPU_REVA_MAA_CTRL_STC_POS)) /**< MAA_CTRL_STC Mask */ 351 352 #define MXC_F_TPU_REVA_MAA_CTRL_CLC_POS 1 /**< MAA_CTRL_CLC Position */ 353 #define MXC_F_TPU_REVA_MAA_CTRL_CLC ((uint32_t)(0x7UL << MXC_F_TPU_REVA_MAA_CTRL_CLC_POS)) /**< MAA_CTRL_CLC Mask */ 354 #define MXC_V_TPU_REVA_MAA_CTRL_CLC_EXP ((uint32_t)0x0UL) /**< MAA_CTRL_CLC_EXP Value */ 355 #define MXC_S_TPU_REVA_MAA_CTRL_CLC_EXP (MXC_V_TPU_REVA_MAA_CTRL_CLC_EXP << MXC_F_TPU_REVA_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_EXP Setting */ 356 #define MXC_V_TPU_REVA_MAA_CTRL_CLC_SQ ((uint32_t)0x1UL) /**< MAA_CTRL_CLC_SQ Value */ 357 #define MXC_S_TPU_REVA_MAA_CTRL_CLC_SQ (MXC_V_TPU_REVA_MAA_CTRL_CLC_SQ << MXC_F_TPU_REVA_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SQ Setting */ 358 #define MXC_V_TPU_REVA_MAA_CTRL_CLC_MUL ((uint32_t)0x2UL) /**< MAA_CTRL_CLC_MUL Value */ 359 #define MXC_S_TPU_REVA_MAA_CTRL_CLC_MUL (MXC_V_TPU_REVA_MAA_CTRL_CLC_MUL << MXC_F_TPU_REVA_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_MUL Setting */ 360 #define MXC_V_TPU_REVA_MAA_CTRL_CLC_SQMUL ((uint32_t)0x3UL) /**< MAA_CTRL_CLC_SQMUL Value */ 361 #define MXC_S_TPU_REVA_MAA_CTRL_CLC_SQMUL (MXC_V_TPU_REVA_MAA_CTRL_CLC_SQMUL << MXC_F_TPU_REVA_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SQMUL Setting */ 362 #define MXC_V_TPU_REVA_MAA_CTRL_CLC_ADD ((uint32_t)0x4UL) /**< MAA_CTRL_CLC_ADD Value */ 363 #define MXC_S_TPU_REVA_MAA_CTRL_CLC_ADD (MXC_V_TPU_REVA_MAA_CTRL_CLC_ADD << MXC_F_TPU_REVA_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_ADD Setting */ 364 #define MXC_V_TPU_REVA_MAA_CTRL_CLC_SUB ((uint32_t)0x5UL) /**< MAA_CTRL_CLC_SUB Value */ 365 #define MXC_S_TPU_REVA_MAA_CTRL_CLC_SUB (MXC_V_TPU_REVA_MAA_CTRL_CLC_SUB << MXC_F_TPU_REVA_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SUB Setting */ 366 367 #define MXC_F_TPU_REVA_MAA_CTRL_OCALC_POS 4 /**< MAA_CTRL_OCALC Position */ 368 #define MXC_F_TPU_REVA_MAA_CTRL_OCALC ((uint32_t)(0x1UL << MXC_F_TPU_REVA_MAA_CTRL_OCALC_POS)) /**< MAA_CTRL_OCALC Mask */ 369 370 #define MXC_F_TPU_REVA_MAA_CTRL_MAAER_POS 7 /**< MAA_CTRL_MAAER Position */ 371 #define MXC_F_TPU_REVA_MAA_CTRL_MAAER ((uint32_t)(0x1UL << MXC_F_TPU_REVA_MAA_CTRL_MAAER_POS)) /**< MAA_CTRL_MAAER Mask */ 372 373 #define MXC_F_TPU_REVA_MAA_CTRL_AMS_POS 8 /**< MAA_CTRL_AMS Position */ 374 #define MXC_F_TPU_REVA_MAA_CTRL_AMS ((uint32_t)(0x3UL << MXC_F_TPU_REVA_MAA_CTRL_AMS_POS)) /**< MAA_CTRL_AMS Mask */ 375 376 #define MXC_F_TPU_REVA_MAA_CTRL_BMS_POS 10 /**< MAA_CTRL_BMS Position */ 377 #define MXC_F_TPU_REVA_MAA_CTRL_BMS ((uint32_t)(0x3UL << MXC_F_TPU_REVA_MAA_CTRL_BMS_POS)) /**< MAA_CTRL_BMS Mask */ 378 379 #define MXC_F_TPU_REVA_MAA_CTRL_EMS_POS 12 /**< MAA_CTRL_EMS Position */ 380 #define MXC_F_TPU_REVA_MAA_CTRL_EMS ((uint32_t)(0x3UL << MXC_F_TPU_REVA_MAA_CTRL_EMS_POS)) /**< MAA_CTRL_EMS Mask */ 381 382 #define MXC_F_TPU_REVA_MAA_CTRL_MMS_POS 14 /**< MAA_CTRL_MMS Position */ 383 #define MXC_F_TPU_REVA_MAA_CTRL_MMS ((uint32_t)(0x3UL << MXC_F_TPU_REVA_MAA_CTRL_MMS_POS)) /**< MAA_CTRL_MMS Mask */ 384 385 #define MXC_F_TPU_REVA_MAA_CTRL_AMA_POS 16 /**< MAA_CTRL_AMA Position */ 386 #define MXC_F_TPU_REVA_MAA_CTRL_AMA ((uint32_t)(0xFUL << MXC_F_TPU_REVA_MAA_CTRL_AMA_POS)) /**< MAA_CTRL_AMA Mask */ 387 388 #define MXC_F_TPU_REVA_MAA_CTRL_BMA_POS 20 /**< MAA_CTRL_BMA Position */ 389 #define MXC_F_TPU_REVA_MAA_CTRL_BMA ((uint32_t)(0xFUL << MXC_F_TPU_REVA_MAA_CTRL_BMA_POS)) /**< MAA_CTRL_BMA Mask */ 390 391 #define MXC_F_TPU_REVA_MAA_CTRL_RMA_POS 24 /**< MAA_CTRL_RMA Position */ 392 #define MXC_F_TPU_REVA_MAA_CTRL_RMA ((uint32_t)(0xFUL << MXC_F_TPU_REVA_MAA_CTRL_RMA_POS)) /**< MAA_CTRL_RMA Mask */ 393 394 #define MXC_F_TPU_REVA_MAA_CTRL_TMA_POS 28 /**< MAA_CTRL_TMA Position */ 395 #define MXC_F_TPU_REVA_MAA_CTRL_TMA ((uint32_t)(0xFUL << MXC_F_TPU_REVA_MAA_CTRL_TMA_POS)) /**< MAA_CTRL_TMA Mask */ 396 397 /**@} end of group TPU_REVA_MAA_CTRL_Register */ 398 399 /** 400 * @ingroup tpu_reva_registers 401 * @defgroup TPU_REVA_DATA_IN TPU_REVA_DATA_IN 402 * @brief Crypto Data Input. Data input can be written to this register instead of using 403 * the DMA. This register writes to the FIFO. This register occupies four 404 * successive words to allow the use of multi-store instructions. Words can be 405 * written to any location, they will be placed in the FIFO in the order they are 406 * written. The endian swap input control bit affects this register. 407 * @{ 408 */ 409 #define MXC_F_TPU_REVA_DATA_IN_DATA_POS 0 /**< DATA_IN_DATA Position */ 410 #define MXC_F_TPU_REVA_DATA_IN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_REVA_DATA_IN_DATA_POS)) /**< DATA_IN_DATA Mask */ 411 412 /**@} end of group TPU_REVA_DATA_IN_Register */ 413 414 /** 415 * @ingroup tpu_reva_registers 416 * @defgroup TPU_REVA_DATA_OUT TPU_REVA_DATA_OUT 417 * @brief Crypto Data Output. Resulting data from cipher calculation. Data is placed in 418 * the lower words of these four registers depending on the algorithm. For block 419 * cipher modes, this register holds the result of most recent encryption or 420 * decryption operation. These registers are affected by the endian swap bits. 421 * @{ 422 */ 423 #define MXC_F_TPU_REVA_DATA_OUT_DATA_POS 0 /**< DATA_OUT_DATA Position */ 424 #define MXC_F_TPU_REVA_DATA_OUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_REVA_DATA_OUT_DATA_POS)) /**< DATA_OUT_DATA Mask */ 425 426 /**@} end of group TPU_REVA_DATA_OUT_Register */ 427 428 /** 429 * @ingroup tpu_reva_registers 430 * @defgroup TPU_REVA_CRC_POLY TPU_REVA_CRC_POLY 431 * @brief CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or 432 * LFSR) should be written to this register. This register is affected by the MSB 433 * control bit. 434 * @{ 435 */ 436 #define MXC_F_TPU_REVA_CRC_POLY_SRC_ADDR_POS 0 /**< CRC_POLY_SRC_ADDR Position */ 437 #define MXC_F_TPU_REVA_CRC_POLY_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_REVA_CRC_POLY_SRC_ADDR_POS)) /**< CRC_POLY_SRC_ADDR Mask */ 438 439 /**@} end of group TPU_REVA_CRC_POLY_Register */ 440 441 /** 442 * @ingroup tpu_reva_registers 443 * @defgroup TPU_REVA_CRC_VAL TPU_REVA_CRC_VAL 444 * @brief CRC Value. This is the state for the Galois Field. This register holds the 445 * result of a CRC calculation or the current state of the LFSR. This register is 446 * affected by the MSB control bit. 447 * @{ 448 */ 449 #define MXC_F_TPU_REVA_CRC_VAL_VAL_POS 0 /**< CRC_VAL_VAL Position */ 450 #define MXC_F_TPU_REVA_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_REVA_CRC_VAL_VAL_POS)) /**< CRC_VAL_VAL Mask */ 451 452 /**@} end of group TPU_REVA_CRC_VAL_Register */ 453 454 /** 455 * @ingroup tpu_reva_registers 456 * @defgroup TPU_REVA_CRC_PRNG TPU_REVA_CRC_PRNG 457 * @brief Pseudo Random Value. Output of the Galois Field shift register. This holds the 458 * resulting pseudo-random number if entropy is disabled or true random number if 459 * entropy is enabled. 460 * @{ 461 */ 462 #define MXC_F_TPU_REVA_CRC_PRNG_PRNG_POS 0 /**< CRC_PRNG_PRNG Position */ 463 #define MXC_F_TPU_REVA_CRC_PRNG_PRNG ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_REVA_CRC_PRNG_PRNG_POS)) /**< CRC_PRNG_PRNG Mask */ 464 465 /**@} end of group TPU_REVA_CRC_PRNG_Register */ 466 467 /** 468 * @ingroup tpu_reva_registers 469 * @defgroup TPU_REVA_HAM_ECC TPU_REVA_HAM_ECC 470 * @brief Hamming ECC Register. 471 * @{ 472 */ 473 #define MXC_F_TPU_REVA_HAM_ECC_ECC_POS 0 /**< HAM_ECC_ECC Position */ 474 #define MXC_F_TPU_REVA_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_TPU_REVA_HAM_ECC_ECC_POS)) /**< HAM_ECC_ECC Mask */ 475 476 #define MXC_F_TPU_REVA_HAM_ECC_PAR_POS 16 /**< HAM_ECC_PAR Position */ 477 #define MXC_F_TPU_REVA_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_TPU_REVA_HAM_ECC_PAR_POS)) /**< HAM_ECC_PAR Mask */ 478 479 /**@} end of group TPU_REVA_HAM_ECC_Register */ 480 481 /** 482 * @ingroup tpu_reva_registers 483 * @defgroup TPU_REVA_CIPHER_INIT TPU_REVA_CIPHER_INIT 484 * @brief Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR 485 * modes, this register holds the initial value. This register is updated with each 486 * encryption or decryption operation. This register is affected by the endian swap 487 * bits. 488 * @{ 489 */ 490 #define MXC_F_TPU_REVA_CIPHER_INIT_IVEC_POS 0 /**< CIPHER_INIT_IVEC Position */ 491 #define MXC_F_TPU_REVA_CIPHER_INIT_IVEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_REVA_CIPHER_INIT_IVEC_POS)) /**< CIPHER_INIT_IVEC Mask */ 492 493 /**@} end of group TPU_REVA_CIPHER_INIT_Register */ 494 495 /** 496 * @ingroup tpu_reva_registers 497 * @defgroup TPU_REVA_CIPHER_KEY TPU_REVA_CIPHER_KEY 498 * @brief Cipher Key. This register holds the key used for block cipher operations. The 499 * lower words are used for block ciphers that use shorter key lengths. This 500 * register is affected by the endian swap input control bits. 501 * @{ 502 */ 503 #define MXC_F_TPU_REVA_CIPHER_KEY_KEY_POS 0 /**< CIPHER_KEY_KEY Position */ 504 #define MXC_F_TPU_REVA_CIPHER_KEY_KEY ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_REVA_CIPHER_KEY_KEY_POS)) /**< CIPHER_KEY_KEY Mask */ 505 506 /**@} end of group TPU_REVA_CIPHER_KEY_Register */ 507 508 /** 509 * @ingroup tpu_reva_registers 510 * @defgroup TPU_REVA_HASH_DIGEST TPU_REVA_HASH_DIGEST 511 * @brief This register holds the calculated hash value. This register is affected by the 512 * endian swap bits. 513 * @{ 514 */ 515 #define MXC_F_TPU_REVA_HASH_DIGEST_HASH_POS 0 /**< HASH_DIGEST_HASH Position */ 516 #define MXC_F_TPU_REVA_HASH_DIGEST_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_REVA_HASH_DIGEST_HASH_POS)) /**< HASH_DIGEST_HASH Mask */ 517 518 /**@} end of group TPU_REVA_HASH_DIGEST_Register */ 519 520 /** 521 * @ingroup tpu_reva_registers 522 * @defgroup TPU_REVA_HASH_MSG_SZ TPU_REVA_HASH_MSG_SZ 523 * @brief Message Size. This register holds the lowest 32-bit of message size in bytes. 524 * @{ 525 */ 526 #define MXC_F_TPU_REVA_HASH_MSG_SZ_MSGSZ_POS 0 /**< HASH_MSG_SZ_MSGSZ Position */ 527 #define MXC_F_TPU_REVA_HASH_MSG_SZ_MSGSZ ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_REVA_HASH_MSG_SZ_MSGSZ_POS)) /**< HASH_MSG_SZ_MSGSZ Mask */ 528 529 /**@} end of group TPU_REVA_HASH_MSG_SZ_Register */ 530 531 /** 532 * @ingroup tpu_reva_registers 533 * @defgroup TPU_REVA_MAA_MAWS TPU_REVA_MAA_MAWS 534 * @brief MAA Word Size. This register defines the number of bits for a modular operation. 535 * This register must be set to a valid value prior to the MAA operation start. 536 * Valid values are from 1 to 2048. Invalid values are ignored and will not 537 * initiate a MAA operation. 538 * @{ 539 */ 540 #define MXC_F_TPU_REVA_MAA_MAWS_MSGSZ_POS 0 /**< MAA_MAWS_MSGSZ Position */ 541 #define MXC_F_TPU_REVA_MAA_MAWS_MSGSZ ((uint32_t)(0xFFFUL << MXC_F_TPU_REVA_MAA_MAWS_MSGSZ_POS)) /**< MAA_MAWS_MSGSZ Mask */ 542 543 /**@} end of group TPU_REVA_MAA_MAWS_Register */ 544 545 #ifdef __cplusplus 546 } 547 #endif 548 549 #endif /* _TPU_REVA_REGS_H_ */ 550
