1 /** 2 * @file tmr_revb_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the TMR_REVB Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _TMR_REVB_REGS_H_ 27 #define _TMR_REVB_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup tmr_revb 65 * @defgroup tmr_revb_registers TMR_REVB_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the TMR_REVB Peripheral Module. 67 * @details Low-Power Configurable Timer 68 */ 69 70 /** 71 * @ingroup tmr_revb_registers 72 * Structure type to access the TMR_REVB Registers. 73 */ 74 typedef struct { 75 __IO uint32_t cnt; /**< <tt>\b 0x00:</tt> TMR_REVB CNT Register */ 76 __IO uint32_t cmp; /**< <tt>\b 0x04:</tt> TMR_REVB CMP Register */ 77 __IO uint32_t pwm; /**< <tt>\b 0x08:</tt> TMR_REVB PWM Register */ 78 __IO uint32_t intfl; /**< <tt>\b 0x0C:</tt> TMR_REVB INTFL Register */ 79 __IO uint32_t ctrl0; /**< <tt>\b 0x10:</tt> TMR_REVB CTRL0 Register */ 80 __IO uint32_t nolcmp; /**< <tt>\b 0x14:</tt> TMR_REVB NOLCMP Register */ 81 __IO uint32_t ctrl1; /**< <tt>\b 0x18:</tt> TMR_REVB CTRL1 Register */ 82 __IO uint32_t wkfl; /**< <tt>\b 0x1C:</tt> TMR_REVB WKFL Register */ 83 } mxc_tmr_revb_regs_t; 84 85 /* Register offsets for module TMR_REVB */ 86 /** 87 * @ingroup tmr_revb_registers 88 * @defgroup TMR_REVB_Register_Offsets Register Offsets 89 * @brief TMR_REVB Peripheral Register Offsets from the TMR_REVB Base Peripheral Address. 90 * @{ 91 */ 92 #define MXC_R_TMR_REVB_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR_REVB Base Address: <tt> 0x0000</tt> */ 93 #define MXC_R_TMR_REVB_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR_REVB Base Address: <tt> 0x0004</tt> */ 94 #define MXC_R_TMR_REVB_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR_REVB Base Address: <tt> 0x0008</tt> */ 95 #define MXC_R_TMR_REVB_INTFL ((uint32_t)0x0000000CUL) /**< Offset from TMR_REVB Base Address: <tt> 0x000C</tt> */ 96 #define MXC_R_TMR_REVB_CTRL0 ((uint32_t)0x00000010UL) /**< Offset from TMR_REVB Base Address: <tt> 0x0010</tt> */ 97 #define MXC_R_TMR_REVB_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR_REVB Base Address: <tt> 0x0014</tt> */ 98 #define MXC_R_TMR_REVB_CTRL1 ((uint32_t)0x00000018UL) /**< Offset from TMR_REVB Base Address: <tt> 0x0018</tt> */ 99 #define MXC_R_TMR_REVB_WKFL ((uint32_t)0x0000001CUL) /**< Offset from TMR_REVB Base Address: <tt> 0x001C</tt> */ 100 /**@} end of group tmr_revb_registers */ 101 102 /** 103 * @ingroup tmr_revb_registers 104 * @defgroup TMR_REVB_CNT TMR_REVB_CNT 105 * @brief Timer Counter Register. 106 * @{ 107 */ 108 #define MXC_F_TMR_REVB_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ 109 #define MXC_F_TMR_REVB_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ 110 111 /**@} end of group TMR_REVB_CNT_Register */ 112 113 /** 114 * @ingroup tmr_revb_registers 115 * @defgroup TMR_REVB_CMP TMR_REVB_CMP 116 * @brief Timer Compare Register. 117 * @{ 118 */ 119 #define MXC_F_TMR_REVB_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ 120 #define MXC_F_TMR_REVB_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ 121 122 /**@} end of group TMR_REVB_CMP_Register */ 123 124 /** 125 * @ingroup tmr_revb_registers 126 * @defgroup TMR_REVB_PWM TMR_REVB_PWM 127 * @brief Timer PWM Register. 128 * @{ 129 */ 130 #define MXC_F_TMR_REVB_PWM_PWM_POS 0 /**< PWM_PWM Position */ 131 #define MXC_F_TMR_REVB_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_PWM_PWM_POS)) /**< PWM_PWM Mask */ 132 133 /**@} end of group TMR_REVB_PWM_Register */ 134 135 /** 136 * @ingroup tmr_revb_registers 137 * @defgroup TMR_REVB_INTFL TMR_REVB_INTFL 138 * @brief Timer Interrupt Status Register. 139 * @{ 140 */ 141 #define MXC_F_TMR_REVB_INTFL_IRQ_A_POS 0 /**< INTFL_IRQ_A Position */ 142 #define MXC_F_TMR_REVB_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */ 143 144 #define MXC_F_TMR_REVB_INTFL_WRDONE_A_POS 8 /**< INTFL_WRDONE_A Position */ 145 #define MXC_F_TMR_REVB_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */ 146 147 #define MXC_F_TMR_REVB_INTFL_WR_DIS_A_POS 9 /**< INTFL_WR_DIS_A Position */ 148 #define MXC_F_TMR_REVB_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */ 149 150 #define MXC_F_TMR_REVB_INTFL_IRQ_B_POS 16 /**< INTFL_IRQ_B Position */ 151 #define MXC_F_TMR_REVB_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */ 152 153 #define MXC_F_TMR_REVB_INTFL_WRDONE_B_POS 24 /**< INTFL_WRDONE_B Position */ 154 #define MXC_F_TMR_REVB_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */ 155 156 #define MXC_F_TMR_REVB_INTFL_WR_DIS_B_POS 25 /**< INTFL_WR_DIS_B Position */ 157 #define MXC_F_TMR_REVB_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */ 158 159 /**@} end of group TMR_REVB_INTFL_Register */ 160 161 /** 162 * @ingroup tmr_revb_registers 163 * @defgroup TMR_REVB_CTRL0 TMR_REVB_CTRL0 164 * @brief Timer Control Register. 165 * @{ 166 */ 167 #define MXC_F_TMR_REVB_CTRL0_MODE_A_POS 0 /**< CTRL0_MODE_A Position */ 168 #define MXC_F_TMR_REVB_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */ 169 #define MXC_V_TMR_REVB_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */ 170 #define MXC_S_TMR_REVB_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_REVB_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */ 171 #define MXC_V_TMR_REVB_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */ 172 #define MXC_S_TMR_REVB_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_REVB_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */ 173 #define MXC_V_TMR_REVB_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */ 174 #define MXC_S_TMR_REVB_CTRL0_MODE_A_COUNTER (MXC_V_TMR_REVB_CTRL0_MODE_A_COUNTER << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */ 175 #define MXC_V_TMR_REVB_CTRL0_MODE_A_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */ 176 #define MXC_S_TMR_REVB_CTRL0_MODE_A_PWM (MXC_V_TMR_REVB_CTRL0_MODE_A_PWM << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */ 177 #define MXC_V_TMR_REVB_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */ 178 #define MXC_S_TMR_REVB_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_REVB_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */ 179 #define MXC_V_TMR_REVB_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */ 180 #define MXC_S_TMR_REVB_CTRL0_MODE_A_COMPARE (MXC_V_TMR_REVB_CTRL0_MODE_A_COMPARE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */ 181 #define MXC_V_TMR_REVB_CTRL0_MODE_A_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */ 182 #define MXC_S_TMR_REVB_CTRL0_MODE_A_GATED (MXC_V_TMR_REVB_CTRL0_MODE_A_GATED << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */ 183 #define MXC_V_TMR_REVB_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */ 184 #define MXC_S_TMR_REVB_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_REVB_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */ 185 #define MXC_V_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */ 186 #define MXC_S_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */ 187 #define MXC_V_TMR_REVB_CTRL0_MODE_A_IGATED ((uint32_t)0xCUL) /**< CTRL0_MODE_A_IGATED Value */ 188 #define MXC_S_TMR_REVB_CTRL0_MODE_A_IGATED (MXC_V_TMR_REVB_CTRL0_MODE_A_IGATED << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */ 189 190 #define MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS 4 /**< CTRL0_CLKDIV_A Position */ 191 #define MXC_F_TMR_REVB_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */ 192 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */ 193 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */ 194 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */ 195 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */ 196 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */ 197 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */ 198 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */ 199 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */ 200 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */ 201 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */ 202 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */ 203 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */ 204 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */ 205 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */ 206 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */ 207 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */ 208 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */ 209 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */ 210 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */ 211 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */ 212 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */ 213 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */ 214 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */ 215 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */ 216 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */ 217 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */ 218 219 #define MXC_F_TMR_REVB_CTRL0_POL_A_POS 8 /**< CTRL0_POL_A Position */ 220 #define MXC_F_TMR_REVB_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */ 221 222 #define MXC_F_TMR_REVB_CTRL0_PWMSYNC_A_POS 9 /**< CTRL0_PWMSYNC_A Position */ 223 #define MXC_F_TMR_REVB_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */ 224 225 #define MXC_F_TMR_REVB_CTRL0_NOLHPOL_A_POS 10 /**< CTRL0_NOLHPOL_A Position */ 226 #define MXC_F_TMR_REVB_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */ 227 228 #define MXC_F_TMR_REVB_CTRL0_NOLLPOL_A_POS 11 /**< CTRL0_NOLLPOL_A Position */ 229 #define MXC_F_TMR_REVB_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */ 230 231 #define MXC_F_TMR_REVB_CTRL0_PWMCKBD_A_POS 12 /**< CTRL0_PWMCKBD_A Position */ 232 #define MXC_F_TMR_REVB_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */ 233 234 #define MXC_F_TMR_REVB_CTRL0_RST_A_POS 13 /**< CTRL0_RST_A Position */ 235 #define MXC_F_TMR_REVB_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */ 236 237 #define MXC_F_TMR_REVB_CTRL0_CLKEN_A_POS 14 /**< CTRL0_CLKEN_A Position */ 238 #define MXC_F_TMR_REVB_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */ 239 240 #define MXC_F_TMR_REVB_CTRL0_EN_A_POS 15 /**< CTRL0_EN_A Position */ 241 #define MXC_F_TMR_REVB_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */ 242 243 #define MXC_F_TMR_REVB_CTRL0_MODE_B_POS 16 /**< CTRL0_MODE_B Position */ 244 #define MXC_F_TMR_REVB_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */ 245 #define MXC_V_TMR_REVB_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */ 246 #define MXC_S_TMR_REVB_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_REVB_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */ 247 #define MXC_V_TMR_REVB_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */ 248 #define MXC_S_TMR_REVB_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_REVB_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */ 249 #define MXC_V_TMR_REVB_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */ 250 #define MXC_S_TMR_REVB_CTRL0_MODE_B_COUNTER (MXC_V_TMR_REVB_CTRL0_MODE_B_COUNTER << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */ 251 #define MXC_V_TMR_REVB_CTRL0_MODE_B_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */ 252 #define MXC_S_TMR_REVB_CTRL0_MODE_B_PWM (MXC_V_TMR_REVB_CTRL0_MODE_B_PWM << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */ 253 #define MXC_V_TMR_REVB_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */ 254 #define MXC_S_TMR_REVB_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_REVB_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */ 255 #define MXC_V_TMR_REVB_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */ 256 #define MXC_S_TMR_REVB_CTRL0_MODE_B_COMPARE (MXC_V_TMR_REVB_CTRL0_MODE_B_COMPARE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */ 257 #define MXC_V_TMR_REVB_CTRL0_MODE_B_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */ 258 #define MXC_S_TMR_REVB_CTRL0_MODE_B_GATED (MXC_V_TMR_REVB_CTRL0_MODE_B_GATED << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */ 259 #define MXC_V_TMR_REVB_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */ 260 #define MXC_S_TMR_REVB_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_REVB_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */ 261 #define MXC_V_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */ 262 #define MXC_S_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */ 263 #define MXC_V_TMR_REVB_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */ 264 #define MXC_S_TMR_REVB_CTRL0_MODE_B_IGATED (MXC_V_TMR_REVB_CTRL0_MODE_B_IGATED << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */ 265 266 #define MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS 20 /**< CTRL0_CLKDIV_B Position */ 267 #define MXC_F_TMR_REVB_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */ 268 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */ 269 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */ 270 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */ 271 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */ 272 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */ 273 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */ 274 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */ 275 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */ 276 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */ 277 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */ 278 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */ 279 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */ 280 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */ 281 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */ 282 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */ 283 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */ 284 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */ 285 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */ 286 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */ 287 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */ 288 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */ 289 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */ 290 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */ 291 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */ 292 #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */ 293 #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */ 294 295 #define MXC_F_TMR_REVB_CTRL0_POL_B_POS 24 /**< CTRL0_POL_B Position */ 296 #define MXC_F_TMR_REVB_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */ 297 298 #define MXC_F_TMR_REVB_CTRL0_PWMSYNC_B_POS 25 /**< CTRL0_PWMSYNC_B Position */ 299 #define MXC_F_TMR_REVB_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */ 300 301 #define MXC_F_TMR_REVB_CTRL0_NOLHPOL_B_POS 26 /**< CTRL0_NOLHPOL_B Position */ 302 #define MXC_F_TMR_REVB_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */ 303 304 #define MXC_F_TMR_REVB_CTRL0_NOLLPOL_B_POS 27 /**< CTRL0_NOLLPOL_B Position */ 305 #define MXC_F_TMR_REVB_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */ 306 307 #define MXC_F_TMR_REVB_CTRL0_PWMCKBD_B_POS 28 /**< CTRL0_PWMCKBD_B Position */ 308 #define MXC_F_TMR_REVB_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */ 309 310 #define MXC_F_TMR_REVB_CTRL0_RST_B_POS 29 /**< CTRL0_RST_B Position */ 311 #define MXC_F_TMR_REVB_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */ 312 313 #define MXC_F_TMR_REVB_CTRL0_CLKEN_B_POS 30 /**< CTRL0_CLKEN_B Position */ 314 #define MXC_F_TMR_REVB_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */ 315 316 #define MXC_F_TMR_REVB_CTRL0_EN_B_POS 31 /**< CTRL0_EN_B Position */ 317 #define MXC_F_TMR_REVB_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */ 318 319 /**@} end of group TMR_REVB_CTRL0_Register */ 320 321 /** 322 * @ingroup tmr_revb_registers 323 * @defgroup TMR_REVB_NOLCMP TMR_REVB_NOLCMP 324 * @brief Timer Non-Overlapping Compare Register. 325 * @{ 326 */ 327 #define MXC_F_TMR_REVB_NOLCMP_LO_A_POS 0 /**< NOLCMP_LO_A Position */ 328 #define MXC_F_TMR_REVB_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */ 329 330 #define MXC_F_TMR_REVB_NOLCMP_HI_A_POS 8 /**< NOLCMP_HI_A Position */ 331 #define MXC_F_TMR_REVB_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */ 332 333 #define MXC_F_TMR_REVB_NOLCMP_LO_B_POS 16 /**< NOLCMP_LO_B Position */ 334 #define MXC_F_TMR_REVB_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */ 335 336 #define MXC_F_TMR_REVB_NOLCMP_HI_B_POS 24 /**< NOLCMP_HI_B Position */ 337 #define MXC_F_TMR_REVB_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */ 338 339 /**@} end of group TMR_REVB_NOLCMP_Register */ 340 341 /** 342 * @ingroup tmr_revb_registers 343 * @defgroup TMR_REVB_CTRL1 TMR_REVB_CTRL1 344 * @brief Timer Configuration Register. 345 * @{ 346 */ 347 #define MXC_F_TMR_REVB_CTRL1_CLKSEL_A_POS 0 /**< CTRL1_CLKSEL_A Position */ 348 #define MXC_F_TMR_REVB_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */ 349 350 #define MXC_F_TMR_REVB_CTRL1_CLKEN_A_POS 2 /**< CTRL1_CLKEN_A Position */ 351 #define MXC_F_TMR_REVB_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */ 352 353 #define MXC_F_TMR_REVB_CTRL1_CLKRDY_A_POS 3 /**< CTRL1_CLKRDY_A Position */ 354 #define MXC_F_TMR_REVB_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */ 355 356 #define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A_POS 4 /**< CTRL1_EVENT_SEL_A Position */ 357 #define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */ 358 359 #define MXC_F_TMR_REVB_CTRL1_NEGTRIG_A_POS 7 /**< CTRL1_NEGTRIG_A Position */ 360 #define MXC_F_TMR_REVB_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */ 361 362 #define MXC_F_TMR_REVB_CTRL1_IE_A_POS 8 /**< CTRL1_IE_A Position */ 363 #define MXC_F_TMR_REVB_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */ 364 365 #define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A_POS 9 /**< CTRL1_CAPEVENT_SEL_A Position */ 366 #define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */ 367 368 #define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A_POS 11 /**< CTRL1_SW_CAPEVENT_A Position */ 369 #define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */ 370 371 #define MXC_F_TMR_REVB_CTRL1_WE_A_POS 12 /**< CTRL1_WE_A Position */ 372 #define MXC_F_TMR_REVB_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */ 373 374 #define MXC_F_TMR_REVB_CTRL1_OUTEN_A_POS 13 /**< CTRL1_OUTEN_A Position */ 375 #define MXC_F_TMR_REVB_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */ 376 377 #define MXC_F_TMR_REVB_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ 378 #define MXC_F_TMR_REVB_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ 379 380 #define MXC_F_TMR_REVB_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ 381 #define MXC_F_TMR_REVB_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ 382 383 #define MXC_F_TMR_REVB_CTRL1_CLKEN_B_POS 18 /**< CTRL1_CLKEN_B Position */ 384 #define MXC_F_TMR_REVB_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */ 385 386 #define MXC_F_TMR_REVB_CTRL1_CLKRDY_B_POS 19 /**< CTRL1_CLKRDY_B Position */ 387 #define MXC_F_TMR_REVB_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */ 388 389 #define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B_POS 20 /**< CTRL1_EVENT_SEL_B Position */ 390 #define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */ 391 392 #define MXC_F_TMR_REVB_CTRL1_NEGTRIG_B_POS 23 /**< CTRL1_NEGTRIG_B Position */ 393 #define MXC_F_TMR_REVB_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */ 394 395 #define MXC_F_TMR_REVB_CTRL1_IE_B_POS 24 /**< CTRL1_IE_B Position */ 396 #define MXC_F_TMR_REVB_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */ 397 398 #define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B_POS 25 /**< CTRL1_CAPEVENT_SEL_B Position */ 399 #define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */ 400 401 #define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B_POS 27 /**< CTRL1_SW_CAPEVENT_B Position */ 402 #define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */ 403 404 #define MXC_F_TMR_REVB_CTRL1_WE_B_POS 28 /**< CTRL1_WE_B Position */ 405 #define MXC_F_TMR_REVB_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */ 406 407 #define MXC_F_TMR_REVB_CTRL1_CASCADE_POS 31 /**< CTRL1_CASCADE Position */ 408 #define MXC_F_TMR_REVB_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */ 409 410 /**@} end of group TMR_REVB_CTRL1_Register */ 411 412 /** 413 * @ingroup tmr_revb_registers 414 * @defgroup TMR_REVB_WKFL TMR_REVB_WKFL 415 * @brief Timer Wakeup Status Register. 416 * @{ 417 */ 418 #define MXC_F_TMR_REVB_WKFL_A_POS 0 /**< WKFL_A Position */ 419 #define MXC_F_TMR_REVB_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_WKFL_A_POS)) /**< WKFL_A Mask */ 420 421 #define MXC_F_TMR_REVB_WKFL_B_POS 16 /**< WKFL_B Position */ 422 #define MXC_F_TMR_REVB_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_WKFL_B_POS)) /**< WKFL_B Mask */ 423 424 /**@} end of group TMR_REVB_WKFL_Register */ 425 426 #ifdef __cplusplus 427 } 428 #endif 429 430 #endif /* _TMR_REVB_REGS_H_ */ 431
