1 /** 2 * @file spi_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SPI_REVA_REGS_H_ 27 #define _SPI_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup spi 65 * @defgroup spi_registers SPI_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. 67 * @details SPI peripheral. 68 */ 69 70 /** 71 * @ingroup spi_registers 72 * Structure type to access the SPI Registers. 73 */ 74 typedef struct { 75 union{ 76 __IO uint32_t fifo32; /**< <tt>\b 0x00:</tt> SPI FIFO32 Register */ 77 __IO uint16_t fifo16[2]; /**< <tt>\b 0x00:</tt> SPI FIFO16 Register */ 78 __IO uint8_t fifo8[4]; /**< <tt>\b 0x00:</tt> SPI FIFO8 Register */ 79 }; 80 __IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPI CTRL0 Register */ 81 __IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPI CTRL1 Register */ 82 __IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */ 83 __IO uint32_t sstime; /**< <tt>\b 0x10:</tt> SPI SSTIME Register */ 84 __IO uint32_t clkctrl; /**< <tt>\b 0x14:</tt> SPI CLKCTRL Register */ 85 __R uint32_t rsv_0x18; 86 __IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI DMA Register */ 87 __IO uint32_t intfl; /**< <tt>\b 0x20:</tt> SPI INTFL Register */ 88 __IO uint32_t inten; /**< <tt>\b 0x24:</tt> SPI INTEN Register */ 89 __IO uint32_t wkfl; /**< <tt>\b 0x28:</tt> SPI WKFL Register */ 90 __IO uint32_t wken; /**< <tt>\b 0x2C:</tt> SPI WKEN Register */ 91 __I uint32_t stat; /**< <tt>\b 0x30:</tt> SPI STAT Register */ 92 } mxc_spi_reva_regs_t; 93 94 /* Register offsets for module SPI */ 95 /** 96 * @ingroup spi_registers 97 * @defgroup SPI_Register_Offsets Register Offsets 98 * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. 99 * @{ 100 */ 101 #define MXC_R_SPI_REVA_FIFO32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 102 #define MXC_R_SPI_REVA_FIFO16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 103 #define MXC_R_SPI_REVA_FIFO8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_SPI_REVA_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: <tt> 0x0004</tt> */ 105 #define MXC_R_SPI_REVA_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: <tt> 0x0008</tt> */ 106 #define MXC_R_SPI_REVA_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: <tt> 0x000C</tt> */ 107 #define MXC_R_SPI_REVA_SSTIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: <tt> 0x0010</tt> */ 108 #define MXC_R_SPI_REVA_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: <tt> 0x0014</tt> */ 109 #define MXC_R_SPI_REVA_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: <tt> 0x001C</tt> */ 110 #define MXC_R_SPI_REVA_INTFL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: <tt> 0x0020</tt> */ 111 #define MXC_R_SPI_REVA_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: <tt> 0x0024</tt> */ 112 #define MXC_R_SPI_REVA_WKFL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: <tt> 0x0028</tt> */ 113 #define MXC_R_SPI_REVA_WKEN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: <tt> 0x002C</tt> */ 114 #define MXC_R_SPI_REVA_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: <tt> 0x0030</tt> */ 115 /**@} end of group spi_registers */ 116 117 /** 118 * @ingroup spi_registers 119 * @defgroup SPI_FIFO32 SPI_FIFO32 120 * @brief Register for reading and writing the FIFO. 121 * @{ 122 */ 123 #define MXC_F_SPI_REVA_FIFO32_DATA_POS 0 /**< FIFO32_DATA Position */ 124 #define MXC_F_SPI_REVA_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_REVA_FIFO32_DATA_POS)) /**< FIFO32_DATA Mask */ 125 126 /**@} end of group SPI_FIFO32_Register */ 127 128 /** 129 * @ingroup spi_registers 130 * @defgroup SPI_FIFO16 SPI_FIFO16 131 * @brief Register for reading and writing the FIFO. 132 * @{ 133 */ 134 #define MXC_F_SPI_REVA_FIFO16_DATA_POS 0 /**< FIFO16_DATA Position */ 135 #define MXC_F_SPI_REVA_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_REVA_FIFO16_DATA_POS)) /**< FIFO16_DATA Mask */ 136 137 /**@} end of group SPI_FIFO16_Register */ 138 139 /** 140 * @ingroup spi_registers 141 * @defgroup SPI_FIFO8 SPI_FIFO8 142 * @brief Register for reading and writing the FIFO. 143 * @{ 144 */ 145 #define MXC_F_SPI_REVA_FIFO8_DATA_POS 0 /**< FIFO8_DATA Position */ 146 #define MXC_F_SPI_REVA_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_REVA_FIFO8_DATA_POS)) /**< FIFO8_DATA Mask */ 147 148 /**@} end of group SPI_FIFO8_Register */ 149 150 /** 151 * @ingroup spi_registers 152 * @defgroup SPI_CTRL0 SPI_CTRL0 153 * @brief Register for controlling SPI peripheral. 154 * @{ 155 */ 156 #define MXC_F_SPI_REVA_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ 157 #define MXC_F_SPI_REVA_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ 158 159 #define MXC_F_SPI_REVA_CTRL0_MST_MODE_POS 1 /**< CTRL0_MST_MODE Position */ 160 #define MXC_F_SPI_REVA_CTRL0_MST_MODE ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_MST_MODE_POS)) /**< CTRL0_MST_MODE Mask */ 161 162 #define MXC_F_SPI_REVA_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ 163 #define MXC_F_SPI_REVA_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ 164 165 #define MXC_F_SPI_REVA_CTRL0_START_POS 5 /**< CTRL0_START Position */ 166 #define MXC_F_SPI_REVA_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_START_POS)) /**< CTRL0_START Mask */ 167 168 #define MXC_F_SPI_REVA_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ 169 #define MXC_F_SPI_REVA_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ 170 171 #define MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS 16 /**< CTRL0_SS_ACTIVE Position */ 172 #define MXC_F_SPI_REVA_CTRL0_SS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS)) /**< CTRL0_SS_ACTIVE Mask */ 173 #define MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_ACTIVE_SS0 Value */ 174 #define MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 (MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS0 Setting */ 175 #define MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_ACTIVE_SS1 Value */ 176 #define MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 (MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS1 Setting */ 177 #define MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_ACTIVE_SS2 Value */ 178 #define MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 (MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS2 Setting */ 179 #define MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_ACTIVE_SS3 Value */ 180 #define MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3 (MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS3 Setting */ 181 182 /**@} end of group SPI_CTRL0_Register */ 183 184 /** 185 * @ingroup spi_registers 186 * @defgroup SPI_CTRL1 SPI_CTRL1 187 * @brief Register for controlling SPI peripheral. 188 * @{ 189 */ 190 #define MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ 191 #define MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ 192 193 #define MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ 194 #define MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ 195 196 /**@} end of group SPI_CTRL1_Register */ 197 198 /** 199 * @ingroup spi_registers 200 * @defgroup SPI_CTRL2 SPI_CTRL2 201 * @brief Register for controlling SPI peripheral. 202 * @{ 203 */ 204 #define MXC_F_SPI_REVA_CTRL2_CLKPHA_POS 0 /**< CTRL2_CLKPHA Position */ 205 #define MXC_F_SPI_REVA_CTRL2_CLKPHA ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL2_CLKPHA_POS)) /**< CTRL2_CLKPHA Mask */ 206 207 #define MXC_F_SPI_REVA_CTRL2_CLKPOL_POS 1 /**< CTRL2_CLKPOL Position */ 208 #define MXC_F_SPI_REVA_CTRL2_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL2_CLKPOL_POS)) /**< CTRL2_CLKPOL Mask */ 209 210 #define MXC_F_SPI_REVA_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ 211 #define MXC_F_SPI_REVA_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ 212 #define MXC_V_SPI_REVA_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */ 213 #define MXC_S_SPI_REVA_CTRL2_NUMBITS_0 (MXC_V_SPI_REVA_CTRL2_NUMBITS_0 << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */ 214 215 #define MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ 216 #define MXC_F_SPI_REVA_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ 217 #define MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ 218 #define MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ 219 #define MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ 220 #define MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ 221 #define MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ 222 #define MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ 223 224 #define MXC_F_SPI_REVA_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ 225 #define MXC_F_SPI_REVA_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ 226 227 #define MXC_F_SPI_REVA_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ 228 #define MXC_F_SPI_REVA_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ 229 #define MXC_V_SPI_REVA_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ 230 #define MXC_S_SPI_REVA_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_REVA_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_REVA_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ 231 #define MXC_V_SPI_REVA_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ 232 #define MXC_S_SPI_REVA_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_REVA_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_REVA_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ 233 #define MXC_V_SPI_REVA_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ 234 #define MXC_S_SPI_REVA_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_REVA_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_REVA_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ 235 #define MXC_V_SPI_REVA_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */ 236 #define MXC_S_SPI_REVA_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_REVA_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_REVA_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */ 237 238 /**@} end of group SPI_CTRL2_Register */ 239 240 /** 241 * @ingroup spi_registers 242 * @defgroup SPI_SSTIME SPI_SSTIME 243 * @brief Register for controlling SPI peripheral/Slave Select Timing. 244 * @{ 245 */ 246 #define MXC_F_SPI_REVA_SSTIME_PRE_POS 0 /**< SSTIME_PRE Position */ 247 #define MXC_F_SPI_REVA_SSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_SSTIME_PRE_POS)) /**< SSTIME_PRE Mask */ 248 #define MXC_V_SPI_REVA_SSTIME_PRE_256 ((uint32_t)0x0UL) /**< SSTIME_PRE_256 Value */ 249 #define MXC_S_SPI_REVA_SSTIME_PRE_256 (MXC_V_SPI_REVA_SSTIME_PRE_256 << MXC_F_SPI_REVA_SSTIME_PRE_POS) /**< SSTIME_PRE_256 Setting */ 250 251 #define MXC_F_SPI_REVA_SSTIME_POST_POS 8 /**< SSTIME_POST Position */ 252 #define MXC_F_SPI_REVA_SSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_SSTIME_POST_POS)) /**< SSTIME_POST Mask */ 253 #define MXC_V_SPI_REVA_SSTIME_POST_256 ((uint32_t)0x0UL) /**< SSTIME_POST_256 Value */ 254 #define MXC_S_SPI_REVA_SSTIME_POST_256 (MXC_V_SPI_REVA_SSTIME_POST_256 << MXC_F_SPI_REVA_SSTIME_POST_POS) /**< SSTIME_POST_256 Setting */ 255 256 #define MXC_F_SPI_REVA_SSTIME_INACT_POS 16 /**< SSTIME_INACT Position */ 257 #define MXC_F_SPI_REVA_SSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_SSTIME_INACT_POS)) /**< SSTIME_INACT Mask */ 258 #define MXC_V_SPI_REVA_SSTIME_INACT_256 ((uint32_t)0x0UL) /**< SSTIME_INACT_256 Value */ 259 #define MXC_S_SPI_REVA_SSTIME_INACT_256 (MXC_V_SPI_REVA_SSTIME_INACT_256 << MXC_F_SPI_REVA_SSTIME_INACT_POS) /**< SSTIME_INACT_256 Setting */ 260 261 /**@} end of group SPI_SSTIME_Register */ 262 263 /** 264 * @ingroup spi_registers 265 * @defgroup SPI_CLKCTRL SPI_CLKCTRL 266 * @brief Register for controlling SPI clock rate. 267 * @{ 268 */ 269 #define MXC_F_SPI_REVA_CLKCTRL_LO_POS 0 /**< CLKCTRL_LO Position */ 270 #define MXC_F_SPI_REVA_CLKCTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_CLKCTRL_LO_POS)) /**< CLKCTRL_LO Mask */ 271 #define MXC_V_SPI_REVA_CLKCTRL_LO_DIS ((uint32_t)0x0UL) /**< CLKCTRL_LO_DIS Value */ 272 #define MXC_S_SPI_REVA_CLKCTRL_LO_DIS (MXC_V_SPI_REVA_CLKCTRL_LO_DIS << MXC_F_SPI_REVA_CLKCTRL_LO_POS) /**< CLKCTRL_LO_DIS Setting */ 273 274 #define MXC_F_SPI_REVA_CLKCTRL_HI_POS 8 /**< CLKCTRL_HI Position */ 275 #define MXC_F_SPI_REVA_CLKCTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_CLKCTRL_HI_POS)) /**< CLKCTRL_HI Mask */ 276 #define MXC_V_SPI_REVA_CLKCTRL_HI_DIS ((uint32_t)0x0UL) /**< CLKCTRL_HI_DIS Value */ 277 #define MXC_S_SPI_REVA_CLKCTRL_HI_DIS (MXC_V_SPI_REVA_CLKCTRL_HI_DIS << MXC_F_SPI_REVA_CLKCTRL_HI_POS) /**< CLKCTRL_HI_DIS Setting */ 278 279 #define MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS 16 /**< CLKCTRL_CLKDIV Position */ 280 #define MXC_F_SPI_REVA_CLKCTRL_CLKDIV ((uint32_t)(0xFUL << MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */ 281 282 /**@} end of group SPI_CLKCTRL_Register */ 283 284 /** 285 * @ingroup spi_registers 286 * @defgroup SPI_DMA SPI_DMA 287 * @brief Register for controlling DMA. 288 * @{ 289 */ 290 #define MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ 291 #define MXC_F_SPI_REVA_DMA_TX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ 292 293 #define MXC_F_SPI_REVA_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ 294 #define MXC_F_SPI_REVA_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ 295 296 #define MXC_F_SPI_REVA_DMA_TX_FLUSH_POS 7 /**< DMA_TX_FLUSH Position */ 297 #define MXC_F_SPI_REVA_DMA_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_TX_FLUSH_POS)) /**< DMA_TX_FLUSH Mask */ 298 299 #define MXC_F_SPI_REVA_DMA_TX_LVL_POS 8 /**< DMA_TX_LVL Position */ 300 #define MXC_F_SPI_REVA_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_REVA_DMA_TX_LVL_POS)) /**< DMA_TX_LVL Mask */ 301 302 #define MXC_F_SPI_REVA_DMA_DMA_TX_EN_POS 15 /**< DMA_DMA_TX_EN Position */ 303 #define MXC_F_SPI_REVA_DMA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_DMA_TX_EN_POS)) /**< DMA_DMA_TX_EN Mask */ 304 305 #define MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS 16 /**< DMA_RX_THD_VAL Position */ 306 #define MXC_F_SPI_REVA_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ 307 308 #define MXC_F_SPI_REVA_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ 309 #define MXC_F_SPI_REVA_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ 310 311 #define MXC_F_SPI_REVA_DMA_RX_FLUSH_POS 23 /**< DMA_RX_FLUSH Position */ 312 #define MXC_F_SPI_REVA_DMA_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_RX_FLUSH_POS)) /**< DMA_RX_FLUSH Mask */ 313 314 #define MXC_F_SPI_REVA_DMA_RX_LVL_POS 24 /**< DMA_RX_LVL Position */ 315 #define MXC_F_SPI_REVA_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_REVA_DMA_RX_LVL_POS)) /**< DMA_RX_LVL Mask */ 316 317 #define MXC_F_SPI_REVA_DMA_DMA_RX_EN_POS 31 /**< DMA_DMA_RX_EN Position */ 318 #define MXC_F_SPI_REVA_DMA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_DMA_RX_EN_POS)) /**< DMA_DMA_RX_EN Mask */ 319 320 /**@} end of group SPI_DMA_Register */ 321 322 /** 323 * @ingroup spi_registers 324 * @defgroup SPI_INTFL SPI_INTFL 325 * @brief Register for reading and clearing interrupt flags. All bits are write 1 to 326 * clear. 327 * @{ 328 */ 329 #define MXC_F_SPI_REVA_INTFL_TX_THD_POS 0 /**< INTFL_TX_THD Position */ 330 #define MXC_F_SPI_REVA_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */ 331 332 #define MXC_F_SPI_REVA_INTFL_TX_EM_POS 1 /**< INTFL_TX_EM Position */ 333 #define MXC_F_SPI_REVA_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */ 334 335 #define MXC_F_SPI_REVA_INTFL_RX_THD_POS 2 /**< INTFL_RX_THD Position */ 336 #define MXC_F_SPI_REVA_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */ 337 338 #define MXC_F_SPI_REVA_INTFL_RX_FULL_POS 3 /**< INTFL_RX_FULL Position */ 339 #define MXC_F_SPI_REVA_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ 340 341 #define MXC_F_SPI_REVA_INTFL_SSA_POS 4 /**< INTFL_SSA Position */ 342 #define MXC_F_SPI_REVA_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_SSA_POS)) /**< INTFL_SSA Mask */ 343 344 #define MXC_F_SPI_REVA_INTFL_SSD_POS 5 /**< INTFL_SSD Position */ 345 #define MXC_F_SPI_REVA_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_SSD_POS)) /**< INTFL_SSD Mask */ 346 347 #define MXC_F_SPI_REVA_INTFL_FAULT_POS 8 /**< INTFL_FAULT Position */ 348 #define MXC_F_SPI_REVA_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */ 349 350 #define MXC_F_SPI_REVA_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */ 351 #define MXC_F_SPI_REVA_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ 352 353 #define MXC_F_SPI_REVA_INTFL_MST_DONE_POS 11 /**< INTFL_MST_DONE Position */ 354 #define MXC_F_SPI_REVA_INTFL_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_MST_DONE_POS)) /**< INTFL_MST_DONE Mask */ 355 356 #define MXC_F_SPI_REVA_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */ 357 #define MXC_F_SPI_REVA_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */ 358 359 #define MXC_F_SPI_REVA_INTFL_TX_UN_POS 13 /**< INTFL_TX_UN Position */ 360 #define MXC_F_SPI_REVA_INTFL_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_TX_UN_POS)) /**< INTFL_TX_UN Mask */ 361 362 #define MXC_F_SPI_REVA_INTFL_RX_OV_POS 14 /**< INTFL_RX_OV Position */ 363 #define MXC_F_SPI_REVA_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */ 364 365 #define MXC_F_SPI_REVA_INTFL_RX_UN_POS 15 /**< INTFL_RX_UN Position */ 366 #define MXC_F_SPI_REVA_INTFL_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_RX_UN_POS)) /**< INTFL_RX_UN Mask */ 367 368 /**@} end of group SPI_INTFL_Register */ 369 370 /** 371 * @ingroup spi_registers 372 * @defgroup SPI_INTEN SPI_INTEN 373 * @brief Register for enabling interrupts. 374 * @{ 375 */ 376 #define MXC_F_SPI_REVA_INTEN_TX_THD_POS 0 /**< INTEN_TX_THD Position */ 377 #define MXC_F_SPI_REVA_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */ 378 379 #define MXC_F_SPI_REVA_INTEN_TX_EM_POS 1 /**< INTEN_TX_EM Position */ 380 #define MXC_F_SPI_REVA_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */ 381 382 #define MXC_F_SPI_REVA_INTEN_RX_THD_POS 2 /**< INTEN_RX_THD Position */ 383 #define MXC_F_SPI_REVA_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */ 384 385 #define MXC_F_SPI_REVA_INTEN_RX_FULL_POS 3 /**< INTEN_RX_FULL Position */ 386 #define MXC_F_SPI_REVA_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ 387 388 #define MXC_F_SPI_REVA_INTEN_SSA_POS 4 /**< INTEN_SSA Position */ 389 #define MXC_F_SPI_REVA_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_SSA_POS)) /**< INTEN_SSA Mask */ 390 391 #define MXC_F_SPI_REVA_INTEN_SSD_POS 5 /**< INTEN_SSD Position */ 392 #define MXC_F_SPI_REVA_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_SSD_POS)) /**< INTEN_SSD Mask */ 393 394 #define MXC_F_SPI_REVA_INTEN_FAULT_POS 8 /**< INTEN_FAULT Position */ 395 #define MXC_F_SPI_REVA_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */ 396 397 #define MXC_F_SPI_REVA_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */ 398 #define MXC_F_SPI_REVA_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ 399 400 #define MXC_F_SPI_REVA_INTEN_MST_DONE_POS 11 /**< INTEN_MST_DONE Position */ 401 #define MXC_F_SPI_REVA_INTEN_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_MST_DONE_POS)) /**< INTEN_MST_DONE Mask */ 402 403 #define MXC_F_SPI_REVA_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */ 404 #define MXC_F_SPI_REVA_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */ 405 406 #define MXC_F_SPI_REVA_INTEN_TX_UN_POS 13 /**< INTEN_TX_UN Position */ 407 #define MXC_F_SPI_REVA_INTEN_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_TX_UN_POS)) /**< INTEN_TX_UN Mask */ 408 409 #define MXC_F_SPI_REVA_INTEN_RX_OV_POS 14 /**< INTEN_RX_OV Position */ 410 #define MXC_F_SPI_REVA_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */ 411 412 #define MXC_F_SPI_REVA_INTEN_RX_UN_POS 15 /**< INTEN_RX_UN Position */ 413 #define MXC_F_SPI_REVA_INTEN_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_RX_UN_POS)) /**< INTEN_RX_UN Mask */ 414 415 /**@} end of group SPI_INTEN_Register */ 416 417 /** 418 * @ingroup spi_registers 419 * @defgroup SPI_WKFL SPI_WKFL 420 * @brief Register for wake up flags. All bits in this register are write 1 to clear. 421 * @{ 422 */ 423 #define MXC_F_SPI_REVA_WKFL_TX_THD_POS 0 /**< WKFL_TX_THD Position */ 424 #define MXC_F_SPI_REVA_WKFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKFL_TX_THD_POS)) /**< WKFL_TX_THD Mask */ 425 426 #define MXC_F_SPI_REVA_WKFL_TX_EM_POS 1 /**< WKFL_TX_EM Position */ 427 #define MXC_F_SPI_REVA_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKFL_TX_EM_POS)) /**< WKFL_TX_EM Mask */ 428 429 #define MXC_F_SPI_REVA_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ 430 #define MXC_F_SPI_REVA_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ 431 432 #define MXC_F_SPI_REVA_WKFL_RX_FULL_POS 3 /**< WKFL_RX_FULL Position */ 433 #define MXC_F_SPI_REVA_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ 434 435 /**@} end of group SPI_WKFL_Register */ 436 437 /** 438 * @ingroup spi_registers 439 * @defgroup SPI_WKEN SPI_WKEN 440 * @brief Register for wake up enable. 441 * @{ 442 */ 443 #define MXC_F_SPI_REVA_WKEN_TX_THD_POS 0 /**< WKEN_TX_THD Position */ 444 #define MXC_F_SPI_REVA_WKEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKEN_TX_THD_POS)) /**< WKEN_TX_THD Mask */ 445 446 #define MXC_F_SPI_REVA_WKEN_TX_EM_POS 1 /**< WKEN_TX_EM Position */ 447 #define MXC_F_SPI_REVA_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKEN_TX_EM_POS)) /**< WKEN_TX_EM Mask */ 448 449 #define MXC_F_SPI_REVA_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ 450 #define MXC_F_SPI_REVA_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ 451 452 #define MXC_F_SPI_REVA_WKEN_RX_FULL_POS 3 /**< WKEN_RX_FULL Position */ 453 #define MXC_F_SPI_REVA_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ 454 455 /**@} end of group SPI_WKEN_Register */ 456 457 /** 458 * @ingroup spi_registers 459 * @defgroup SPI_STAT SPI_STAT 460 * @brief SPI Status register. 461 * @{ 462 */ 463 #define MXC_F_SPI_REVA_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ 464 #define MXC_F_SPI_REVA_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_REVA_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ 465 466 /**@} end of group SPI_STAT_Register */ 467 468 #ifdef __cplusplus 469 } 470 #endif 471 472 #endif /* _SPI_REVA_REGS_H_ */ 473
