1 /** 2 * @file spixr_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXR_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SPIXR_REVA_REGS_H_ 27 #define _SPIXR_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup spixr_reva 65 * @defgroup spixr_reva_registers SPIXR_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SPIXR_REVA Peripheral Module. 67 * @details SPIXR peripheral. 68 */ 69 70 /** 71 * @ingroup spixr_reva_registers 72 * Structure type to access the SPIXR_REVA Registers. 73 */ 74 typedef struct { 75 union{ 76 __IO uint32_t data32; /**< <tt>\b 0x00:</tt> SPIXR_REVA DATA32 Register */ 77 __IO uint16_t data16[2]; /**< <tt>\b 0x00:</tt> SPIXR_REVA DATA16 Register */ 78 __IO uint8_t data8[4]; /**< <tt>\b 0x00:</tt> SPIXR_REVA DATA8 Register */ 79 }; 80 __IO uint32_t ctrl1; /**< <tt>\b 0x04:</tt> SPIXR_REVA CTRL1 Register */ 81 __IO uint32_t ctrl2; /**< <tt>\b 0x08:</tt> SPIXR_REVA CTRL2 Register */ 82 __IO uint32_t ctrl3; /**< <tt>\b 0x0C:</tt> SPIXR_REVA CTRL3 Register */ 83 __IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPIXR_REVA SS_TIME Register */ 84 __IO uint32_t brg_ctrl; /**< <tt>\b 0x14:</tt> SPIXR_REVA BRG_CTRL Register */ 85 __R uint32_t rsv_0x18; 86 __IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPIXR_REVA DMA Register */ 87 __IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPIXR_REVA INT_FL Register */ 88 __IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPIXR_REVA INT_EN Register */ 89 __IO uint32_t wake_fl; /**< <tt>\b 0x28:</tt> SPIXR_REVA WAKE_FL Register */ 90 __IO uint32_t wake_en; /**< <tt>\b 0x2C:</tt> SPIXR_REVA WAKE_EN Register */ 91 __I uint32_t stat; /**< <tt>\b 0x30:</tt> SPIXR_REVA STAT Register */ 92 __IO uint32_t xmem_ctrl; /**< <tt>\b 0x34:</tt> SPIXR_REVA XMEM_CTRL Register */ 93 } mxc_spixr_reva_regs_t; 94 95 /* Register offsets for module SPIXR_REVA */ 96 /** 97 * @ingroup spixr_reva_registers 98 * @defgroup SPIXR_REVA_Register_Offsets Register Offsets 99 * @brief SPIXR_REVA Peripheral Register Offsets from the SPIXR_REVA Base Peripheral Address. 100 * @{ 101 */ 102 #define MXC_R_SPIXR_REVA_DATA32 ((uint32_t)0x00000000UL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x0000</tt> */ 103 #define MXC_R_SPIXR_REVA_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_SPIXR_REVA_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x0000</tt> */ 105 #define MXC_R_SPIXR_REVA_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x0004</tt> */ 106 #define MXC_R_SPIXR_REVA_CTRL2 ((uint32_t)0x00000008UL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x0008</tt> */ 107 #define MXC_R_SPIXR_REVA_CTRL3 ((uint32_t)0x0000000CUL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x000C</tt> */ 108 #define MXC_R_SPIXR_REVA_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x0010</tt> */ 109 #define MXC_R_SPIXR_REVA_BRG_CTRL ((uint32_t)0x00000014UL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x0014</tt> */ 110 #define MXC_R_SPIXR_REVA_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x001C</tt> */ 111 #define MXC_R_SPIXR_REVA_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x0020</tt> */ 112 #define MXC_R_SPIXR_REVA_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x0024</tt> */ 113 #define MXC_R_SPIXR_REVA_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x0028</tt> */ 114 #define MXC_R_SPIXR_REVA_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x002C</tt> */ 115 #define MXC_R_SPIXR_REVA_STAT ((uint32_t)0x00000030UL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x0030</tt> */ 116 #define MXC_R_SPIXR_REVA_XMEM_CTRL ((uint32_t)0x00000034UL) /**< Offset from SPIXR_REVA Base Address: <tt> 0x0034</tt> */ 117 /**@} end of group spixr_reva_registers */ 118 119 /** 120 * @ingroup spixr_reva_registers 121 * @defgroup SPIXR_REVA_DATA32 SPIXR_REVA_DATA32 122 * @brief Register for reading and writing the FIFO. 123 * @{ 124 */ 125 #define MXC_F_SPIXR_REVA_DATA32_DATA_POS 0 /**< DATA32_DATA Position */ 126 #define MXC_F_SPIXR_REVA_DATA32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPIXR_REVA_DATA32_DATA_POS)) /**< DATA32_DATA Mask */ 127 128 /**@} end of group SPIXR_REVA_DATA32_Register */ 129 130 /** 131 * @ingroup spixr_reva_registers 132 * @defgroup SPIXR_REVA_DATA16 SPIXR_REVA_DATA16 133 * @brief Register for reading and writing the FIFO. 134 * @{ 135 */ 136 #define MXC_F_SPIXR_REVA_DATA16_DATA_POS 0 /**< DATA16_DATA Position */ 137 #define MXC_F_SPIXR_REVA_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIXR_REVA_DATA16_DATA_POS)) /**< DATA16_DATA Mask */ 138 139 /**@} end of group SPIXR_REVA_DATA16_Register */ 140 141 /** 142 * @ingroup spixr_reva_registers 143 * @defgroup SPIXR_REVA_DATA8 SPIXR_REVA_DATA8 144 * @brief Register for reading and writing the FIFO. 145 * @{ 146 */ 147 #define MXC_F_SPIXR_REVA_DATA8_DATA_POS 0 /**< DATA8_DATA Position */ 148 #define MXC_F_SPIXR_REVA_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPIXR_REVA_DATA8_DATA_POS)) /**< DATA8_DATA Mask */ 149 150 /**@} end of group SPIXR_REVA_DATA8_Register */ 151 152 /** 153 * @ingroup spixr_reva_registers 154 * @defgroup SPIXR_REVA_CTRL1 SPIXR_REVA_CTRL1 155 * @brief Register for controlling SPI peripheral. 156 * @{ 157 */ 158 #define MXC_F_SPIXR_REVA_CTRL1_SPIEN_POS 0 /**< CTRL1_SPIEN Position */ 159 #define MXC_F_SPIXR_REVA_CTRL1_SPIEN ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_CTRL1_SPIEN_POS)) /**< CTRL1_SPIEN Mask */ 160 161 #define MXC_F_SPIXR_REVA_CTRL1_MMEN_POS 1 /**< CTRL1_MMEN Position */ 162 #define MXC_F_SPIXR_REVA_CTRL1_MMEN ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_CTRL1_MMEN_POS)) /**< CTRL1_MMEN Mask */ 163 164 #define MXC_F_SPIXR_REVA_CTRL1_SSIO_POS 4 /**< CTRL1_SSIO Position */ 165 #define MXC_F_SPIXR_REVA_CTRL1_SSIO ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_CTRL1_SSIO_POS)) /**< CTRL1_SSIO Mask */ 166 167 #define MXC_F_SPIXR_REVA_CTRL1_TX_START_POS 5 /**< CTRL1_TX_START Position */ 168 #define MXC_F_SPIXR_REVA_CTRL1_TX_START ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_CTRL1_TX_START_POS)) /**< CTRL1_TX_START Mask */ 169 170 #define MXC_F_SPIXR_REVA_CTRL1_SS_CTRL_POS 8 /**< CTRL1_SS_CTRL Position */ 171 #define MXC_F_SPIXR_REVA_CTRL1_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_CTRL1_SS_CTRL_POS)) /**< CTRL1_SS_CTRL Mask */ 172 173 #define MXC_F_SPIXR_REVA_CTRL1_SS_POS 16 /**< CTRL1_SS Position */ 174 #define MXC_F_SPIXR_REVA_CTRL1_SS ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_CTRL1_SS_POS)) /**< CTRL1_SS Mask */ 175 176 /**@} end of group SPIXR_REVA_CTRL1_Register */ 177 178 /** 179 * @ingroup spixr_reva_registers 180 * @defgroup SPIXR_REVA_CTRL2 SPIXR_REVA_CTRL2 181 * @brief Register for controlling SPI peripheral. 182 * @{ 183 */ 184 #define MXC_F_SPIXR_REVA_CTRL2_TX_NUM_CHAR_POS 0 /**< CTRL2_TX_NUM_CHAR Position */ 185 #define MXC_F_SPIXR_REVA_CTRL2_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_REVA_CTRL2_TX_NUM_CHAR_POS)) /**< CTRL2_TX_NUM_CHAR Mask */ 186 187 #define MXC_F_SPIXR_REVA_CTRL2_RX_NUM_CHAR_POS 16 /**< CTRL2_RX_NUM_CHAR Position */ 188 #define MXC_F_SPIXR_REVA_CTRL2_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_REVA_CTRL2_RX_NUM_CHAR_POS)) /**< CTRL2_RX_NUM_CHAR Mask */ 189 190 /**@} end of group SPIXR_REVA_CTRL2_Register */ 191 192 /** 193 * @ingroup spixr_reva_registers 194 * @defgroup SPIXR_REVA_CTRL3 SPIXR_REVA_CTRL3 195 * @brief Register for controlling SPI peripheral. 196 * @{ 197 */ 198 #define MXC_F_SPIXR_REVA_CTRL3_CPHA_POS 0 /**< CTRL3_CPHA Position */ 199 #define MXC_F_SPIXR_REVA_CTRL3_CPHA ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_CTRL3_CPHA_POS)) /**< CTRL3_CPHA Mask */ 200 201 #define MXC_F_SPIXR_REVA_CTRL3_CPOL_POS 1 /**< CTRL3_CPOL Position */ 202 #define MXC_F_SPIXR_REVA_CTRL3_CPOL ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_CTRL3_CPOL_POS)) /**< CTRL3_CPOL Mask */ 203 204 #define MXC_F_SPIXR_REVA_CTRL3_SCLK_FB_INV_POS 4 /**< CTRL3_SCLK_FB_INV Position */ 205 #define MXC_F_SPIXR_REVA_CTRL3_SCLK_FB_INV ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_CTRL3_SCLK_FB_INV_POS)) /**< CTRL3_SCLK_FB_INV Mask */ 206 207 #define MXC_F_SPIXR_REVA_CTRL3_NUMBITS_POS 8 /**< CTRL3_NUMBITS Position */ 208 #define MXC_F_SPIXR_REVA_CTRL3_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIXR_REVA_CTRL3_NUMBITS_POS)) /**< CTRL3_NUMBITS Mask */ 209 #define MXC_V_SPIXR_REVA_CTRL3_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL3_NUMBITS_0 Value */ 210 #define MXC_S_SPIXR_REVA_CTRL3_NUMBITS_0 (MXC_V_SPIXR_REVA_CTRL3_NUMBITS_0 << MXC_F_SPIXR_REVA_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_0 Setting */ 211 212 #define MXC_F_SPIXR_REVA_CTRL3_DATA_WIDTH_POS 12 /**< CTRL3_DATA_WIDTH Position */ 213 #define MXC_F_SPIXR_REVA_CTRL3_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXR_REVA_CTRL3_DATA_WIDTH_POS)) /**< CTRL3_DATA_WIDTH Mask */ 214 #define MXC_V_SPIXR_REVA_CTRL3_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL3_DATA_WIDTH_MONO Value */ 215 #define MXC_S_SPIXR_REVA_CTRL3_DATA_WIDTH_MONO (MXC_V_SPIXR_REVA_CTRL3_DATA_WIDTH_MONO << MXC_F_SPIXR_REVA_CTRL3_DATA_WIDTH_POS) /**< CTRL3_DATA_WIDTH_MONO Setting */ 216 #define MXC_V_SPIXR_REVA_CTRL3_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL3_DATA_WIDTH_DUAL Value */ 217 #define MXC_S_SPIXR_REVA_CTRL3_DATA_WIDTH_DUAL (MXC_V_SPIXR_REVA_CTRL3_DATA_WIDTH_DUAL << MXC_F_SPIXR_REVA_CTRL3_DATA_WIDTH_POS) /**< CTRL3_DATA_WIDTH_DUAL Setting */ 218 #define MXC_V_SPIXR_REVA_CTRL3_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL3_DATA_WIDTH_QUAD Value */ 219 #define MXC_S_SPIXR_REVA_CTRL3_DATA_WIDTH_QUAD (MXC_V_SPIXR_REVA_CTRL3_DATA_WIDTH_QUAD << MXC_F_SPIXR_REVA_CTRL3_DATA_WIDTH_POS) /**< CTRL3_DATA_WIDTH_QUAD Setting */ 220 221 #define MXC_F_SPIXR_REVA_CTRL3_THREE_WIRE_POS 15 /**< CTRL3_THREE_WIRE Position */ 222 #define MXC_F_SPIXR_REVA_CTRL3_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_CTRL3_THREE_WIRE_POS)) /**< CTRL3_THREE_WIRE Mask */ 223 224 #define MXC_F_SPIXR_REVA_CTRL3_SSPOL_POS 16 /**< CTRL3_SSPOL Position */ 225 #define MXC_F_SPIXR_REVA_CTRL3_SSPOL ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_CTRL3_SSPOL_POS)) /**< CTRL3_SSPOL Mask */ 226 227 /**@} end of group SPIXR_REVA_CTRL3_Register */ 228 229 /** 230 * @ingroup spixr_reva_registers 231 * @defgroup SPIXR_REVA_SS_TIME SPIXR_REVA_SS_TIME 232 * @brief Register for controlling SPI peripheral. 233 * @{ 234 */ 235 #define MXC_F_SPIXR_REVA_SS_TIME_SSACT1_POS 0 /**< SS_TIME_SSACT1 Position */ 236 #define MXC_F_SPIXR_REVA_SS_TIME_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPIXR_REVA_SS_TIME_SSACT1_POS)) /**< SS_TIME_SSACT1 Mask */ 237 #define MXC_V_SPIXR_REVA_SS_TIME_SSACT1_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT1_256 Value */ 238 #define MXC_S_SPIXR_REVA_SS_TIME_SSACT1_256 (MXC_V_SPIXR_REVA_SS_TIME_SSACT1_256 << MXC_F_SPIXR_REVA_SS_TIME_SSACT1_POS) /**< SS_TIME_SSACT1_256 Setting */ 239 240 #define MXC_F_SPIXR_REVA_SS_TIME_SSACT2_POS 8 /**< SS_TIME_SSACT2 Position */ 241 #define MXC_F_SPIXR_REVA_SS_TIME_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPIXR_REVA_SS_TIME_SSACT2_POS)) /**< SS_TIME_SSACT2 Mask */ 242 #define MXC_V_SPIXR_REVA_SS_TIME_SSACT2_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT2_256 Value */ 243 #define MXC_S_SPIXR_REVA_SS_TIME_SSACT2_256 (MXC_V_SPIXR_REVA_SS_TIME_SSACT2_256 << MXC_F_SPIXR_REVA_SS_TIME_SSACT2_POS) /**< SS_TIME_SSACT2_256 Setting */ 244 245 #define MXC_F_SPIXR_REVA_SS_TIME_SSINACT_POS 16 /**< SS_TIME_SSINACT Position */ 246 #define MXC_F_SPIXR_REVA_SS_TIME_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPIXR_REVA_SS_TIME_SSINACT_POS)) /**< SS_TIME_SSINACT Mask */ 247 #define MXC_V_SPIXR_REVA_SS_TIME_SSINACT_256 ((uint32_t)0x0UL) /**< SS_TIME_SSINACT_256 Value */ 248 #define MXC_S_SPIXR_REVA_SS_TIME_SSINACT_256 (MXC_V_SPIXR_REVA_SS_TIME_SSINACT_256 << MXC_F_SPIXR_REVA_SS_TIME_SSINACT_POS) /**< SS_TIME_SSINACT_256 Setting */ 249 250 /**@} end of group SPIXR_REVA_SS_TIME_Register */ 251 252 /** 253 * @ingroup spixr_reva_registers 254 * @defgroup SPIXR_REVA_BRG_CTRL SPIXR_REVA_BRG_CTRL 255 * @brief Register for controlling SPI clock rate. 256 * @{ 257 */ 258 #define MXC_F_SPIXR_REVA_BRG_CTRL_LOW_POS 0 /**< BRG_CTRL_LOW Position */ 259 #define MXC_F_SPIXR_REVA_BRG_CTRL_LOW ((uint32_t)(0xFFUL << MXC_F_SPIXR_REVA_BRG_CTRL_LOW_POS)) /**< BRG_CTRL_LOW Mask */ 260 #define MXC_V_SPIXR_REVA_BRG_CTRL_LOW_DIS ((uint32_t)0x0UL) /**< BRG_CTRL_LOW_DIS Value */ 261 #define MXC_S_SPIXR_REVA_BRG_CTRL_LOW_DIS (MXC_V_SPIXR_REVA_BRG_CTRL_LOW_DIS << MXC_F_SPIXR_REVA_BRG_CTRL_LOW_POS) /**< BRG_CTRL_LOW_DIS Setting */ 262 263 #define MXC_F_SPIXR_REVA_BRG_CTRL_HI_POS 8 /**< BRG_CTRL_HI Position */ 264 #define MXC_F_SPIXR_REVA_BRG_CTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPIXR_REVA_BRG_CTRL_HI_POS)) /**< BRG_CTRL_HI Mask */ 265 #define MXC_V_SPIXR_REVA_BRG_CTRL_HI_DIS ((uint32_t)0x0UL) /**< BRG_CTRL_HI_DIS Value */ 266 #define MXC_S_SPIXR_REVA_BRG_CTRL_HI_DIS (MXC_V_SPIXR_REVA_BRG_CTRL_HI_DIS << MXC_F_SPIXR_REVA_BRG_CTRL_HI_POS) /**< BRG_CTRL_HI_DIS Setting */ 267 268 #define MXC_F_SPIXR_REVA_BRG_CTRL_SCALE_POS 16 /**< BRG_CTRL_SCALE Position */ 269 #define MXC_F_SPIXR_REVA_BRG_CTRL_SCALE ((uint32_t)(0xFUL << MXC_F_SPIXR_REVA_BRG_CTRL_SCALE_POS)) /**< BRG_CTRL_SCALE Mask */ 270 271 /**@} end of group SPIXR_REVA_BRG_CTRL_Register */ 272 273 /** 274 * @ingroup spixr_reva_registers 275 * @defgroup SPIXR_REVA_DMA SPIXR_REVA_DMA 276 * @brief Register for controlling DMA. 277 * @{ 278 */ 279 #define MXC_F_SPIXR_REVA_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ 280 #define MXC_F_SPIXR_REVA_DMA_TX_FIFO_LEVEL ((uint32_t)(0x3FUL << MXC_F_SPIXR_REVA_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ 281 282 #define MXC_F_SPIXR_REVA_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ 283 #define MXC_F_SPIXR_REVA_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ 284 285 #define MXC_F_SPIXR_REVA_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ 286 #define MXC_F_SPIXR_REVA_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ 287 288 #define MXC_F_SPIXR_REVA_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ 289 #define MXC_F_SPIXR_REVA_DMA_TX_FIFO_CNT ((uint32_t)(0x1FUL << MXC_F_SPIXR_REVA_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ 290 291 #define MXC_F_SPIXR_REVA_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ 292 #define MXC_F_SPIXR_REVA_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ 293 294 #define MXC_F_SPIXR_REVA_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ 295 #define MXC_F_SPIXR_REVA_DMA_RX_FIFO_LEVEL ((uint32_t)(0x3FUL << MXC_F_SPIXR_REVA_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ 296 297 #define MXC_F_SPIXR_REVA_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ 298 #define MXC_F_SPIXR_REVA_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ 299 300 #define MXC_F_SPIXR_REVA_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ 301 #define MXC_F_SPIXR_REVA_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ 302 303 #define MXC_F_SPIXR_REVA_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ 304 #define MXC_F_SPIXR_REVA_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXR_REVA_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ 305 306 #define MXC_F_SPIXR_REVA_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ 307 #define MXC_F_SPIXR_REVA_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ 308 309 /**@} end of group SPIXR_REVA_DMA_Register */ 310 311 /** 312 * @ingroup spixr_reva_registers 313 * @defgroup SPIXR_REVA_INT_FL SPIXR_REVA_INT_FL 314 * @brief Register for reading and clearing interrupt flags. All bits are write 1 to 315 * clear. 316 * @{ 317 */ 318 #define MXC_F_SPIXR_REVA_INT_FL_TX_THRESH_POS 0 /**< INT_FL_TX_THRESH Position */ 319 #define MXC_F_SPIXR_REVA_INT_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_TX_THRESH_POS)) /**< INT_FL_TX_THRESH Mask */ 320 321 #define MXC_F_SPIXR_REVA_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */ 322 #define MXC_F_SPIXR_REVA_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */ 323 324 #define MXC_F_SPIXR_REVA_INT_FL_RX_THRESH_POS 2 /**< INT_FL_RX_THRESH Position */ 325 #define MXC_F_SPIXR_REVA_INT_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_RX_THRESH_POS)) /**< INT_FL_RX_THRESH Mask */ 326 327 #define MXC_F_SPIXR_REVA_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */ 328 #define MXC_F_SPIXR_REVA_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */ 329 330 #define MXC_F_SPIXR_REVA_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */ 331 #define MXC_F_SPIXR_REVA_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */ 332 333 #define MXC_F_SPIXR_REVA_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */ 334 #define MXC_F_SPIXR_REVA_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */ 335 336 #define MXC_F_SPIXR_REVA_INT_FL_FAULT_POS 8 /**< INT_FL_FAULT Position */ 337 #define MXC_F_SPIXR_REVA_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_FAULT_POS)) /**< INT_FL_FAULT Mask */ 338 339 #define MXC_F_SPIXR_REVA_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */ 340 #define MXC_F_SPIXR_REVA_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */ 341 342 #define MXC_F_SPIXR_REVA_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */ 343 #define MXC_F_SPIXR_REVA_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */ 344 345 #define MXC_F_SPIXR_REVA_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */ 346 #define MXC_F_SPIXR_REVA_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */ 347 348 #define MXC_F_SPIXR_REVA_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */ 349 #define MXC_F_SPIXR_REVA_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */ 350 351 #define MXC_F_SPIXR_REVA_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */ 352 #define MXC_F_SPIXR_REVA_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ 353 354 #define MXC_F_SPIXR_REVA_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */ 355 #define MXC_F_SPIXR_REVA_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */ 356 357 /**@} end of group SPIXR_REVA_INT_FL_Register */ 358 359 /** 360 * @ingroup spixr_reva_registers 361 * @defgroup SPIXR_REVA_INT_EN SPIXR_REVA_INT_EN 362 * @brief Register for enabling interrupts. 363 * @{ 364 */ 365 #define MXC_F_SPIXR_REVA_INT_EN_TX_THRESH_POS 0 /**< INT_EN_TX_THRESH Position */ 366 #define MXC_F_SPIXR_REVA_INT_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_TX_THRESH_POS)) /**< INT_EN_TX_THRESH Mask */ 367 368 #define MXC_F_SPIXR_REVA_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */ 369 #define MXC_F_SPIXR_REVA_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */ 370 371 #define MXC_F_SPIXR_REVA_INT_EN_RX_THRESH_POS 2 /**< INT_EN_RX_THRESH Position */ 372 #define MXC_F_SPIXR_REVA_INT_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_RX_THRESH_POS)) /**< INT_EN_RX_THRESH Mask */ 373 374 #define MXC_F_SPIXR_REVA_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */ 375 #define MXC_F_SPIXR_REVA_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */ 376 377 #define MXC_F_SPIXR_REVA_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */ 378 #define MXC_F_SPIXR_REVA_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */ 379 380 #define MXC_F_SPIXR_REVA_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */ 381 #define MXC_F_SPIXR_REVA_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */ 382 383 #define MXC_F_SPIXR_REVA_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */ 384 #define MXC_F_SPIXR_REVA_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */ 385 386 #define MXC_F_SPIXR_REVA_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */ 387 #define MXC_F_SPIXR_REVA_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */ 388 389 #define MXC_F_SPIXR_REVA_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */ 390 #define MXC_F_SPIXR_REVA_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */ 391 392 #define MXC_F_SPIXR_REVA_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */ 393 #define MXC_F_SPIXR_REVA_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */ 394 395 #define MXC_F_SPIXR_REVA_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */ 396 #define MXC_F_SPIXR_REVA_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */ 397 398 #define MXC_F_SPIXR_REVA_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */ 399 #define MXC_F_SPIXR_REVA_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */ 400 401 #define MXC_F_SPIXR_REVA_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */ 402 #define MXC_F_SPIXR_REVA_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */ 403 404 /**@} end of group SPIXR_REVA_INT_EN_Register */ 405 406 /** 407 * @ingroup spixr_reva_registers 408 * @defgroup SPIXR_REVA_WAKE_FL SPIXR_REVA_WAKE_FL 409 * @brief Register for wake up flags. All bits in this register are write 1 to clear. 410 * @{ 411 */ 412 #define MXC_F_SPIXR_REVA_WAKE_FL_TX_THRESH_POS 0 /**< WAKE_FL_TX_THRESH Position */ 413 #define MXC_F_SPIXR_REVA_WAKE_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_WAKE_FL_TX_THRESH_POS)) /**< WAKE_FL_TX_THRESH Mask */ 414 415 #define MXC_F_SPIXR_REVA_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */ 416 #define MXC_F_SPIXR_REVA_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */ 417 418 #define MXC_F_SPIXR_REVA_WAKE_FL_RX_THRESH_POS 2 /**< WAKE_FL_RX_THRESH Position */ 419 #define MXC_F_SPIXR_REVA_WAKE_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_WAKE_FL_RX_THRESH_POS)) /**< WAKE_FL_RX_THRESH Mask */ 420 421 #define MXC_F_SPIXR_REVA_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */ 422 #define MXC_F_SPIXR_REVA_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */ 423 424 /**@} end of group SPIXR_REVA_WAKE_FL_Register */ 425 426 /** 427 * @ingroup spixr_reva_registers 428 * @defgroup SPIXR_REVA_WAKE_EN SPIXR_REVA_WAKE_EN 429 * @brief Register for wake up enable. 430 * @{ 431 */ 432 #define MXC_F_SPIXR_REVA_WAKE_EN_TX_THRESH_POS 0 /**< WAKE_EN_TX_THRESH Position */ 433 #define MXC_F_SPIXR_REVA_WAKE_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_WAKE_EN_TX_THRESH_POS)) /**< WAKE_EN_TX_THRESH Mask */ 434 435 #define MXC_F_SPIXR_REVA_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */ 436 #define MXC_F_SPIXR_REVA_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */ 437 438 #define MXC_F_SPIXR_REVA_WAKE_EN_RX_THRESH_POS 2 /**< WAKE_EN_RX_THRESH Position */ 439 #define MXC_F_SPIXR_REVA_WAKE_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_WAKE_EN_RX_THRESH_POS)) /**< WAKE_EN_RX_THRESH Mask */ 440 441 #define MXC_F_SPIXR_REVA_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */ 442 #define MXC_F_SPIXR_REVA_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */ 443 444 /**@} end of group SPIXR_REVA_WAKE_EN_Register */ 445 446 /** 447 * @ingroup spixr_reva_registers 448 * @defgroup SPIXR_REVA_STAT SPIXR_REVA_STAT 449 * @brief SPI Status register. 450 * @{ 451 */ 452 #define MXC_F_SPIXR_REVA_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ 453 #define MXC_F_SPIXR_REVA_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ 454 455 /**@} end of group SPIXR_REVA_STAT_Register */ 456 457 /** 458 * @ingroup spixr_reva_registers 459 * @defgroup SPIXR_REVA_XMEM_CTRL SPIXR_REVA_XMEM_CTRL 460 * @brief Register to control external memory. 461 * @{ 462 */ 463 #define MXC_F_SPIXR_REVA_XMEM_CTRL_RD_CMD_POS 0 /**< XMEM_CTRL_RD_CMD Position */ 464 #define MXC_F_SPIXR_REVA_XMEM_CTRL_RD_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_REVA_XMEM_CTRL_RD_CMD_POS)) /**< XMEM_CTRL_RD_CMD Mask */ 465 466 #define MXC_F_SPIXR_REVA_XMEM_CTRL_WR_CMD_POS 8 /**< XMEM_CTRL_WR_CMD Position */ 467 #define MXC_F_SPIXR_REVA_XMEM_CTRL_WR_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_REVA_XMEM_CTRL_WR_CMD_POS)) /**< XMEM_CTRL_WR_CMD Mask */ 468 469 #define MXC_F_SPIXR_REVA_XMEM_CTRL_DUMMY_CLK_POS 16 /**< XMEM_CTRL_DUMMY_CLK Position */ 470 #define MXC_F_SPIXR_REVA_XMEM_CTRL_DUMMY_CLK ((uint32_t)(0xFFUL << MXC_F_SPIXR_REVA_XMEM_CTRL_DUMMY_CLK_POS)) /**< XMEM_CTRL_DUMMY_CLK Mask */ 471 472 #define MXC_F_SPIXR_REVA_XMEM_CTRL_XMEM_EN_POS 31 /**< XMEM_CTRL_XMEM_EN Position */ 473 #define MXC_F_SPIXR_REVA_XMEM_CTRL_XMEM_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_REVA_XMEM_CTRL_XMEM_EN_POS)) /**< XMEM_CTRL_XMEM_EN Mask */ 474 475 /**@} end of group SPIXR_REVA_XMEM_CTRL_Register */ 476 477 #ifdef __cplusplus 478 } 479 #endif 480 481 #endif /* _SPIXR_REVA_REGS_H_ */ 482
