1 /** 2 * @file spixfm_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXFM_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SPIXFM_REVA_REGS_H_ 27 #define _SPIXFM_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup spixfm_reva 65 * @defgroup spixfm_reva_registers SPIXFM_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SPIXFM_REVA Peripheral Module. 67 * @details SPIXF Master 68 */ 69 70 /** 71 * @ingroup spixfm_reva_registers 72 * Structure type to access the SPIXFM_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t cfg; /**< <tt>\b 0x00:</tt> SPIXFM_REVA CFG Register */ 76 __IO uint32_t fetch_ctrl; /**< <tt>\b 0x04:</tt> SPIXFM_REVA FETCH_CTRL Register */ 77 __IO uint32_t mode_ctrl; /**< <tt>\b 0x08:</tt> SPIXFM_REVA MODE_CTRL Register */ 78 __IO uint32_t mode_data; /**< <tt>\b 0x0C:</tt> SPIXFM_REVA MODE_DATA Register */ 79 __IO uint32_t fb_ctrl; /**< <tt>\b 0x10:</tt> SPIXFM_REVA FB_CTRL Register */ 80 __R uint32_t rsv_0x14_0x1b[2]; 81 __IO uint32_t io_ctrl; /**< <tt>\b 0x1C:</tt> SPIXFM_REVA IO_CTRL Register */ 82 __IO uint32_t sec_ctrl; /**< <tt>\b 0x20:</tt> SPIXFM_REVA SEC_CTRL Register */ 83 __IO uint32_t bus_idle; /**< <tt>\b 0x24:</tt> SPIXFM_REVA BUS_IDLE Register */ 84 } mxc_spixfm_reva_regs_t; 85 86 /* Register offsets for module SPIXFM_REVA */ 87 /** 88 * @ingroup spixfm_reva_registers 89 * @defgroup SPIXFM_REVA_Register_Offsets Register Offsets 90 * @brief SPIXFM_REVA Peripheral Register Offsets from the SPIXFM_REVA Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_SPIXFM_REVA_CFG ((uint32_t)0x00000000UL) /**< Offset from SPIXFM_REVA Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_SPIXFM_REVA_FETCH_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIXFM_REVA Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_SPIXFM_REVA_MODE_CTRL ((uint32_t)0x00000008UL) /**< Offset from SPIXFM_REVA Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_SPIXFM_REVA_MODE_DATA ((uint32_t)0x0000000CUL) /**< Offset from SPIXFM_REVA Base Address: <tt> 0x000C</tt> */ 97 #define MXC_R_SPIXFM_REVA_FB_CTRL ((uint32_t)0x00000010UL) /**< Offset from SPIXFM_REVA Base Address: <tt> 0x0010</tt> */ 98 #define MXC_R_SPIXFM_REVA_IO_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIXFM_REVA Base Address: <tt> 0x001C</tt> */ 99 #define MXC_R_SPIXFM_REVA_SEC_CTRL ((uint32_t)0x00000020UL) /**< Offset from SPIXFM_REVA Base Address: <tt> 0x0020</tt> */ 100 #define MXC_R_SPIXFM_REVA_BUS_IDLE ((uint32_t)0x00000024UL) /**< Offset from SPIXFM_REVA Base Address: <tt> 0x0024</tt> */ 101 /**@} end of group spixfm_reva_registers */ 102 103 /** 104 * @ingroup spixfm_reva_registers 105 * @defgroup SPIXFM_REVA_CFG SPIXFM_REVA_CFG 106 * @brief SPIX Configuration Register. 107 * @{ 108 */ 109 #define MXC_F_SPIXFM_REVA_CFG_MODE_POS 0 /**< CFG_MODE Position */ 110 #define MXC_F_SPIXFM_REVA_CFG_MODE ((uint32_t)(0x3UL << MXC_F_SPIXFM_REVA_CFG_MODE_POS)) /**< CFG_MODE Mask */ 111 #define MXC_V_SPIXFM_REVA_CFG_MODE_SCLK_HI_SAMPLE_RISING ((uint32_t)0x0UL) /**< CFG_MODE_SCLK_HI_SAMPLE_RISING Value */ 112 #define MXC_S_SPIXFM_REVA_CFG_MODE_SCLK_HI_SAMPLE_RISING (MXC_V_SPIXFM_REVA_CFG_MODE_SCLK_HI_SAMPLE_RISING << MXC_F_SPIXFM_REVA_CFG_MODE_POS) /**< CFG_MODE_SCLK_HI_SAMPLE_RISING Setting */ 113 #define MXC_V_SPIXFM_REVA_CFG_MODE_SCLK_LO_SAMPLE_FAILLING ((uint32_t)0x3UL) /**< CFG_MODE_SCLK_LO_SAMPLE_FAILLING Value */ 114 #define MXC_S_SPIXFM_REVA_CFG_MODE_SCLK_LO_SAMPLE_FAILLING (MXC_V_SPIXFM_REVA_CFG_MODE_SCLK_LO_SAMPLE_FAILLING << MXC_F_SPIXFM_REVA_CFG_MODE_POS) /**< CFG_MODE_SCLK_LO_SAMPLE_FAILLING Setting */ 115 116 #define MXC_F_SPIXFM_REVA_CFG_SSPOL_POS 2 /**< CFG_SSPOL Position */ 117 #define MXC_F_SPIXFM_REVA_CFG_SSPOL ((uint32_t)(0x1UL << MXC_F_SPIXFM_REVA_CFG_SSPOL_POS)) /**< CFG_SSPOL Mask */ 118 119 #define MXC_F_SPIXFM_REVA_CFG_SSEL_POS 4 /**< CFG_SSEL Position */ 120 #define MXC_F_SPIXFM_REVA_CFG_SSEL ((uint32_t)(0x7UL << MXC_F_SPIXFM_REVA_CFG_SSEL_POS)) /**< CFG_SSEL Mask */ 121 122 #define MXC_F_SPIXFM_REVA_CFG_LO_CLK_POS 8 /**< CFG_LO_CLK Position */ 123 #define MXC_F_SPIXFM_REVA_CFG_LO_CLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_REVA_CFG_LO_CLK_POS)) /**< CFG_LO_CLK Mask */ 124 125 #define MXC_F_SPIXFM_REVA_CFG_HI_CLK_POS 12 /**< CFG_HI_CLK Position */ 126 #define MXC_F_SPIXFM_REVA_CFG_HI_CLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_REVA_CFG_HI_CLK_POS)) /**< CFG_HI_CLK Mask */ 127 128 #define MXC_F_SPIXFM_REVA_CFG_SSACT_POS 16 /**< CFG_SSACT Position */ 129 #define MXC_F_SPIXFM_REVA_CFG_SSACT ((uint32_t)(0x3UL << MXC_F_SPIXFM_REVA_CFG_SSACT_POS)) /**< CFG_SSACT Mask */ 130 #define MXC_V_SPIXFM_REVA_CFG_SSACT_OFF ((uint32_t)0x0UL) /**< CFG_SSACT_OFF Value */ 131 #define MXC_S_SPIXFM_REVA_CFG_SSACT_OFF (MXC_V_SPIXFM_REVA_CFG_SSACT_OFF << MXC_F_SPIXFM_REVA_CFG_SSACT_POS) /**< CFG_SSACT_OFF Setting */ 132 #define MXC_V_SPIXFM_REVA_CFG_SSACT_FOR_2_MOD_CLK ((uint32_t)0x1UL) /**< CFG_SSACT_FOR_2_MOD_CLK Value */ 133 #define MXC_S_SPIXFM_REVA_CFG_SSACT_FOR_2_MOD_CLK (MXC_V_SPIXFM_REVA_CFG_SSACT_FOR_2_MOD_CLK << MXC_F_SPIXFM_REVA_CFG_SSACT_POS) /**< CFG_SSACT_FOR_2_MOD_CLK Setting */ 134 #define MXC_V_SPIXFM_REVA_CFG_SSACT_FOR_4_MOD_CLK ((uint32_t)0x2UL) /**< CFG_SSACT_FOR_4_MOD_CLK Value */ 135 #define MXC_S_SPIXFM_REVA_CFG_SSACT_FOR_4_MOD_CLK (MXC_V_SPIXFM_REVA_CFG_SSACT_FOR_4_MOD_CLK << MXC_F_SPIXFM_REVA_CFG_SSACT_POS) /**< CFG_SSACT_FOR_4_MOD_CLK Setting */ 136 #define MXC_V_SPIXFM_REVA_CFG_SSACT_FOR_8_MOD_CLK ((uint32_t)0x3UL) /**< CFG_SSACT_FOR_8_MOD_CLK Value */ 137 #define MXC_S_SPIXFM_REVA_CFG_SSACT_FOR_8_MOD_CLK (MXC_V_SPIXFM_REVA_CFG_SSACT_FOR_8_MOD_CLK << MXC_F_SPIXFM_REVA_CFG_SSACT_POS) /**< CFG_SSACT_FOR_8_MOD_CLK Setting */ 138 139 #define MXC_F_SPIXFM_REVA_CFG_SSIACT_POS 18 /**< CFG_SSIACT Position */ 140 #define MXC_F_SPIXFM_REVA_CFG_SSIACT ((uint32_t)(0x3UL << MXC_F_SPIXFM_REVA_CFG_SSIACT_POS)) /**< CFG_SSIACT Mask */ 141 #define MXC_V_SPIXFM_REVA_CFG_SSIACT_FOR_1_MOD_CLK ((uint32_t)0x0UL) /**< CFG_SSIACT_FOR_1_MOD_CLK Value */ 142 #define MXC_S_SPIXFM_REVA_CFG_SSIACT_FOR_1_MOD_CLK (MXC_V_SPIXFM_REVA_CFG_SSIACT_FOR_1_MOD_CLK << MXC_F_SPIXFM_REVA_CFG_SSIACT_POS) /**< CFG_SSIACT_FOR_1_MOD_CLK Setting */ 143 #define MXC_V_SPIXFM_REVA_CFG_SSIACT_FOR_3_MOD_CLK ((uint32_t)0x1UL) /**< CFG_SSIACT_FOR_3_MOD_CLK Value */ 144 #define MXC_S_SPIXFM_REVA_CFG_SSIACT_FOR_3_MOD_CLK (MXC_V_SPIXFM_REVA_CFG_SSIACT_FOR_3_MOD_CLK << MXC_F_SPIXFM_REVA_CFG_SSIACT_POS) /**< CFG_SSIACT_FOR_3_MOD_CLK Setting */ 145 #define MXC_V_SPIXFM_REVA_CFG_SSIACT_FOR_5_MOD_CLK ((uint32_t)0x2UL) /**< CFG_SSIACT_FOR_5_MOD_CLK Value */ 146 #define MXC_S_SPIXFM_REVA_CFG_SSIACT_FOR_5_MOD_CLK (MXC_V_SPIXFM_REVA_CFG_SSIACT_FOR_5_MOD_CLK << MXC_F_SPIXFM_REVA_CFG_SSIACT_POS) /**< CFG_SSIACT_FOR_5_MOD_CLK Setting */ 147 #define MXC_V_SPIXFM_REVA_CFG_SSIACT_FOR_9_MOD_CLK ((uint32_t)0x3UL) /**< CFG_SSIACT_FOR_9_MOD_CLK Value */ 148 #define MXC_S_SPIXFM_REVA_CFG_SSIACT_FOR_9_MOD_CLK (MXC_V_SPIXFM_REVA_CFG_SSIACT_FOR_9_MOD_CLK << MXC_F_SPIXFM_REVA_CFG_SSIACT_POS) /**< CFG_SSIACT_FOR_9_MOD_CLK Setting */ 149 150 /**@} end of group SPIXFM_REVA_CFG_Register */ 151 152 /** 153 * @ingroup spixfm_reva_registers 154 * @defgroup SPIXFM_REVA_FETCH_CTRL SPIXFM_REVA_FETCH_CTRL 155 * @brief SPIX Fetch Control Register. 156 * @{ 157 */ 158 #define MXC_F_SPIXFM_REVA_FETCH_CTRL_CMDVAL_POS 0 /**< FETCH_CTRL_CMDVAL Position */ 159 #define MXC_F_SPIXFM_REVA_FETCH_CTRL_CMDVAL ((uint32_t)(0xFFUL << MXC_F_SPIXFM_REVA_FETCH_CTRL_CMDVAL_POS)) /**< FETCH_CTRL_CMDVAL Mask */ 160 161 #define MXC_F_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_POS 8 /**< FETCH_CTRL_CMD_WIDTH Position */ 162 #define MXC_F_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_POS)) /**< FETCH_CTRL_CMD_WIDTH Mask */ 163 #define MXC_V_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCH_CTRL_CMD_WIDTH_SINGLE Value */ 164 #define MXC_S_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_SINGLE (MXC_V_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_SINGLE << MXC_F_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_POS) /**< FETCH_CTRL_CMD_WIDTH_SINGLE Setting */ 165 #define MXC_V_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCH_CTRL_CMD_WIDTH_DUAL_IO Value */ 166 #define MXC_S_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_DUAL_IO (MXC_V_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_DUAL_IO << MXC_F_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_POS) /**< FETCH_CTRL_CMD_WIDTH_DUAL_IO Setting */ 167 #define MXC_V_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCH_CTRL_CMD_WIDTH_QUAD_IO Value */ 168 #define MXC_S_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_QUAD_IO (MXC_V_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_QUAD_IO << MXC_F_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_POS) /**< FETCH_CTRL_CMD_WIDTH_QUAD_IO Setting */ 169 #define MXC_V_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCH_CTRL_CMD_WIDTH_INVALID Value */ 170 #define MXC_S_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_INVALID (MXC_V_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_INVALID << MXC_F_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_POS) /**< FETCH_CTRL_CMD_WIDTH_INVALID Setting */ 171 172 #define MXC_F_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_POS 10 /**< FETCH_CTRL_ADDR_WIDTH Position */ 173 #define MXC_F_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_POS)) /**< FETCH_CTRL_ADDR_WIDTH Mask */ 174 #define MXC_V_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCH_CTRL_ADDR_WIDTH_SINGLE Value */ 175 #define MXC_S_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_SINGLE (MXC_V_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_SINGLE Setting */ 176 #define MXC_V_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCH_CTRL_ADDR_WIDTH_DUAL_IO Value */ 177 #define MXC_S_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_DUAL_IO (MXC_V_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_DUAL_IO Setting */ 178 #define MXC_V_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCH_CTRL_ADDR_WIDTH_QUAD_IO Value */ 179 #define MXC_S_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_QUAD_IO (MXC_V_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_QUAD_IO Setting */ 180 #define MXC_V_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCH_CTRL_ADDR_WIDTH_INVALID Value */ 181 #define MXC_S_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_INVALID (MXC_V_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_INVALID << MXC_F_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_INVALID Setting */ 182 183 #define MXC_F_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_POS 12 /**< FETCH_CTRL_DATA_WIDTH Position */ 184 #define MXC_F_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_POS)) /**< FETCH_CTRL_DATA_WIDTH Mask */ 185 #define MXC_V_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCH_CTRL_DATA_WIDTH_SINGLE Value */ 186 #define MXC_S_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_SINGLE (MXC_V_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_SINGLE Setting */ 187 #define MXC_V_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCH_CTRL_DATA_WIDTH_DUAL_IO Value */ 188 #define MXC_S_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_DUAL_IO (MXC_V_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_DUAL_IO Setting */ 189 #define MXC_V_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCH_CTRL_DATA_WIDTH_QUAD_IO Value */ 190 #define MXC_S_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_QUAD_IO (MXC_V_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_QUAD_IO Setting */ 191 #define MXC_V_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCH_CTRL_DATA_WIDTH_INVALID Value */ 192 #define MXC_S_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_INVALID (MXC_V_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_INVALID << MXC_F_SPIXFM_REVA_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_INVALID Setting */ 193 194 #define MXC_F_SPIXFM_REVA_FETCH_CTRL_FOUR_BYTE_ADDR_POS 16 /**< FETCH_CTRL_FOUR_BYTE_ADDR Position */ 195 #define MXC_F_SPIXFM_REVA_FETCH_CTRL_FOUR_BYTE_ADDR ((uint32_t)(0x1UL << MXC_F_SPIXFM_REVA_FETCH_CTRL_FOUR_BYTE_ADDR_POS)) /**< FETCH_CTRL_FOUR_BYTE_ADDR Mask */ 196 197 /**@} end of group SPIXFM_REVA_FETCH_CTRL_Register */ 198 199 /** 200 * @ingroup spixfm_reva_registers 201 * @defgroup SPIXFM_REVA_MODE_CTRL SPIXFM_REVA_MODE_CTRL 202 * @brief SPIX Mode Control Register. 203 * @{ 204 */ 205 #define MXC_F_SPIXFM_REVA_MODE_CTRL_MDCLK_POS 0 /**< MODE_CTRL_MDCLK Position */ 206 #define MXC_F_SPIXFM_REVA_MODE_CTRL_MDCLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_REVA_MODE_CTRL_MDCLK_POS)) /**< MODE_CTRL_MDCLK Mask */ 207 208 #define MXC_F_SPIXFM_REVA_MODE_CTRL_NO_CMD_POS 8 /**< MODE_CTRL_NO_CMD Position */ 209 #define MXC_F_SPIXFM_REVA_MODE_CTRL_NO_CMD ((uint32_t)(0x1UL << MXC_F_SPIXFM_REVA_MODE_CTRL_NO_CMD_POS)) /**< MODE_CTRL_NO_CMD Mask */ 210 211 #define MXC_F_SPIXFM_REVA_MODE_CTRL_MODE_SEND_POS 9 /**< MODE_CTRL_MODE_SEND Position */ 212 #define MXC_F_SPIXFM_REVA_MODE_CTRL_MODE_SEND ((uint32_t)(0x1UL << MXC_F_SPIXFM_REVA_MODE_CTRL_MODE_SEND_POS)) /**< MODE_CTRL_MODE_SEND Mask */ 213 214 /**@} end of group SPIXFM_REVA_MODE_CTRL_Register */ 215 216 /** 217 * @ingroup spixfm_reva_registers 218 * @defgroup SPIXFM_REVA_MODE_DATA SPIXFM_REVA_MODE_DATA 219 * @brief SPIX Mode Data Register. 220 * @{ 221 */ 222 #define MXC_F_SPIXFM_REVA_MODE_DATA_DATA_POS 0 /**< MODE_DATA_DATA Position */ 223 #define MXC_F_SPIXFM_REVA_MODE_DATA_DATA ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_REVA_MODE_DATA_DATA_POS)) /**< MODE_DATA_DATA Mask */ 224 225 #define MXC_F_SPIXFM_REVA_MODE_DATA_OUT_EN_POS 16 /**< MODE_DATA_OUT_EN Position */ 226 #define MXC_F_SPIXFM_REVA_MODE_DATA_OUT_EN ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_REVA_MODE_DATA_OUT_EN_POS)) /**< MODE_DATA_OUT_EN Mask */ 227 228 /**@} end of group SPIXFM_REVA_MODE_DATA_Register */ 229 230 /** 231 * @ingroup spixfm_reva_registers 232 * @defgroup SPIXFM_REVA_FB_CTRL SPIXFM_REVA_FB_CTRL 233 * @brief SPIX Feedback Control Register. 234 * @{ 235 */ 236 #define MXC_F_SPIXFM_REVA_FB_CTRL_FB_EN_POS 0 /**< FB_CTRL_FB_EN Position */ 237 #define MXC_F_SPIXFM_REVA_FB_CTRL_FB_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_REVA_FB_CTRL_FB_EN_POS)) /**< FB_CTRL_FB_EN Mask */ 238 239 #define MXC_F_SPIXFM_REVA_FB_CTRL_INVERT_EN_POS 1 /**< FB_CTRL_INVERT_EN Position */ 240 #define MXC_F_SPIXFM_REVA_FB_CTRL_INVERT_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_REVA_FB_CTRL_INVERT_EN_POS)) /**< FB_CTRL_INVERT_EN Mask */ 241 242 /**@} end of group SPIXFM_REVA_FB_CTRL_Register */ 243 244 /** 245 * @ingroup spixfm_reva_registers 246 * @defgroup SPIXFM_REVA_IO_CTRL SPIXFM_REVA_IO_CTRL 247 * @brief SPIX IO Control Register. 248 * @{ 249 */ 250 #define MXC_F_SPIXFM_REVA_IO_CTRL_SCLK_DS_POS 0 /**< IO_CTRL_SCLK_DS Position */ 251 #define MXC_F_SPIXFM_REVA_IO_CTRL_SCLK_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_REVA_IO_CTRL_SCLK_DS_POS)) /**< IO_CTRL_SCLK_DS Mask */ 252 253 #define MXC_F_SPIXFM_REVA_IO_CTRL_SS_DS_POS 1 /**< IO_CTRL_SS_DS Position */ 254 #define MXC_F_SPIXFM_REVA_IO_CTRL_SS_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_REVA_IO_CTRL_SS_DS_POS)) /**< IO_CTRL_SS_DS Mask */ 255 256 #define MXC_F_SPIXFM_REVA_IO_CTRL_SDIO_DS_POS 2 /**< IO_CTRL_SDIO_DS Position */ 257 #define MXC_F_SPIXFM_REVA_IO_CTRL_SDIO_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_REVA_IO_CTRL_SDIO_DS_POS)) /**< IO_CTRL_SDIO_DS Mask */ 258 259 #define MXC_F_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_POS 3 /**< IO_CTRL_PU_PD_CTRL Position */ 260 #define MXC_F_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL ((uint32_t)(0x3UL << MXC_F_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_POS)) /**< IO_CTRL_PU_PD_CTRL Mask */ 261 #define MXC_V_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_TRI_STATE ((uint32_t)0x0UL) /**< IO_CTRL_PU_PD_CTRL_TRI_STATE Value */ 262 #define MXC_S_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_TRI_STATE (MXC_V_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_TRI_STATE << MXC_F_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_POS) /**< IO_CTRL_PU_PD_CTRL_TRI_STATE Setting */ 263 #define MXC_V_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_PULL_UP ((uint32_t)0x1UL) /**< IO_CTRL_PU_PD_CTRL_PULL_UP Value */ 264 #define MXC_S_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_PULL_UP (MXC_V_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_PULL_UP << MXC_F_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_POS) /**< IO_CTRL_PU_PD_CTRL_PULL_UP Setting */ 265 #define MXC_V_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_PULL_DOWN ((uint32_t)0x2UL) /**< IO_CTRL_PU_PD_CTRL_PULL_DOWN Value */ 266 #define MXC_S_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_PULL_DOWN (MXC_V_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_PULL_DOWN << MXC_F_SPIXFM_REVA_IO_CTRL_PU_PD_CTRL_POS) /**< IO_CTRL_PU_PD_CTRL_PULL_DOWN Setting */ 267 268 /**@} end of group SPIXFM_REVA_IO_CTRL_Register */ 269 270 /** 271 * @ingroup spixfm_reva_registers 272 * @defgroup SPIXFM_REVA_SEC_CTRL SPIXFM_REVA_SEC_CTRL 273 * @brief SPIX Memory Security Control Register. 274 * @{ 275 */ 276 #define MXC_F_SPIXFM_REVA_SEC_CTRL_DEC_EN_POS 0 /**< SEC_CTRL_DEC_EN Position */ 277 #define MXC_F_SPIXFM_REVA_SEC_CTRL_DEC_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_REVA_SEC_CTRL_DEC_EN_POS)) /**< SEC_CTRL_DEC_EN Mask */ 278 279 #define MXC_F_SPIXFM_REVA_SEC_CTRL_AUTH_DISABLE_POS 1 /**< SEC_CTRL_AUTH_DISABLE Position */ 280 #define MXC_F_SPIXFM_REVA_SEC_CTRL_AUTH_DISABLE ((uint32_t)(0x1UL << MXC_F_SPIXFM_REVA_SEC_CTRL_AUTH_DISABLE_POS)) /**< SEC_CTRL_AUTH_DISABLE Mask */ 281 282 /**@} end of group SPIXFM_REVA_SEC_CTRL_Register */ 283 284 /** 285 * @ingroup spixfm_reva_registers 286 * @defgroup SPIXFM_REVA_BUS_IDLE SPIXFM_REVA_BUS_IDLE 287 * @brief Bus Idle 288 * @{ 289 */ 290 #define MXC_F_SPIXFM_REVA_BUS_IDLE_BUSIDLE_POS 0 /**< BUS_IDLE_BUSIDLE Position */ 291 #define MXC_F_SPIXFM_REVA_BUS_IDLE_BUSIDLE ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_REVA_BUS_IDLE_BUSIDLE_POS)) /**< BUS_IDLE_BUSIDLE Mask */ 292 293 /**@} end of group SPIXFM_REVA_BUS_IDLE_Register */ 294 295 #ifdef __cplusplus 296 } 297 #endif 298 299 #endif /* _SPIXFM_REVA_REGS_H_ */ 300
